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charset="utf-8" The "qup-memory" interconnect path is optional and may not be defined in all device trees. Unroll the loop-based ICC path initialization to allow specific error handling for each path type. The "qup-core" and "qup-config" paths remain mandatory and will fail probe if missing, while "qup-memory" is now handled as optional and skipped when not present in the device tree. Co-developed-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Praveen Talari --- v1->v2: Bjorn: - Updated commit text. - Used local variable for more readable. --- drivers/soc/qcom/qcom-geni-se.c | 36 +++++++++++++++++---------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-s= e.c index cd1779b6a91a..b6167b968ef6 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -899,30 +899,32 @@ EXPORT_SYMBOL_GPL(geni_se_rx_dma_unprep); =20 int geni_icc_get(struct geni_se *se, const char *icc_ddr) { - int i, err; - const char *icc_names[] =3D {"qup-core", "qup-config", icc_ddr}; + struct geni_icc_path *icc_paths =3D se->icc_paths; =20 if (has_acpi_companion(se->dev)) return 0; =20 - for (i =3D 0; i < ARRAY_SIZE(se->icc_paths); i++) { - if (!icc_names[i]) - continue; - - se->icc_paths[i].path =3D devm_of_icc_get(se->dev, icc_names[i]); - if (IS_ERR(se->icc_paths[i].path)) - goto err; + icc_paths[GENI_TO_CORE].path =3D devm_of_icc_get(se->dev, "qup-core"); + if (IS_ERR(icc_paths[GENI_TO_CORE].path)) + return dev_err_probe(se->dev, PTR_ERR(icc_paths[GENI_TO_CORE].path), + "Failed to get 'qup-core' ICC path\n"); + + icc_paths[CPU_TO_GENI].path =3D devm_of_icc_get(se->dev, "qup-config"); + if (IS_ERR(icc_paths[CPU_TO_GENI].path)) + return dev_err_probe(se->dev, PTR_ERR(icc_paths[CPU_TO_GENI].path), + "Failed to get 'qup-config' ICC path\n"); + + /* The DDR path is optional, depending on protocol and hw capabilities */ + icc_paths[GENI_TO_DDR].path =3D devm_of_icc_get(se->dev, "qup-memory"); + if (IS_ERR(icc_paths[GENI_TO_DDR].path)) { + if (PTR_ERR(icc_paths[GENI_TO_DDR].path) =3D=3D -ENODATA) + icc_paths[GENI_TO_DDR].path =3D NULL; + else + return dev_err_probe(se->dev, PTR_ERR(icc_paths[GENI_TO_DDR].path), + "Failed to get 'qup-memory' ICC path\n"); } =20 return 0; - -err: - err =3D PTR_ERR(se->icc_paths[i].path); - if (err !=3D -EPROBE_DEFER) - dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n", - icc_names[i], err); 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Sun, 28 Dec 2025 20:55:12 -0800 (PST) Received: from hu-ptalari-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7ff7dfac29bsm27902080b3a.39.2025.12.28.20.55.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Dec 2025 20:55:11 -0800 (PST) From: Praveen Talari To: Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mukesh Kumar Savaliya , Viken Dadhaniya , Bjorn Andersson , Konrad Dybcio , Praveen Talari , linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alexey.klimov@linaro.org, krzk@kernel.org, bryan.odonoghue@linaro.org, jorge.ramirez@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com Cc: psodagud@quicinc.com, djaggi@quicinc.com, quic_msavaliy@quicinc.com, quic_vtanuku@quicinc.com, quic_arandive@quicinc.com, quic_shazhuss@quicinc.com, quic_cchiluve@quicinc.com, Konrad Dybcio Subject: [PATCH v2 02/12] soc: qcom: geni-se: Add geni_icc_set_bw_ab() function Date: Mon, 29 Dec 2025 10:24:36 +0530 Message-Id: <20251229045446.3227667-3-praveen.talari@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251229045446.3227667-1-praveen.talari@oss.qualcomm.com> References: <20251229045446.3227667-1-praveen.talari@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: -32nMboaXPq0_2_4iqVCUVKz9YLl6xdd X-Authority-Analysis: v=2.4 cv=O4o0fR9W c=1 sm=1 tr=0 ts=695209b1 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=BVB3BO4C9w_THQaB-9MA:9 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: -32nMboaXPq0_2_4iqVCUVKz9YLl6xdd X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI5MDA0MiBTYWx0ZWRfX1nPHxuAtFPVW SH93BL4NeGtHZXpOfdk6NaHqZ77saDajfSPCPhY3/K7Od6s++pO5LKrUdlYt5fcby/4Sw011FpS +NzfsbcB3zL1e6HQBm4Eq5tSz5p5PPV4P1SOu7QbFGhm2QGZA3qoToCIjlY/+7mflQMEEjcr1q6 mp0vZhaYu7KHPx3OwmKC+VGWM45C7UETVJzUmtNWqt656tIrkWbTBM9UalfWtWMwv3EFEpwzViN 0ldJl8jkiT85yeOHyJiAr+lZ6/+dIoOAgkJuPCL9xU9z2oRUg+rh4FUP5JxCGES16/oBUPn3m9E 5ssVcWOfQck01O4BVkcboFZSX4dQHJB3guYnBjKLgbeO4gKVVLfTSXFsxKJm1QSJQOO5wshYbom WLX1gye7CiHR2K0Nck1OsDLfDkrBDJFzkY8bprorWjOXgNc9x/0lo3RGIR19GwCh/MXtNuaSkRW dmMWS2O/YCZEx79e0Ag== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-29_01,2025-12-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 clxscore=1015 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512290042 Content-Type: text/plain; charset="utf-8" Add a new function geni_icc_set_bw_ab() that allows callers to set average bandwidth values for all ICC (Interconnect) paths in a single call. This function takes separate parameters for core, config, and DDR average bandwidth values and applies them to the respective ICC paths. This provides a more convenient API for drivers that need to configure specific average bandwidth values. Co-developed-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Praveen Talari --- drivers/soc/qcom/qcom-geni-se.c | 22 ++++++++++++++++++++++ include/linux/soc/qcom/geni-se.h | 1 + 2 files changed, 23 insertions(+) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-s= e.c index b6167b968ef6..b0542f836453 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -946,6 +946,28 @@ int geni_icc_set_bw(struct geni_se *se) } EXPORT_SYMBOL_GPL(geni_icc_set_bw); =20 +/** + * geni_icc_set_bw_ab() - Set average bandwidth for all ICC paths and apply + * @se: Pointer to the concerned serial engine. + * @core_ab: Average bandwidth in kBps for GENI_TO_CORE path. + * @cfg_ab: Average bandwidth in kBps for CPU_TO_GENI path. + * @ddr_ab: Average bandwidth in kBps for GENI_TO_DDR path. + * + * Sets bandwidth values for all ICC paths and applies them. DDR path is + * optional and only set if it exists. + * + * Return: 0 on success, negative error code on failure. + */ +int geni_icc_set_bw_ab(struct geni_se *se, u32 core_ab, u32 cfg_ab, u32 dd= r_ab) +{ + se->icc_paths[GENI_TO_CORE].avg_bw =3D core_ab; + se->icc_paths[CPU_TO_GENI].avg_bw =3D cfg_ab; + se->icc_paths[GENI_TO_DDR].avg_bw =3D ddr_ab; + + return geni_icc_set_bw(se); +} +EXPORT_SYMBOL_GPL(geni_icc_set_bw_ab); + void geni_icc_set_tag(struct geni_se *se, u32 tag) { int i; diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni= -se.h index 0a984e2579fe..980aabea2157 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -528,6 +528,7 @@ void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr= _t iova, size_t len); int geni_icc_get(struct geni_se *se, const char *icc_ddr); =20 int geni_icc_set_bw(struct geni_se *se); +int geni_icc_set_bw_ab(struct geni_se *se, u32 core_ab, u32 cfg_ab, u32 dd= r_ab); void geni_icc_set_tag(struct geni_se *se, u32 tag); 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charset="utf-8" The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently duplicate code for initializing shared resources such as clocks and interconnect paths. Introduce a new helper API, geni_se_resources_init(), to centralize this initialization logic, improving modularity and simplifying the probe function. Signed-off-by: Praveen Talari --- v1 -> v2: From kernel test robot - Updated proper return value for devm_pm_opp_set_clkname() --- drivers/soc/qcom/qcom-geni-se.c | 47 ++++++++++++++++++++++++++++++++ include/linux/soc/qcom/geni-se.h | 6 ++++ 2 files changed, 53 insertions(+) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-s= e.c index b0542f836453..75e722cd1a94 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -19,6 +19,7 @@ #include #include #include +#include #include =20 /** @@ -1012,6 +1013,52 @@ int geni_icc_disable(struct geni_se *se) } EXPORT_SYMBOL_GPL(geni_icc_disable); =20 +/** + * geni_se_resources_init() - Initialize resources for a GENI SE device. + * @se: Pointer to the geni_se structure representing the GENI SE device. + * + * This function initializes various resources required by the GENI Serial= Engine + * (SE) device, including clock resources (core and SE clocks), interconne= ct + * paths for communication. + * It retrieves optional and mandatory clock resources, adds an OF-based + * operating performance point (OPP) table, and sets up interconnect paths + * with default bandwidths. The function also sets a flag (`has_opp`) to + * indicate whether OPP support is available for the device. + * + * Return: 0 on success, or a negative errno on failure. + */ +int geni_se_resources_init(struct geni_se *se) +{ + int ret; + + se->core_clk =3D devm_clk_get_optional(se->dev, "core"); + if (IS_ERR(se->core_clk)) + return dev_err_probe(se->dev, PTR_ERR(se->core_clk), + "Failed to get optional core clk\n"); + + se->clk =3D devm_clk_get(se->dev, "se"); + if (IS_ERR(se->clk) && !has_acpi_companion(se->dev)) + return dev_err_probe(se->dev, PTR_ERR(se->clk), + "Failed to get SE clk\n"); + + ret =3D devm_pm_opp_set_clkname(se->dev, "se"); + if (ret) + return ret; + + ret =3D devm_pm_opp_of_add_table(se->dev); + if (ret && ret !=3D -ENODEV) + return dev_err_probe(se->dev, ret, "Failed to add OPP table\n"); + + se->has_opp =3D (ret =3D=3D 0); + + ret =3D geni_icc_get(se, "qup-memory"); + if (ret) + return ret; + + return geni_icc_set_bw_ab(se, GENI_DEFAULT_BW, GENI_DEFAULT_BW, GENI_DEFA= ULT_BW); +} +EXPORT_SYMBOL_GPL(geni_se_resources_init); + /** * geni_find_protocol_fw() - Locate and validate SE firmware for a protoco= l. * @dev: Pointer to the device structure. diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni= -se.h index 980aabea2157..c182dd0f0bde 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -60,18 +60,22 @@ struct geni_icc_path { * @dev: Pointer to the Serial Engine device * @wrapper: Pointer to the parent QUP Wrapper core * @clk: Handle to the core serial engine clock + * @core_clk: Auxiliary clock, which may be required by a protocol * @num_clk_levels: Number of valid clock levels in clk_perf_tbl * @clk_perf_tbl: Table of clock frequency input to serial engine clock * @icc_paths: Array of ICC paths for SE + * @has_opp: Indicates if OPP is supported */ struct geni_se { void __iomem *base; struct device *dev; struct geni_wrapper *wrapper; struct clk *clk; + struct clk *core_clk; unsigned int num_clk_levels; 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charset="utf-8" The GENI SE protocol drivers (I2C, SPI, UART) implement similar resource activation/deactivation sequences independently, leading to code duplication. Introduce geni_se_resources_activate()/geni_se_resources_deactivate() to power on/off resources.The activate function enables ICC, clocks, and TLMM whereas the deactivate function disables resources in reverse order including OPP rate reset, clocks, ICC and TLMM. Signed-off-by: Praveen Talari --- v1 -> v2 Bjorn - Updated commit message based code changes. - Removed geni_se_resource_state() API. - Utilized code snippet from geni_se_resources_off() --- drivers/soc/qcom/qcom-geni-se.c | 77 ++++++++++++++++++++++++++++++++ include/linux/soc/qcom/geni-se.h | 4 ++ 2 files changed, 81 insertions(+) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-s= e.c index 75e722cd1a94..fbffbc9ea7a6 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -1013,6 +1013,83 @@ int geni_icc_disable(struct geni_se *se) } EXPORT_SYMBOL_GPL(geni_icc_disable); =20 +/** + * geni_se_resources_deactivate() - Deactivate GENI SE device resources + * @se: Pointer to the geni_se structure + * + * Deactivates device resources for power saving: OPP rate to 0, pin contr= ol + * to sleep state, turns off clocks, and disables interconnect. Skips ACPI= devices. + * + * Return: 0 on success, negative error code on failure + */ +int geni_se_resources_deactivate(struct geni_se *se) +{ + int ret; + + if (has_acpi_companion(se->dev)) + return 0; + + if (se->has_opp) + dev_pm_opp_set_rate(se->dev, 0); + + ret =3D pinctrl_pm_select_sleep_state(se->dev); + if (ret) + return ret; + + geni_se_clks_off(se); + + if (se->core_clk) + clk_disable_unprepare(se->core_clk); + + return geni_icc_disable(se); +} + +/** + * geni_se_resources_activate() - Activate GENI SE device resources + * @se: Pointer to the geni_se structure + * + * Activates device resources for operation: enables interconnect, prepare= s clocks, + * and sets pin control to default state. Includes error cleanup. Skips AC= PI devices. + * + * Return: 0 on success, negative error code on failure + */ +int geni_se_resources_activate(struct geni_se *se) +{ + int ret; + + if (has_acpi_companion(se->dev)) + return 0; + + ret =3D geni_icc_enable(se); + if (ret) + return ret; + + if (se->core_clk) { + ret =3D clk_prepare_enable(se->core_clk); + if (ret) + goto out_icc_disable; + } + + ret =3D geni_se_clks_on(se); + if (ret) + goto out_clk_disable; + + ret =3D pinctrl_pm_select_default_state(se->dev); + if (ret) { + geni_se_clks_off(se); + goto out_clk_disable; + } + + return ret; + +out_clk_disable: + if (se->core_clk) + clk_disable_unprepare(se->core_clk); +out_icc_disable: + geni_icc_disable(se); + return ret; +} + /** * geni_se_resources_init() - Initialize resources for a GENI SE device. * @se: Pointer to the geni_se structure representing the GENI SE device. diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni= -se.h index c182dd0f0bde..36a68149345c 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -541,6 +541,10 @@ int geni_icc_disable(struct geni_se *se); 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charset="utf-8" The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently handle the attachment of power domains. This often leads to duplicated code logic across different driver probe functions. Introduce a new helper API, geni_se_domain_attach(), to centralize the logic for attaching "power" and "perf" domains to the GENI SE device. Signed-off-by: Praveen Talari --- drivers/soc/qcom/qcom-geni-se.c | 29 +++++++++++++++++++++++++++++ include/linux/soc/qcom/geni-se.h | 4 ++++ 2 files changed, 33 insertions(+) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-s= e.c index fbffbc9ea7a6..decf7cf5172e 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include =20 @@ -1090,6 +1091,34 @@ int geni_se_resources_activate(struct geni_se *se) return ret; } =20 +/** + * geni_se_domain_attach() - Attach power domains to a GENI SE device. + * @se: Pointer to the geni_se structure representing the GENI SE device. + * + * This function attaches the necessary power domains ("power" and "perf") + * to the GENI Serial Engine device. It initializes `se->pd_list` with the + * attached domains. + * + * Return: 0 on success, or a negative error code on failure. + */ +int geni_se_domain_attach(struct geni_se *se) +{ + struct dev_pm_domain_attach_data pd_data =3D { + .pd_flags =3D PD_FLAG_DEV_LINK_ON, + .pd_names =3D (const char*[]) { "power", "perf" }, + .num_pd_names =3D 2, + }; + int ret; + + ret =3D dev_pm_domain_attach_list(se->dev, + &pd_data, &se->pd_list); + if (ret <=3D 0) + return -EINVAL; + + return 0; +} +EXPORT_SYMBOL_GPL(geni_se_domain_attach); + /** * geni_se_resources_init() - Initialize resources for a GENI SE device. * @se: Pointer to the geni_se structure representing the GENI SE device. diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni= -se.h index 36a68149345c..5f75159c5531 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -64,6 +64,7 @@ struct geni_icc_path { * @num_clk_levels: Number of valid clock levels in clk_perf_tbl * @clk_perf_tbl: Table of clock frequency input to serial engine clock * @icc_paths: Array of ICC paths for SE + * @pd_list: Power domain list for managing power domains * @has_opp: Indicates if OPP is supported */ struct geni_se { @@ -75,6 +76,7 @@ struct geni_se { unsigned int num_clk_levels; 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charset="utf-8" The GENI Serial Engine (SE) drivers (I2C, SPI, and SERIAL) currently manage performance levels and operating points directly. This resulting in code duplication across drivers. such as configuring a specific level or find and apply an OPP based on a clock frequency. Introduce two new helper APIs, geni_se_set_perf_level() and geni_se_set_perf_opp(), addresses this issue by providing a streamlined method for the GENI Serial Engine (SE) drivers to find and set the OPP based on the desired performance level, thereby eliminating redundancy. Signed-off-by: Praveen Talari --- drivers/soc/qcom/qcom-geni-se.c | 50 ++++++++++++++++++++++++++++++++ include/linux/soc/qcom/geni-se.h | 4 +++ 2 files changed, 54 insertions(+) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-s= e.c index decf7cf5172e..fd63cc6a7faf 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -282,6 +282,12 @@ struct se_fw_hdr { #define geni_setbits32(_addr, _v) writel(readl(_addr) | (_v), _addr) #define geni_clrbits32(_addr, _v) writel(readl(_addr) & ~(_v), _addr) =20 +enum domain_idx { + DOMAIN_IDX_POWER, + DOMAIN_IDX_PERF, + DOMAIN_IDX_MAX +}; + /** * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version * @se: Pointer to the corresponding serial engine. @@ -1091,6 +1097,50 @@ int geni_se_resources_activate(struct geni_se *se) return ret; } =20 +/** + * geni_se_set_perf_level() - Set performance level for GENI SE. + * @se: Pointer to the struct geni_se instance. + * @level: The desired performance level. + * + * Sets the performance level by directly calling dev_pm_opp_set_level + * on the performance device associated with the SE. + * + * Return: 0 on success, or a negative error code on failure. + */ +int geni_se_set_perf_level(struct geni_se *se, unsigned long level) +{ + return dev_pm_opp_set_level(se->pd_list->pd_devs[DOMAIN_IDX_PERF], level); +} +EXPORT_SYMBOL_GPL(geni_se_set_perf_level); + +/** + * geni_se_set_perf_opp() - Set performance OPP for GENI SE by frequency. + * @se: Pointer to the struct geni_se instance. + * @clk_freq: The requested clock frequency. + * + * Finds the nearest operating performance point (OPP) for the given + * clock frequency and applies it to the SE's performance device. + * + * Return: 0 on success, or a negative error code on failure. + */ +int geni_se_set_perf_opp(struct geni_se *se, unsigned long clk_freq) +{ + struct device *perf_dev =3D se->pd_list->pd_devs[DOMAIN_IDX_PERF]; + struct dev_pm_opp *opp; + int ret; + + opp =3D dev_pm_opp_find_freq_floor(perf_dev, &clk_freq); + if (IS_ERR(opp)) { + dev_err(se->dev, "failed to find opp for freq %lu\n", clk_freq); + return PTR_ERR(opp); + } + + ret =3D dev_pm_opp_set_opp(perf_dev, opp); + dev_pm_opp_put(opp); + return ret; +} +EXPORT_SYMBOL_GPL(geni_se_set_perf_opp); + /** * geni_se_domain_attach() - Attach power domains to a GENI SE device. * @se: Pointer to the geni_se structure representing the GENI SE device. diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni= -se.h index 5f75159c5531..c5e6ab85df09 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -550,5 +550,9 @@ int geni_se_resources_deactivate(struct geni_se *se); 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charset="utf-8" Add DT bindings for the QUP GENI I2C controller on sa8255p platforms. SA8255p platform abstracts resources such as clocks, interconnect and GPIO pins configuration in Firmware. SCMI power and perf protocol are utilized to request resource configurations. SA8255p platform does not require the Serial Engine (SE) common properties as the SE firmware is loaded and managed by the TrustZone (TZ) secure environment. Co-developed-by: Nikunj Kela Signed-off-by: Nikunj Kela Signed-off-by: Praveen Talari Reviewed-by: Krzysztof Kozlowski --- v1->v2: Krzysztof: - Added dma properties in example node - Removed minItems from power-domains property - Added in commit text about common property --- .../bindings/i2c/qcom,sa8255p-geni-i2c.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni= -i2c.yaml diff --git a/Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.ya= ml b/Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml new file mode 100644 index 000000000000..a61e40b5cbc1 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/qcom,sa8255p-geni-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SA8255p QUP GENI I2C Controller + +maintainers: + - Praveen Talari + +properties: + compatible: + const: qcom,sa8255p-geni-i2c + + reg: + maxItems: 1 + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 2 + + power-domain-names: + items: + - const: power + - const: perf + +required: + - compatible + - reg + - interrupts + - power-domains + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + i2c@a90000 { + compatible =3D "qcom,sa8255p-geni-i2c"; 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charset="utf-8" Moving the serial engine setup to geni_i2c_init() API for a cleaner probe function and utilizes the PM runtime API to control resources instead of direct clock-related APIs for better resource management. Enables reusability of the serial engine initialization like hibernation and deep sleep features where hardware context is lost. Signed-off-by: Praveen Talari --- v1->v2: Bjorn: - Updated commit text. --- drivers/i2c/busses/i2c-qcom-geni.c | 154 ++++++++++++++--------------- 1 file changed, 73 insertions(+), 81 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qc= om-geni.c index 3a04016db2c3..58c32ffbd150 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -976,10 +976,75 @@ static int setup_gpi_dma(struct geni_i2c_dev *gi2c) return ret; } =20 +static int geni_i2c_init(struct geni_i2c_dev *gi2c) +{ + const struct geni_i2c_desc *desc =3D NULL; + u32 proto, tx_depth; + bool fifo_disable; + int ret; + + ret =3D pm_runtime_resume_and_get(gi2c->se.dev); + if (ret < 0) { + dev_err(gi2c->se.dev, "error turning on device :%d\n", ret); + return ret; + } + + proto =3D geni_se_read_proto(&gi2c->se); + if (proto =3D=3D GENI_SE_INVALID_PROTO) { + ret =3D geni_load_se_firmware(&gi2c->se, GENI_SE_I2C); + if (ret) { + dev_err_probe(gi2c->se.dev, ret, "i2c firmware load failed ret: %d\n", = ret); + goto err; + } + } else if (proto !=3D GENI_SE_I2C) { + ret =3D dev_err_probe(gi2c->se.dev, -ENXIO, "Invalid proto %d\n", proto); + goto err; + } + + desc =3D device_get_match_data(gi2c->se.dev); + if (desc && desc->no_dma_support) + fifo_disable =3D false; + else + fifo_disable =3D readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIF= O_IF_DISABLE; + + if (fifo_disable) { + /* FIFO is disabled, so we can only use GPI DMA */ + gi2c->gpi_mode =3D true; + ret =3D setup_gpi_dma(gi2c); + if (ret) + goto err; + + dev_dbg(gi2c->se.dev, "Using GPI DMA mode for I2C\n"); + } else { + gi2c->gpi_mode =3D false; + tx_depth =3D geni_se_get_tx_fifo_depth(&gi2c->se); + + /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */ + if (!tx_depth && desc) + tx_depth =3D desc->tx_fifo_depth; + + if (!tx_depth) { + ret =3D dev_err_probe(gi2c->se.dev, -EINVAL, + "Invalid TX FIFO depth\n"); + goto err; + } + + gi2c->tx_wm =3D tx_depth - 1; + geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth); + geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, + PACKING_BYTES_PW, true, true, true); + + dev_dbg(gi2c->se.dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth); + } + +err: + pm_runtime_put(gi2c->se.dev); + return ret; +} + static int geni_i2c_probe(struct platform_device *pdev) { struct geni_i2c_dev *gi2c; - u32 proto, tx_depth, fifo_disable; int ret; struct device *dev =3D &pdev->dev; const struct geni_i2c_desc *desc =3D NULL; @@ -1059,100 +1124,27 @@ static int geni_i2c_probe(struct platform_device *= pdev) if (ret) return ret; =20 - ret =3D clk_prepare_enable(gi2c->core_clk); - if (ret) - return ret; - - ret =3D geni_se_resources_on(&gi2c->se); - if (ret) { - dev_err_probe(dev, ret, "Error turning on resources\n"); - goto err_clk; - } - proto =3D geni_se_read_proto(&gi2c->se); - if (proto =3D=3D GENI_SE_INVALID_PROTO) { - ret =3D geni_load_se_firmware(&gi2c->se, GENI_SE_I2C); - if (ret) { - dev_err_probe(dev, ret, "i2c firmware load failed ret: %d\n", ret); - goto err_resources; - } - } else if (proto !=3D GENI_SE_I2C) { - ret =3D dev_err_probe(dev, -ENXIO, "Invalid proto %d\n", proto); - goto err_resources; - } - - if (desc && desc->no_dma_support) - fifo_disable =3D false; - else - fifo_disable =3D readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIF= O_IF_DISABLE; - - if (fifo_disable) { - /* FIFO is disabled, so we can only use GPI DMA */ - gi2c->gpi_mode =3D true; - ret =3D setup_gpi_dma(gi2c); - if (ret) - goto err_resources; - - dev_dbg(dev, "Using GPI DMA mode for I2C\n"); - } else { - gi2c->gpi_mode =3D false; - tx_depth =3D geni_se_get_tx_fifo_depth(&gi2c->se); - - /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */ - if (!tx_depth && desc) - tx_depth =3D desc->tx_fifo_depth; - - if (!tx_depth) { - ret =3D dev_err_probe(dev, -EINVAL, - "Invalid TX FIFO depth\n"); - goto err_resources; - } - - gi2c->tx_wm =3D tx_depth - 1; - geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth); - geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, - PACKING_BYTES_PW, true, true, true); - - dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth); - } - - clk_disable_unprepare(gi2c->core_clk); - ret =3D geni_se_resources_off(&gi2c->se); - if (ret) { - dev_err_probe(dev, ret, "Error turning off resources\n"); - goto err_dma; - } - - ret =3D geni_icc_disable(&gi2c->se); - if (ret) - goto err_dma; - gi2c->suspended =3D 1; pm_runtime_set_suspended(gi2c->se.dev); pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY); pm_runtime_use_autosuspend(gi2c->se.dev); pm_runtime_enable(gi2c->se.dev); =20 + ret =3D geni_i2c_init(gi2c); + if (ret < 0) { + pm_runtime_disable(gi2c->se.dev); + return ret; + } + ret =3D i2c_add_adapter(&gi2c->adap); if (ret) { dev_err_probe(dev, ret, "Error adding i2c adapter\n"); pm_runtime_disable(gi2c->se.dev); - goto err_dma; + return ret; } =20 dev_dbg(dev, "Geni-I2C adaptor successfully added\n"); =20 - return ret; - -err_resources: - geni_se_resources_off(&gi2c->se); -err_clk: - clk_disable_unprepare(gi2c->core_clk); - - return ret; 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charset="utf-8" Refactor the resource initialization in geni_i2c_probe() by introducing a new geni_i2c_resources_init() function and utilizing the common geni_se_resources_init() framework and clock frequency mapping, making the probe function cleaner. Signed-off-by: Praveen Talari --- v1->v2: - Updated commit text. --- drivers/i2c/busses/i2c-qcom-geni.c | 53 ++++++++++++------------------ 1 file changed, 21 insertions(+), 32 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qc= om-geni.c index 58c32ffbd150..a4b13022e508 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -1042,6 +1042,23 @@ static int geni_i2c_init(struct geni_i2c_dev *gi2c) return ret; } =20 +static int geni_i2c_resources_init(struct geni_i2c_dev *gi2c) +{ + int ret; + + ret =3D geni_se_resources_init(&gi2c->se); + if (ret) + return ret; + + ret =3D geni_i2c_clk_map_idx(gi2c); + if (ret) + return dev_err_probe(gi2c->se.dev, ret, "Invalid clk frequency %d Hz\n", + gi2c->clk_freq_out); + + return geni_icc_set_bw_ab(&gi2c->se, GENI_DEFAULT_BW, GENI_DEFAULT_BW, + Bps_to_icc(gi2c->clk_freq_out)); +} + static int geni_i2c_probe(struct platform_device *pdev) { struct geni_i2c_dev *gi2c; @@ -1061,16 +1078,6 @@ static int geni_i2c_probe(struct platform_device *pd= ev) =20 desc =3D device_get_match_data(&pdev->dev); =20 - if (desc && desc->has_core_clk) { - gi2c->core_clk =3D devm_clk_get(dev, "core"); - if (IS_ERR(gi2c->core_clk)) - return PTR_ERR(gi2c->core_clk); - } - - gi2c->se.clk =3D devm_clk_get(dev, "se"); - if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev)) - return PTR_ERR(gi2c->se.clk); - ret =3D device_property_read_u32(dev, "clock-frequency", &gi2c->clk_freq_out); if (ret) { @@ -1085,16 +1092,15 @@ static int geni_i2c_probe(struct platform_device *p= dev) if (gi2c->irq < 0) return gi2c->irq; =20 - ret =3D geni_i2c_clk_map_idx(gi2c); - if (ret) - return dev_err_probe(dev, ret, "Invalid clk frequency %d Hz\n", - gi2c->clk_freq_out); - gi2c->adap.algo =3D &geni_i2c_algo; init_completion(&gi2c->done); spin_lock_init(&gi2c->lock); platform_set_drvdata(pdev, gi2c); =20 + ret =3D geni_i2c_resources_init(gi2c); + if (ret) + return ret; + /* Keep interrupts disabled initially to allow for low-power modes */ ret =3D devm_request_irq(dev, gi2c->irq, geni_i2c_irq, IRQF_NO_AUTOEN, dev_name(dev), gi2c); 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charset="utf-8" To manage GENI serial engine resources during runtime power management, drivers currently need to call functions for ICC, clock, and SE resource operations in both suspend and resume paths, resulting in code duplication across drivers. The new geni_se_resources_activate() and geni_se_resources_deactivate() helper APIs addresses this issue by providing a streamlined method to enable or disable all resources based, thereby eliminating redundancy across drivers. Signed-off-by: Praveen Talari --- v1->v2: Bjorn: - Remove geni_se_resources_state() API. - Used geni_se_resources_activate() and geni_se_resources_deactivate() to enable/disable resources. --- drivers/i2c/busses/i2c-qcom-geni.c | 28 +++++----------------------- 1 file changed, 5 insertions(+), 23 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qc= om-geni.c index a4b13022e508..b0a18e3d57d9 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -1160,18 +1160,15 @@ static int __maybe_unused geni_i2c_runtime_suspend(= struct device *dev) struct geni_i2c_dev *gi2c =3D dev_get_drvdata(dev); =20 disable_irq(gi2c->irq); - ret =3D geni_se_resources_off(&gi2c->se); + + ret =3D geni_se_resources_deactivate(&gi2c->se); if (ret) { enable_irq(gi2c->irq); return ret; - - } else { - gi2c->suspended =3D 1; } =20 - clk_disable_unprepare(gi2c->core_clk); - - return geni_icc_disable(&gi2c->se); + gi2c->suspended =3D 1; + return ret; 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charset="utf-8" To avoid repeatedly fetching and checking platform data across various functions, store the struct of_device_id data directly in the i2c private structure. This change enhances code maintainability and reduces redundancy. Signed-off-by: Praveen Talari --- drivers/i2c/busses/i2c-qcom-geni.c | 32 ++++++++++++++++-------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qc= om-geni.c index b0a18e3d57d9..1c9356e13b97 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -77,6 +77,13 @@ enum geni_i2c_err_code { #define XFER_TIMEOUT HZ #define RST_TIMEOUT HZ =20 +struct geni_i2c_desc { + bool has_core_clk; + char *icc_ddr; + bool no_dma_support; + unsigned int tx_fifo_depth; +}; + #define QCOM_I2C_MIN_NUM_OF_MSGS_MULTI_DESC 2 =20 /** @@ -121,13 +128,7 @@ struct geni_i2c_dev { bool is_tx_multi_desc_xfer; u32 num_msgs; struct geni_i2c_gpi_multi_desc_xfer i2c_multi_desc_config; -}; - -struct geni_i2c_desc { - bool has_core_clk; - char *icc_ddr; - bool no_dma_support; - unsigned int tx_fifo_depth; + const struct geni_i2c_desc *dev_data; }; =20 struct geni_i2c_err_log { @@ -978,7 +979,6 @@ static int setup_gpi_dma(struct geni_i2c_dev *gi2c) =20 static int geni_i2c_init(struct geni_i2c_dev *gi2c) { - const struct geni_i2c_desc *desc =3D NULL; u32 proto, tx_depth; bool fifo_disable; int ret; @@ -1001,8 +1001,7 @@ static int geni_i2c_init(struct geni_i2c_dev *gi2c) goto err; } =20 - desc =3D device_get_match_data(gi2c->se.dev); - if (desc && desc->no_dma_support) + if (gi2c->dev_data->no_dma_support) fifo_disable =3D false; else fifo_disable =3D readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIF= O_IF_DISABLE; @@ -1020,8 +1019,8 @@ static int geni_i2c_init(struct geni_i2c_dev *gi2c) tx_depth =3D geni_se_get_tx_fifo_depth(&gi2c->se); =20 /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */ - if (!tx_depth && desc) - tx_depth =3D desc->tx_fifo_depth; + if (!tx_depth && gi2c->dev_data->has_core_clk) + tx_depth =3D gi2c->dev_data->tx_fifo_depth; =20 if (!tx_depth) { ret =3D dev_err_probe(gi2c->se.dev, -EINVAL, @@ -1064,7 +1063,6 @@ static int geni_i2c_probe(struct platform_device *pde= v) struct geni_i2c_dev *gi2c; int ret; struct device *dev =3D &pdev->dev; - const struct geni_i2c_desc *desc =3D NULL; =20 gi2c =3D devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL); 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Sun, 28 Dec 2025 20:56:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IH2Im2N5utl57u5unWBSgURqzOVdOWAS9FpqgH0c6WfdB4d8UmoshJqLGq4PSmYCtSzhPUoPg== X-Received: by 2002:a05:6a00:808c:b0:7e8:450c:61b5 with SMTP id d2e1a72fcca58-7ff6607b7e7mr25052010b3a.37.1766984182790; Sun, 28 Dec 2025 20:56:22 -0800 (PST) Received: from hu-ptalari-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7ff7dfac29bsm27902080b3a.39.2025.12.28.20.56.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Dec 2025 20:56:22 -0800 (PST) From: Praveen Talari To: Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mukesh Kumar Savaliya , Viken Dadhaniya , Bjorn Andersson , Konrad Dybcio , Praveen Talari , linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alexey.klimov@linaro.org, krzk@kernel.org, bryan.odonoghue@linaro.org, jorge.ramirez@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com Cc: psodagud@quicinc.com, djaggi@quicinc.com, quic_msavaliy@quicinc.com, quic_vtanuku@quicinc.com, quic_arandive@quicinc.com, quic_shazhuss@quicinc.com, quic_cchiluve@quicinc.com Subject: [PATCH v2 12/12] i2c: qcom-geni: Enable I2C on SA8255p Qualcomm platforms Date: Mon, 29 Dec 2025 10:24:46 +0530 Message-Id: <20251229045446.3227667-13-praveen.talari@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251229045446.3227667-1-praveen.talari@oss.qualcomm.com> References: <20251229045446.3227667-1-praveen.talari@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI5MDA0MiBTYWx0ZWRfX+8wp6YzaAvnT eyOZYwP5E0VavxM6EIYmQhVJUxFwamS2+BlutmCRY8ScRgV7l6tdnK9YJMzb46DZN/IEaHQmzLe /fXkfZ+BezYv3CS5YGRYFxkZiQjtr5dirZwEgRDtsEVYwwvAD37dkc24sd7bQ6ksXGc3ljkzY6d X2HjppouU+/xH1LeBHZgP3H+YNe8NK6JN6IeAGZ0BYujQg3/IYWiyfsx6+J1DJBEkmtcvSrspCK DvGFbojiavZaV4hdJdE+RJyFQAibQFhV4PTSUbOUu6Y0MZkno7PcWoLOmTWFFIrEbMcrVCyWJAf oUPKpZeB1ZjzoAd5mwbaKPJ4OFStQ8gDtiaHjCpC7SmXOwCurmojBf0OVkAtBfpb1fm37eXUbAO HaklDiwlfopkNlcnTdreIDNz8e/Q+W1aB4I6u3YhPTmAalA4UKm798PrDLiHTm6G7l4zcM17N4O K1zseSVsNehOsjifEPQ== X-Proofpoint-ORIG-GUID: nLv8dQkstSkTidT77kEvRXCq74Pgw1yz X-Proofpoint-GUID: nLv8dQkstSkTidT77kEvRXCq74Pgw1yz X-Authority-Analysis: v=2.4 cv=CK4nnBrD c=1 sm=1 tr=0 ts=695209f8 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=zgZzUwpPmSg69XYvEVoA:9 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-29_01,2025-12-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 adultscore=0 suspectscore=0 priorityscore=1501 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512290042 Content-Type: text/plain; charset="utf-8" The Qualcomm automotive SA8255p SoC relies on firmware to configure platform resources, including clocks, interconnects and TLMM. The driver requests resources operations over SCMI using power and performance protocols. The SCMI power protocol enables or disables resources like clocks, interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs, such as resume/suspend, to control power on/off. The SCMI performance protocol manages I2C frequency, with each frequency rate represented by a performance level. The driver uses geni_se_set_perf_opp() API to request the desired frequency rate.. As part of geni_se_set_perf_opp(), the OPP for the requested frequency is obtained using dev_pm_opp_find_freq_floor() and the performance level is set using dev_pm_opp_set_opp(). Signed-off-by: Praveen Talari --- V1->v2: From kernel test robot: - Initialized ret to "0" in resume/suspend callbacks. Bjorn: - Used seperate APIs for the resouces enable/disable. --- drivers/i2c/busses/i2c-qcom-geni.c | 53 ++++++++++++++++++++++-------- 1 file changed, 40 insertions(+), 13 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qc= om-geni.c index 1c9356e13b97..72457b98f155 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -82,6 +82,10 @@ struct geni_i2c_desc { char *icc_ddr; bool no_dma_support; unsigned int tx_fifo_depth; + int (*resources_init)(struct geni_se *se); + int (*set_rate)(struct geni_se *se, unsigned long freq); + int (*power_on)(struct geni_se *se); + int (*power_off)(struct geni_se *se); }; =20 #define QCOM_I2C_MIN_NUM_OF_MSGS_MULTI_DESC 2 @@ -203,8 +207,9 @@ static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi= 2c) return -EINVAL; } =20 -static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c) +static int qcom_geni_i2c_conf(struct geni_se *se, unsigned long freq) { + struct geni_i2c_dev *gi2c =3D dev_get_drvdata(se->dev); const struct geni_i2c_clk_fld *itr =3D gi2c->clk_fld; u32 val; =20 @@ -217,6 +222,7 @@ static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2= c) val |=3D itr->t_low_cnt << LOW_COUNTER_SHFT; val |=3D itr->t_cycle_cnt; writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS); + return 0; } =20 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c) @@ -908,7 +914,9 @@ static int geni_i2c_xfer(struct i2c_adapter *adap, return ret; } =20 - qcom_geni_i2c_conf(gi2c); + ret =3D gi2c->dev_data->set_rate(&gi2c->se, gi2c->clk_freq_out); + if (ret) + return ret; =20 if (gi2c->gpi_mode) ret =3D geni_i2c_gpi_xfer(gi2c, msgs, num); @@ -1041,8 +1049,9 @@ static int geni_i2c_init(struct geni_i2c_dev *gi2c) return ret; } =20 -static int geni_i2c_resources_init(struct geni_i2c_dev *gi2c) +static int geni_i2c_resources_init(struct geni_se *se) { + struct geni_i2c_dev *gi2c =3D dev_get_drvdata(se->dev); int ret; =20 ret =3D geni_se_resources_init(&gi2c->se); @@ -1095,7 +1104,7 @@ static int geni_i2c_probe(struct platform_device *pde= v) spin_lock_init(&gi2c->lock); platform_set_drvdata(pdev, gi2c); =20 - ret =3D geni_i2c_resources_init(gi2c); + ret =3D gi2c->dev_data->resources_init(&gi2c->se); if (ret) return ret; =20 @@ -1154,15 +1163,17 @@ static void geni_i2c_shutdown(struct platform_devic= e *pdev) =20 static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev) { - int ret; + int ret =3D 0; struct geni_i2c_dev *gi2c =3D dev_get_drvdata(dev); =20 disable_irq(gi2c->irq); =20 - ret =3D geni_se_resources_deactivate(&gi2c->se); - if (ret) { - enable_irq(gi2c->irq); - return ret; + if (gi2c->dev_data->power_off) { + ret =3D gi2c->dev_data->power_off(&gi2c->se); + if (ret) { + enable_irq(gi2c->irq); + return ret; + } } =20 gi2c->suspended =3D 1; @@ -1171,12 +1182,14 @@ static int __maybe_unused geni_i2c_runtime_suspend(= struct device *dev) =20 static int __maybe_unused geni_i2c_runtime_resume(struct device *dev) { - int ret; + int ret =3D 0; struct geni_i2c_dev *gi2c =3D dev_get_drvdata(dev); =20 - ret =3D geni_se_resources_activate(&gi2c->se); - if (ret) - return ret; + if (gi2c->dev_data->power_on) { + ret =3D gi2c->dev_data->power_on(&gi2c->se); + if (ret) + return ret; + } =20 enable_irq(gi2c->irq); gi2c->suspended =3D 0; @@ -1215,6 +1228,10 @@ static const struct dev_pm_ops geni_i2c_pm_ops =3D { =20 static const struct geni_i2c_desc geni_i2c =3D { .icc_ddr =3D "qup-memory", + .resources_init =3D geni_i2c_resources_init, + .set_rate =3D qcom_geni_i2c_conf, + .power_on =3D geni_se_resources_activate, + .power_off =3D geni_se_resources_deactivate, }; =20 static const struct geni_i2c_desc i2c_master_hub =3D { @@ -1222,11 +1239,21 @@ static const struct geni_i2c_desc i2c_master_hub = =3D { .icc_ddr =3D NULL, .no_dma_support =3D true, .tx_fifo_depth =3D 16, + .resources_init =3D geni_i2c_resources_init, + .set_rate =3D qcom_geni_i2c_conf, + .power_on =3D geni_se_resources_activate, + .power_off =3D geni_se_resources_deactivate, +}; + +static const struct geni_i2c_desc sa8255p_geni_i2c =3D { + .resources_init =3D geni_se_domain_attach, + .set_rate =3D geni_se_set_perf_opp, }; =20 static const struct of_device_id geni_i2c_dt_match[] =3D { { .compatible =3D "qcom,geni-i2c", .data =3D &geni_i2c }, { .compatible =3D "qcom,geni-i2c-master-hub", .data =3D &i2c_master_hub }, + { .compatible =3D "qcom,sa8255p-geni-i2c", .data =3D &sa8255p_geni_i2c }, {} }; MODULE_DEVICE_TABLE(of, geni_i2c_dt_match); --=20 2.34.1