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Mon, 29 Dec 2025 03:04:42 -0800 (PST) From: Guodong Xu Date: Mon, 29 Dec 2025 19:04:07 +0800 Subject: [PATCH 4/4] reset: spacemit: Add SpacemiT K3 reset driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251229-k3-reset-v1-4-eda0747bded3@riscstar.com> References: <20251229-k3-reset-v1-0-eda0747bded3@riscstar.com> In-Reply-To: <20251229-k3-reset-v1-0-eda0747bded3@riscstar.com> To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan Cc: Alex Elder , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Guodong Xu X-Mailer: b4 0.14.3 Add support for the SpacemiT K3 SoC reset controller. The K3 reset driver reuses the common reset controller code and provides K3-specific reset data for devices managed by the following units: - MPMU (Main Power Management Unit) - APBC (APB clock unit) - APMU (Application Subsystem Power Management Unit) - DCIU (DMA Control and Interface Unit) Signed-off-by: Guodong Xu --- drivers/reset/spacemit/Kconfig | 11 ++ drivers/reset/spacemit/Makefile | 1 + drivers/reset/spacemit/reset-spacemit-k3.c | 229 +++++++++++++++++++++++++= ++++ 3 files changed, 241 insertions(+) diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig index 56a4858b30e1..545d6b41c6ca 100644 --- a/drivers/reset/spacemit/Kconfig +++ b/drivers/reset/spacemit/Kconfig @@ -22,4 +22,15 @@ config RESET_SPACEMIT_K1 unit (CCU) driver to provide reset control functionality for various peripherals and subsystems in the SoC. =20 +config RESET_SPACEMIT_K3 + tristate "Support for SpacemiT K3 SoC" + depends on SPACEMIT_K3_CCU + select RESET_SPACEMIT_COMMON + default SPACEMIT_K3_CCU + help + Support for reset controller in SpacemiT K3 SoC. + This driver works with the SpacemiT K3 clock controller + unit (CCU) driver to provide reset control functionality + for various peripherals and subsystems in the SoC. + endmenu diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makef= ile index fecda9f211b2..be2daa183152 100644 --- a/drivers/reset/spacemit/Makefile +++ b/drivers/reset/spacemit/Makefile @@ -2,4 +2,5 @@ obj-$(CONFIG_RESET_SPACEMIT_COMMON) +=3D reset-spacemit-common.o =20 obj-$(CONFIG_RESET_SPACEMIT_K1) +=3D reset-spacemit-k1.o +obj-$(CONFIG_RESET_SPACEMIT_K3) +=3D reset-spacemit-k3.o =20 diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spa= cemit/reset-spacemit-k3.c new file mode 100644 index 000000000000..d143e1d66309 --- /dev/null +++ b/drivers/reset/spacemit/reset-spacemit-k3.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/* SpacemiT K3 reset controller driver */ + +#include + +#include +#include + +#include "reset-spacemit-common.h" + +static const struct ccu_reset_data k3_mpmu_resets[] =3D { + [RESET_MPMU_WDT] =3D RESET_DATA(MPMU_WDTPCR, BIT(2), 0), + [RESET_MPMU_RIPC] =3D RESET_DATA(MPMU_RIPCCR, BIT(2), 0), +}; + +static const struct ccu_reset_controller_data k3_mpmu_reset_data =3D { + .reset_data =3D k3_mpmu_resets, + .count =3D ARRAY_SIZE(k3_mpmu_resets), +}; + +static const struct ccu_reset_data k3_apbc_resets[] =3D { + [RESET_APBC_UART0] =3D RESET_DATA(APBC_UART0_CLK_RST, BIT(2), 0), + [RESET_APBC_UART2] =3D RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0), + [RESET_APBC_UART3] =3D RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0), + [RESET_APBC_UART4] =3D RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0), + [RESET_APBC_UART5] =3D RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0), + [RESET_APBC_UART6] =3D RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0), + [RESET_APBC_UART7] =3D RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0), + [RESET_APBC_UART8] =3D RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0), + [RESET_APBC_UART9] =3D RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0), + [RESET_APBC_UART10] =3D RESET_DATA(APBC_UART10_CLK_RST, BIT(2), 0), + [RESET_APBC_GPIO] =3D RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM0] =3D RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM1] =3D RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM2] =3D RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM3] =3D RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM4] =3D RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM5] =3D RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM6] =3D RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM7] =3D RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM8] =3D RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM9] =3D RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM10] =3D RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM11] =3D RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM12] =3D RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM13] =3D RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM14] =3D RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM15] =3D RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM16] =3D RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM17] =3D RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM18] =3D RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM19] =3D RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), 0), + [RESET_APBC_SPI0] =3D RESET_DATA(APBC_SSP0_CLK_RST, BIT(2), 0), + [RESET_APBC_SPI1] =3D RESET_DATA(APBC_SSP1_CLK_RST, BIT(2), 0), + [RESET_APBC_SPI3] =3D RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0), + [RESET_APBC_RTC] =3D RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0), + [RESET_APBC_TWSI0] =3D RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0), + [RESET_APBC_TWSI1] =3D RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0), + [RESET_APBC_TWSI2] =3D RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0), + [RESET_APBC_TWSI4] =3D RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0), + [RESET_APBC_TWSI5] =3D RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0), + [RESET_APBC_TWSI6] =3D RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0), + [RESET_APBC_TWSI8] =3D RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0), + [RESET_APBC_TIMERS0] =3D RESET_DATA(APBC_TIMERS0_CLK_RST, BIT(2), 0), + [RESET_APBC_TIMERS1] =3D RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0), + [RESET_APBC_TIMERS2] =3D RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0), + [RESET_APBC_TIMERS3] =3D RESET_DATA(APBC_TIMERS3_CLK_RST, BIT(2), 0), + [RESET_APBC_TIMERS4] =3D RESET_DATA(APBC_TIMERS4_CLK_RST, BIT(2), 0), + [RESET_APBC_TIMERS5] =3D RESET_DATA(APBC_TIMERS5_CLK_RST, BIT(2), 0), + [RESET_APBC_TIMERS6] =3D RESET_DATA(APBC_TIMERS6_CLK_RST, BIT(2), 0), + [RESET_APBC_TIMERS7] =3D RESET_DATA(APBC_TIMERS7_CLK_RST, BIT(2), 0), + [RESET_APBC_AIB] =3D RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0), + [RESET_APBC_ONEWIRE] =3D RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0), + [RESET_APBC_I2S0] =3D RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0), + [RESET_APBC_I2S1] =3D RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0), + [RESET_APBC_I2S2] =3D RESET_DATA(APBC_SSPA2_CLK_RST, BIT(2), 0), + [RESET_APBC_I2S3] =3D RESET_DATA(APBC_SSPA3_CLK_RST, BIT(2), 0), + [RESET_APBC_I2S4] =3D RESET_DATA(APBC_SSPA4_CLK_RST, BIT(2), 0), + [RESET_APBC_I2S5] =3D RESET_DATA(APBC_SSPA5_CLK_RST, BIT(2), 0), + [RESET_APBC_DRO] =3D RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0), + [RESET_APBC_IR0] =3D RESET_DATA(APBC_IR0_CLK_RST, BIT(2), 0), + [RESET_APBC_IR1] =3D RESET_DATA(APBC_IR1_CLK_RST, BIT(2), 0), + [RESET_APBC_TSEN] =3D RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0), + [RESET_IPC_AP2AUD] =3D RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0), + [RESET_APBC_CAN0] =3D RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0), + [RESET_APBC_CAN1] =3D RESET_DATA(APBC_CAN1_CLK_RST, BIT(2), 0), + [RESET_APBC_CAN2] =3D RESET_DATA(APBC_CAN2_CLK_RST, BIT(2), 0), + [RESET_APBC_CAN3] =3D RESET_DATA(APBC_CAN3_CLK_RST, BIT(2), 0), + [RESET_APBC_CAN4] =3D RESET_DATA(APBC_CAN4_CLK_RST, BIT(2), 0), +}; + +static const struct ccu_reset_controller_data k3_apbc_reset_data =3D { + .reset_data =3D k3_apbc_resets, + .count =3D ARRAY_SIZE(k3_apbc_resets), +}; + +static const struct ccu_reset_data k3_apmu_resets[] =3D { + [RESET_APMU_CSI] =3D RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_CCIC2PHY] =3D RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(= 2)), + [RESET_APMU_CCIC3PHY] =3D RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(= 29)), + [RESET_APMU_ISP_CIBUS] =3D RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)), + [RESET_APMU_DSI_ESC] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)), + [RESET_APMU_LCD] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)), + [RESET_APMU_V2D] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)), + [RESET_APMU_LCD_MCLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)), + [RESET_APMU_LCD_DSCCLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(15)= ), + [RESET_APMU_SC2_HCLK] =3D RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_CCIC_4X] =3D RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_CCIC1_PHY] =3D RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)), + [RESET_APMU_SDH_AXI] =3D RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_SDH0] =3D RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_SDH1] =3D RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_SDH2] =3D RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_USB2] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, + BIT(1)|BIT(2)|BIT(3)), + [RESET_APMU_USB3_PORTA] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, + BIT(5)|BIT(6)|BIT(7)), + [RESET_APMU_USB3_PORTB] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, + BIT(9)|BIT(10)|BIT(11)), + [RESET_APMU_USB3_PORTC] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, + BIT(13)|BIT(14)|BIT(15)), + [RESET_APMU_USB3_PORTD] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, + BIT(17)|BIT(18)|BIT(19)), + [RESET_APMU_QSPI] =3D RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_QSPI_BUS] =3D RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_DMA] =3D RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_AES_WTM] =3D RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)), + [RESET_APMU_MCB_DCLK] =3D RESET_DATA(APMU_MCB_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_MCB_ACLK] =3D RESET_DATA(APMU_MCB_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_VPU] =3D RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_DTC] =3D RESET_DATA(APMU_DTC_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_GPU] =3D RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_MC] =3D RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)), + [RESET_APMU_CPU0_POP] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(0), 0), + [RESET_APMU_CPU0_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(1), 0), + [RESET_APMU_CPU1_POP] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(3), 0), + [RESET_APMU_CPU1_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(4), 0), + [RESET_APMU_CPU2_POP] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(6), 0), + [RESET_APMU_CPU2_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(7), 0), + [RESET_APMU_CPU3_POP] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(9), 0), + [RESET_APMU_CPU3_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(10), 0), + [RESET_APMU_C0_MPSUB_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(12), 0), + [RESET_APMU_CPU4_POP] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(16), 0), + [RESET_APMU_CPU4_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(17), 0), + [RESET_APMU_CPU5_POP] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(19), 0), + [RESET_APMU_CPU5_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(20), 0), + [RESET_APMU_CPU6_POP] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(22), 0), + [RESET_APMU_CPU6_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(23), 0), + [RESET_APMU_CPU7_POP] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(25), 0), + [RESET_APMU_CPU7_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(26), 0), + [RESET_APMU_C1_MPSUB_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(28), 0), + [RESET_APMU_MPSUB_DBG] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(29), 0), + [RESET_APMU_UCIE] =3D RESET_DATA(APMU_UCIE_CTRL, + BIT(1) | BIT(2) | BIT(3), 0), + [RESET_APMU_RCPU] =3D RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, + BIT(3) | BIT(2) | BIT(0)), + [RESET_APMU_DSI4LN2_ESCCLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT= (3)), + [RESET_APMU_DSI4LN2_LCD_SW] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT= (4)), + [RESET_APMU_DSI4LN2_LCD_MCLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, B= IT(9)), + [RESET_APMU_DSI4LN2_LCD_DSCCLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0,= BIT(15)), + [RESET_APMU_DSI4LN2_DPU_ACLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL5, 0, B= IT(0)), + [RESET_APMU_DPU_ACLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL5, 0, BIT(15)), + [RESET_APMU_UFS_ACLK] =3D RESET_DATA(APMU_UFS_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_EDP0] =3D RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(0)), + [RESET_APMU_EDP1] =3D RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(16)), + [RESET_APMU_PCIE_PORTA] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, + BIT(5) | BIT(4) | BIT(3)), + [RESET_APMU_PCIE_PORTB] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, + BIT(5) | BIT(4) | BIT(3)), + [RESET_APMU_PCIE_PORTC] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, + BIT(5) | BIT(4) | BIT(3)), + [RESET_APMU_PCIE_PORTD] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, + BIT(5) | BIT(4) | BIT(3)), + [RESET_APMU_PCIE_PORTE] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, + BIT(5) | BIT(4) | BIT(3)), + [RESET_APMU_EMAC0] =3D RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_EMAC1] =3D RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_EMAC2] =3D RESET_DATA(APMU_EMAC2_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_ESPI_MCLK] =3D RESET_DATA(APMU_ESPI_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_ESPI_SCLK] =3D RESET_DATA(APMU_ESPI_CLK_RES_CTRL, 0, BIT(2)), +}; + +static const struct ccu_reset_controller_data k3_apmu_reset_data =3D { + .reset_data =3D k3_apmu_resets, + .count =3D ARRAY_SIZE(k3_apmu_resets), +}; + +static const struct ccu_reset_data k3_dciu_resets[] =3D { + [RESET_DCIU_HDMA] =3D RESET_DATA(DCIU_DMASYS_RSTN, 0, BIT(0)), + [RESET_DCIU_DMA350] =3D RESET_DATA(DCIU_DMASYS_SDMA_RSTN, 0, BIT(0)), + [RESET_DCIU_DMA350_0] =3D RESET_DATA(DCIU_DMASYS_S0_RSTN, 0, BIT(0)), + [RESET_DCIU_DMA350_1] =3D RESET_DATA(DCIU_DMASYS_S1_RSTN, 0, BIT(0)), + [RESET_DCIU_AXIDMA0] =3D RESET_DATA(DCIU_DMASYS_A0_RSTN, 0, BIT(0)), + [RESET_DCIU_AXIDMA1] =3D RESET_DATA(DCIU_DMASYS_A1_RSTN, 0, BIT(0)), + [RESET_DCIU_AXIDMA2] =3D RESET_DATA(DCIU_DMASYS_A2_RSTN, 0, BIT(0)), + [RESET_DCIU_AXIDMA3] =3D RESET_DATA(DCIU_DMASYS_A3_RSTN, 0, BIT(0)), + [RESET_DCIU_AXIDMA4] =3D RESET_DATA(DCIU_DMASYS_A4_RSTN, 0, BIT(0)), + [RESET_DCIU_AXIDMA5] =3D RESET_DATA(DCIU_DMASYS_A5_RSTN, 0, BIT(0)), + [RESET_DCIU_AXIDMA6] =3D RESET_DATA(DCIU_DMASYS_A6_RSTN, 0, BIT(0)), + [RESET_DCIU_AXIDMA7] =3D RESET_DATA(DCIU_DMASYS_A7_RSTN, 0, BIT(0)), +}; + +static const struct ccu_reset_controller_data k3_dciu_reset_data =3D { + .reset_data =3D k3_dciu_resets, + .count =3D ARRAY_SIZE(k3_dciu_resets), +}; + +#define K3_AUX_DEV_ID(_unit) SPACEMIT_AUX_DEV_ID(k3, _unit) + +static const struct auxiliary_device_id spacemit_k3_reset_ids[] =3D { + K3_AUX_DEV_ID(mpmu), + K3_AUX_DEV_ID(apbc), + K3_AUX_DEV_ID(apmu), + K3_AUX_DEV_ID(dciu), + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(auxiliary, spacemit_k3_reset_ids); + +static struct auxiliary_driver spacemit_k3_reset_driver =3D { + .probe =3D spacemit_reset_probe, + .id_table =3D spacemit_k3_reset_ids, +}; +module_auxiliary_driver(spacemit_k3_reset_driver); + +MODULE_IMPORT_NS("RESET_SPACEMIT"); +MODULE_AUTHOR("Guodong Xu "); +MODULE_DESCRIPTION("SpacemiT K3 reset controller driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0