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Mon, 29 Dec 2025 03:04:30 -0800 (PST) From: Guodong Xu Date: Mon, 29 Dec 2025 19:04:04 +0800 Subject: [PATCH 1/4] dt-bindings: reset: spacemit: Add K3 reset IDs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251229-k3-reset-v1-1-eda0747bded3@riscstar.com> References: <20251229-k3-reset-v1-0-eda0747bded3@riscstar.com> In-Reply-To: <20251229-k3-reset-v1-0-eda0747bded3@riscstar.com> To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan Cc: Alex Elder , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Guodong Xu X-Mailer: b4 0.14.3 Add reset IDs for SpacemiT K3 SoC. Signed-off-by: Guodong Xu --- include/dt-bindings/reset/spacemit,k3-resets.h | 171 +++++++++++++++++++++= ++++ 1 file changed, 171 insertions(+) diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bi= ndings/reset/spacemit,k3-resets.h new file mode 100644 index 000000000000..79ac1c22b7b5 --- /dev/null +++ b/include/dt-bindings/reset/spacemit,k3-resets.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 SpacemiT Technology Co. Ltd + */ + +#ifndef _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_ +#define _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_ + +/* MPMU resets */ +#define RESET_MPMU_WDT 0 +#define RESET_MPMU_RIPC 1 + +/* APBC resets */ +#define RESET_APBC_UART0 0 +#define RESET_APBC_UART2 1 +#define RESET_APBC_UART3 2 +#define RESET_APBC_UART4 3 +#define RESET_APBC_UART5 4 +#define RESET_APBC_UART6 5 +#define RESET_APBC_UART7 6 +#define RESET_APBC_UART8 7 +#define RESET_APBC_UART9 8 +#define RESET_APBC_UART10 9 +#define RESET_APBC_GPIO 10 +#define RESET_APBC_PWM0 11 +#define RESET_APBC_PWM1 12 +#define RESET_APBC_PWM2 13 +#define RESET_APBC_PWM3 14 +#define RESET_APBC_PWM4 15 +#define RESET_APBC_PWM5 16 +#define RESET_APBC_PWM6 17 +#define RESET_APBC_PWM7 18 +#define RESET_APBC_PWM8 19 +#define RESET_APBC_PWM9 20 +#define RESET_APBC_PWM10 21 +#define RESET_APBC_PWM11 22 +#define RESET_APBC_PWM12 23 +#define RESET_APBC_PWM13 24 +#define RESET_APBC_PWM14 25 +#define RESET_APBC_PWM15 26 +#define RESET_APBC_PWM16 27 +#define RESET_APBC_PWM17 28 +#define RESET_APBC_PWM18 29 +#define RESET_APBC_PWM19 30 +#define RESET_APBC_SPI0 31 +#define RESET_APBC_SPI1 32 +#define RESET_APBC_SPI3 33 +#define RESET_APBC_RTC 34 +#define RESET_APBC_TWSI0 35 +#define RESET_APBC_TWSI1 36 +#define RESET_APBC_TWSI2 37 +#define RESET_APBC_TWSI4 38 +#define RESET_APBC_TWSI5 39 +#define RESET_APBC_TWSI6 40 +#define RESET_APBC_TWSI8 41 +#define RESET_APBC_TIMERS0 42 +#define RESET_APBC_TIMERS1 43 +#define RESET_APBC_TIMERS2 44 +#define RESET_APBC_TIMERS3 45 +#define RESET_APBC_TIMERS4 46 +#define RESET_APBC_TIMERS5 47 +#define RESET_APBC_TIMERS6 48 +#define RESET_APBC_TIMERS7 49 +#define RESET_APBC_AIB 50 +#define RESET_APBC_ONEWIRE 51 +#define RESET_APBC_I2S0 52 +#define RESET_APBC_I2S1 53 +#define RESET_APBC_I2S2 54 +#define RESET_APBC_I2S3 55 +#define RESET_APBC_I2S4 56 +#define RESET_APBC_I2S5 57 +#define RESET_APBC_DRO 58 +#define RESET_APBC_IR0 59 +#define RESET_APBC_IR1 60 +#define RESET_APBC_TSEN 61 +#define RESET_IPC_AP2AUD 62 +#define RESET_APBC_CAN0 63 +#define RESET_APBC_CAN1 64 +#define RESET_APBC_CAN2 65 +#define RESET_APBC_CAN3 66 +#define RESET_APBC_CAN4 67 + +/* APMU resets */ +#define RESET_APMU_CSI 0 +#define RESET_APMU_CCIC2PHY 1 +#define RESET_APMU_CCIC3PHY 2 +#define RESET_APMU_ISP_CIBUS 3 +#define RESET_APMU_DSI_ESC 4 +#define RESET_APMU_LCD 5 +#define RESET_APMU_V2D 6 +#define RESET_APMU_LCD_MCLK 7 +#define RESET_APMU_LCD_DSCCLK 8 +#define RESET_APMU_SC2_HCLK 9 +#define RESET_APMU_CCIC_4X 10 +#define RESET_APMU_CCIC1_PHY 11 +#define RESET_APMU_SDH_AXI 12 +#define RESET_APMU_SDH0 13 +#define RESET_APMU_SDH1 14 +#define RESET_APMU_SDH2 15 +#define RESET_APMU_USB2 16 +#define RESET_APMU_USB3_PORTA 17 +#define RESET_APMU_USB3_PORTB 18 +#define RESET_APMU_USB3_PORTC 19 +#define RESET_APMU_USB3_PORTD 20 +#define RESET_APMU_QSPI 21 +#define RESET_APMU_QSPI_BUS 22 +#define RESET_APMU_DMA 23 +#define RESET_APMU_AES_WTM 24 +#define RESET_APMU_MCB_DCLK 25 +#define RESET_APMU_MCB_ACLK 26 +#define RESET_APMU_VPU 27 +#define RESET_APMU_DTC 28 +#define RESET_APMU_GPU 29 +#define RESET_APMU_ALZO 30 +#define RESET_APMU_MC 31 +#define RESET_APMU_CPU0_POP 32 +#define RESET_APMU_CPU0_SW 33 +#define RESET_APMU_CPU1_POP 34 +#define RESET_APMU_CPU1_SW 35 +#define RESET_APMU_CPU2_POP 36 +#define RESET_APMU_CPU2_SW 37 +#define RESET_APMU_CPU3_POP 38 +#define RESET_APMU_CPU3_SW 39 +#define RESET_APMU_C0_MPSUB_SW 40 +#define RESET_APMU_CPU4_POP 41 +#define RESET_APMU_CPU4_SW 42 +#define RESET_APMU_CPU5_POP 43 +#define RESET_APMU_CPU5_SW 44 +#define RESET_APMU_CPU6_POP 45 +#define RESET_APMU_CPU6_SW 46 +#define RESET_APMU_CPU7_POP 47 +#define RESET_APMU_CPU7_SW 48 +#define RESET_APMU_C1_MPSUB_SW 49 +#define RESET_APMU_MPSUB_DBG 50 +#define RESET_APMU_UCIE 51 +#define RESET_APMU_RCPU 52 +#define RESET_APMU_DSI4LN2_ESCCLK 53 +#define RESET_APMU_DSI4LN2_LCD_SW 54 +#define RESET_APMU_DSI4LN2_LCD_MCLK 55 +#define RESET_APMU_DSI4LN2_LCD_DSCCLK 56 +#define RESET_APMU_DSI4LN2_DPU_ACLK 57 +#define RESET_APMU_DPU_ACLK 58 +#define RESET_APMU_UFS_ACLK 59 +#define RESET_APMU_EDP0 60 +#define RESET_APMU_EDP1 61 +#define RESET_APMU_PCIE_PORTA 62 +#define RESET_APMU_PCIE_PORTB 63 +#define RESET_APMU_PCIE_PORTC 64 +#define RESET_APMU_PCIE_PORTD 65 +#define RESET_APMU_PCIE_PORTE 66 +#define RESET_APMU_EMAC0 67 +#define RESET_APMU_EMAC1 68 +#define RESET_APMU_EMAC2 69 +#define RESET_APMU_ESPI_MCLK 70 +#define RESET_APMU_ESPI_SCLK 71 + +/* DCIU resets*/ +#define RESET_DCIU_HDMA 0 +#define RESET_DCIU_DMA350 1 +#define RESET_DCIU_DMA350_0 2 +#define RESET_DCIU_DMA350_1 3 +#define RESET_DCIU_AXIDMA0 4 +#define RESET_DCIU_AXIDMA1 5 +#define RESET_DCIU_AXIDMA2 6 +#define RESET_DCIU_AXIDMA3 7 +#define RESET_DCIU_AXIDMA4 8 +#define RESET_DCIU_AXIDMA5 9 +#define RESET_DCIU_AXIDMA6 10 +#define RESET_DCIU_AXIDMA7 11 + +#endif /* _DT_BINDINGS_RESET_SPACEMIT_K3_H_ */ --=20 2.43.0 From nobody Sun Feb 8 05:23:43 2026 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com 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List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251229-k3-reset-v1-2-eda0747bded3@riscstar.com> References: <20251229-k3-reset-v1-0-eda0747bded3@riscstar.com> In-Reply-To: <20251229-k3-reset-v1-0-eda0747bded3@riscstar.com> To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan Cc: Alex Elder , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Guodong Xu X-Mailer: b4 0.14.3 Create a dedicated subdirectory for SpacemiT reset drivers to allow for better organization as support for more SoCs is added. Move the existing K1 reset driver into this new directory and rename it to reset-spacemit-k1.c. Rename the Kconfig symbol to RESET_SPACEMIT_K1 and update its default from ARCH_SPACEMIT to SPACEMIT_K1_CCU. The reset driver depends on the clock driver to register reset devices as an auxiliary device, so the default should reflect this dependency. Also sort the drivers/reset/Kconfig entries alphabetically. Signed-off-by: Guodong Xu --- drivers/reset/Kconfig | 12 ++--------= -- drivers/reset/Makefile | 2 +- drivers/reset/spacemit/Kconfig | 14 ++++++++++= ++++ drivers/reset/spacemit/Makefile | 3 +++ .../{reset-spacemit.c =3D> spacemit/reset-spacemit-k1.c} | 0 5 files changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 6e5d6deffa7d..b110f0fa7bb1 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -299,15 +299,6 @@ config RESET_SOCFPGA This enables the reset driver for the SoCFPGA ARMv7 platforms. This driver gets initialized early during platform init calls. =20 -config RESET_SPACEMIT - tristate "SpacemiT reset driver" - depends on ARCH_SPACEMIT || COMPILE_TEST - select AUXILIARY_BUS - default ARCH_SPACEMIT - help - This enables the reset controller driver for SpacemiT SoCs, - including the K1. - config RESET_SUNPLUS bool "Sunplus SoCs Reset Driver" if COMPILE_TEST default ARCH_SUNPLUS @@ -406,9 +397,10 @@ config RESET_ZYNQMP This enables the reset controller driver for Xilinx ZynqMP SoCs. =20 source "drivers/reset/amlogic/Kconfig" +source "drivers/reset/hisilicon/Kconfig" +source "drivers/reset/spacemit/Kconfig" source "drivers/reset/starfive/Kconfig" source "drivers/reset/sti/Kconfig" -source "drivers/reset/hisilicon/Kconfig" source "drivers/reset/tegra/Kconfig" =20 endif diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 9c3e484dfd81..fc0cc99f8514 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -2,6 +2,7 @@ obj-y +=3D core.o obj-y +=3D amlogic/ obj-y +=3D hisilicon/ +obj-y +=3D spacemit/ obj-y +=3D starfive/ obj-y +=3D sti/ obj-y +=3D tegra/ @@ -38,7 +39,6 @@ obj-$(CONFIG_RESET_RZV2H_USB2PHY) +=3D reset-rzv2h-usb2ph= y.o obj-$(CONFIG_RESET_SCMI) +=3D reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) +=3D reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) +=3D reset-socfpga.o -obj-$(CONFIG_RESET_SPACEMIT) +=3D reset-spacemit.o obj-$(CONFIG_RESET_SUNPLUS) +=3D reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) +=3D reset-sunxi.o obj-$(CONFIG_RESET_TH1520) +=3D reset-th1520.o diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig new file mode 100644 index 000000000000..552884e8b72a --- /dev/null +++ b/drivers/reset/spacemit/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config RESET_SPACEMIT_K1 + tristate "SpacemiT K1 reset driver" + depends on ARCH_SPACEMIT || COMPILE_TEST + depends on SPACEMIT_K1_CCU + select AUXILIARY_BUS + default SPACEMIT_K1_CCU + help + Support for reset controller in SpacemiT K1 SoC. + This driver works with the SpacemiT K1 clock controller + unit (CCU) driver to provide reset control functionality + for various peripherals and subsystems in the SoC. + diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makef= ile new file mode 100644 index 000000000000..de7e358c74fd --- /dev/null +++ b/drivers/reset/spacemit/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_RESET_SPACEMIT_K1) +=3D reset-spacemit-k1.o + diff --git a/drivers/reset/reset-spacemit.c b/drivers/reset/spacemit/reset-= spacemit-k1.c similarity index 100% rename from drivers/reset/reset-spacemit.c rename to drivers/reset/spacemit/reset-spacemit-k1.c --=20 2.43.0 From nobody Sun Feb 8 05:23:43 2026 Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E6D8299923 for ; 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Mon, 29 Dec 2025 03:04:38 -0800 (PST) Received: from [127.0.1.1] ([2a12:a305:4::40d7]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7ff7aa32916sm29338817b3a.8.2025.12.29.03.04.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Dec 2025 03:04:38 -0800 (PST) From: Guodong Xu Date: Mon, 29 Dec 2025 19:04:06 +0800 Subject: [PATCH 3/4] reset: spacemit: Extract common K1 reset code Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251229-k3-reset-v1-3-eda0747bded3@riscstar.com> References: <20251229-k3-reset-v1-0-eda0747bded3@riscstar.com> In-Reply-To: <20251229-k3-reset-v1-0-eda0747bded3@riscstar.com> To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan Cc: Alex Elder , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Guodong Xu X-Mailer: b4 0.14.3 Extract the common reset controller code from the K1 driver into separate reset-spacemit-common.{c,h} files. This prepares for additional SpacemiT SoCs that share the same reset controller architecture. The common code now includes handlers for reset assert deassert operations and probing for auxiliary bus devices. Signed-off-by: Guodong Xu --- drivers/reset/spacemit/Kconfig | 17 +++- drivers/reset/spacemit/Makefile | 2 + drivers/reset/spacemit/reset-spacemit-common.c | 79 +++++++++++++++++ drivers/reset/spacemit/reset-spacemit-common.h | 53 ++++++++++++ drivers/reset/spacemit/reset-spacemit-k1.c | 113 +++------------------= ---- 5 files changed, 158 insertions(+), 106 deletions(-) diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig index 552884e8b72a..56a4858b30e1 100644 --- a/drivers/reset/spacemit/Kconfig +++ b/drivers/reset/spacemit/Kconfig @@ -1,10 +1,20 @@ # SPDX-License-Identifier: GPL-2.0-only =20 -config RESET_SPACEMIT_K1 - tristate "SpacemiT K1 reset driver" +menu "Reset support for SpacemiT platforms" depends on ARCH_SPACEMIT || COMPILE_TEST - depends on SPACEMIT_K1_CCU + +config RESET_SPACEMIT_COMMON + tristate select AUXILIARY_BUS + help + Common reset controller infrastructure for SpacemiT SoCs. + This provides shared code and helper functions used by + reset drivers for various SpacemiT SoC families. + +config RESET_SPACEMIT_K1 + tristate "Support for SpacemiT K1 SoC" + depends on SPACEMIT_K1_CCU + select RESET_SPACEMIT_COMMON default SPACEMIT_K1_CCU help Support for reset controller in SpacemiT K1 SoC. @@ -12,3 +22,4 @@ config RESET_SPACEMIT_K1 unit (CCU) driver to provide reset control functionality for various peripherals and subsystems in the SoC. =20 +endmenu diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makef= ile index de7e358c74fd..fecda9f211b2 100644 --- a/drivers/reset/spacemit/Makefile +++ b/drivers/reset/spacemit/Makefile @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_RESET_SPACEMIT_COMMON) +=3D reset-spacemit-common.o + obj-$(CONFIG_RESET_SPACEMIT_K1) +=3D reset-spacemit-k1.o =20 diff --git a/drivers/reset/spacemit/reset-spacemit-common.c b/drivers/reset= /spacemit/reset-spacemit-common.c new file mode 100644 index 000000000000..e4b3f0e2c59d --- /dev/null +++ b/drivers/reset/spacemit/reset-spacemit-common.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/* SpacemiT reset controller driver - common implementation */ + +#include +#include +#include + +#include + +#include "reset-spacemit-common.h" + +static int spacemit_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct ccu_reset_controller *controller; + const struct ccu_reset_data *data; + u32 mask; + u32 val; + + controller =3D container_of(rcdev, struct ccu_reset_controller, rcdev); + data =3D &controller->data->reset_data[id]; + mask =3D data->assert_mask | data->deassert_mask; + val =3D assert ? data->assert_mask : data->deassert_mask; + + return regmap_update_bits(controller->regmap, data->offset, mask, val); +} + +static int spacemit_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return spacemit_reset_update(rcdev, id, true); +} + +static int spacemit_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return spacemit_reset_update(rcdev, id, false); +} + +const struct reset_control_ops spacemit_reset_control_ops =3D { + .assert =3D spacemit_reset_assert, + .deassert =3D spacemit_reset_deassert, +}; +EXPORT_SYMBOL_GPL(spacemit_reset_control_ops); + +static int spacemit_reset_controller_register(struct device *dev, + struct ccu_reset_controller *controller) +{ + struct reset_controller_dev *rcdev =3D &controller->rcdev; + + rcdev->ops =3D &spacemit_reset_control_ops; + rcdev->owner =3D THIS_MODULE; + rcdev->of_node =3D dev->of_node; + rcdev->nr_resets =3D controller->data->count; + + return devm_reset_controller_register(dev, &controller->rcdev); +} + +int spacemit_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct spacemit_ccu_adev *rdev =3D to_spacemit_ccu_adev(adev); + struct ccu_reset_controller *controller; + struct device *dev =3D &adev->dev; + + controller =3D devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); + if (!controller) + return -ENOMEM; + controller->data =3D (const struct ccu_reset_controller_data *)id->driver= _data; + controller->regmap =3D rdev->regmap; + + return spacemit_reset_controller_register(dev, controller); +} +EXPORT_SYMBOL_NS_GPL(spacemit_reset_probe, "RESET_SPACEMIT"); + +MODULE_DESCRIPTION("SpacemiT reset controller driver - common code"); +MODULE_LICENSE("GPL"); + diff --git a/drivers/reset/spacemit/reset-spacemit-common.h b/drivers/reset= /spacemit/reset-spacemit-common.h new file mode 100644 index 000000000000..9900a92f2c88 --- /dev/null +++ b/drivers/reset/spacemit/reset-spacemit-common.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * SpacemiT reset controller driver - common definitions + */ + +#ifndef _RESET_SPACEMIT_COMMON_H_ +#define _RESET_SPACEMIT_COMMON_H_ + +#include +#include +#include +#include + +struct ccu_reset_data { + u32 offset; + u32 assert_mask; + u32 deassert_mask; +}; + +struct ccu_reset_controller_data { + const struct ccu_reset_data *reset_data; /* array */ + size_t count; +}; + +struct ccu_reset_controller { + struct reset_controller_dev rcdev; + const struct ccu_reset_controller_data *data; + struct regmap *regmap; +}; + +#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ + { \ + .offset =3D (_offset), \ + .assert_mask =3D (_assert_mask), \ + .deassert_mask =3D (_deassert_mask), \ + } + +/* Common reset operations */ +extern const struct reset_control_ops spacemit_reset_control_ops; + +/* Common probe function */ +int spacemit_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id); + +/* Common auxiliary device ID macro */ +#define SPACEMIT_AUX_DEV_ID(_prefix, _unit) \ + { \ + .name =3D "spacemit_ccu." _K_RST(_unit), \ + .driver_data =3D (kernel_ulong_t)&_prefix ## _ ## _unit ## _reset_data, \ + } + +#endif /* _RESET_SPACEMIT_COMMON_H_ */ + diff --git a/drivers/reset/spacemit/reset-spacemit-k1.c b/drivers/reset/spa= cemit/reset-spacemit-k1.c index 8922e14fa836..111acbdb5040 100644 --- a/drivers/reset/spacemit/reset-spacemit-k1.c +++ b/drivers/reset/spacemit/reset-spacemit-k1.c @@ -1,41 +1,13 @@ // SPDX-License-Identifier: GPL-2.0-only =20 -/* SpacemiT reset controller driver */ +/* SpacemiT K1 reset controller driver */ =20 -#include -#include -#include #include -#include -#include -#include =20 -#include #include +#include =20 -struct ccu_reset_data { - u32 offset; - u32 assert_mask; - u32 deassert_mask; -}; - -struct ccu_reset_controller_data { - const struct ccu_reset_data *reset_data; /* array */ - size_t count; -}; - -struct ccu_reset_controller { - struct reset_controller_dev rcdev; - const struct ccu_reset_controller_data *data; - struct regmap *regmap; -}; - -#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ - { \ - .offset =3D (_offset), \ - .assert_mask =3D (_assert_mask), \ - .deassert_mask =3D (_deassert_mask), \ - } +#include "reset-spacemit-common.h" =20 static const struct ccu_reset_data k1_mpmu_resets[] =3D { [RESET_WDT] =3D RESET_DATA(MPMU_WDTPCR, BIT(2), 0), @@ -214,91 +186,26 @@ static const struct ccu_reset_controller_data k1_apbc= 2_reset_data =3D { .count =3D ARRAY_SIZE(k1_apbc2_resets), }; =20 -static int spacemit_reset_update(struct reset_controller_dev *rcdev, - unsigned long id, bool assert) -{ - struct ccu_reset_controller *controller; - const struct ccu_reset_data *data; - u32 mask; - u32 val; - - controller =3D container_of(rcdev, struct ccu_reset_controller, rcdev); - data =3D &controller->data->reset_data[id]; - mask =3D data->assert_mask | data->deassert_mask; - val =3D assert ? data->assert_mask : data->deassert_mask; - - return regmap_update_bits(controller->regmap, data->offset, mask, val); -} - -static int spacemit_reset_assert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - return spacemit_reset_update(rcdev, id, true); -} - -static int spacemit_reset_deassert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - return spacemit_reset_update(rcdev, id, false); -} - -static const struct reset_control_ops spacemit_reset_control_ops =3D { - .assert =3D spacemit_reset_assert, - .deassert =3D spacemit_reset_deassert, -}; - -static int spacemit_reset_controller_register(struct device *dev, - struct ccu_reset_controller *controller) -{ - struct reset_controller_dev *rcdev =3D &controller->rcdev; - - rcdev->ops =3D &spacemit_reset_control_ops; - rcdev->owner =3D THIS_MODULE; - rcdev->of_node =3D dev->of_node; - rcdev->nr_resets =3D controller->data->count; - - return devm_reset_controller_register(dev, &controller->rcdev); -} - -static int spacemit_reset_probe(struct auxiliary_device *adev, - const struct auxiliary_device_id *id) -{ - struct spacemit_ccu_adev *rdev =3D to_spacemit_ccu_adev(adev); - struct ccu_reset_controller *controller; - struct device *dev =3D &adev->dev; - - controller =3D devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); - if (!controller) - return -ENOMEM; - controller->data =3D (const struct ccu_reset_controller_data *)id->driver= _data; - controller->regmap =3D rdev->regmap; - - return spacemit_reset_controller_register(dev, controller); -} - -#define K1_AUX_DEV_ID(_unit) \ - { \ - .name =3D "spacemit_ccu." _K_RST(_unit), \ - .driver_data =3D (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \ - } +#define K1_AUX_DEV_ID(_unit) SPACEMIT_AUX_DEV_ID(k1, _unit) =20 -static const struct auxiliary_device_id spacemit_reset_ids[] =3D { +static const struct auxiliary_device_id spacemit_k1_reset_ids[] =3D { K1_AUX_DEV_ID(mpmu), K1_AUX_DEV_ID(apbc), K1_AUX_DEV_ID(apmu), K1_AUX_DEV_ID(rcpu), K1_AUX_DEV_ID(rcpu2), K1_AUX_DEV_ID(apbc2), - { }, + { /* sentinel */ } }; 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Mon, 29 Dec 2025 03:04:43 -0800 (PST) Received: from [127.0.1.1] ([2a12:a305:4::40d7]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7ff7aa32916sm29338817b3a.8.2025.12.29.03.04.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Dec 2025 03:04:42 -0800 (PST) From: Guodong Xu Date: Mon, 29 Dec 2025 19:04:07 +0800 Subject: [PATCH 4/4] reset: spacemit: Add SpacemiT K3 reset driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251229-k3-reset-v1-4-eda0747bded3@riscstar.com> References: <20251229-k3-reset-v1-0-eda0747bded3@riscstar.com> In-Reply-To: <20251229-k3-reset-v1-0-eda0747bded3@riscstar.com> To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan Cc: Alex Elder , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Guodong Xu X-Mailer: b4 0.14.3 Add support for the SpacemiT K3 SoC reset controller. The K3 reset driver reuses the common reset controller code and provides K3-specific reset data for devices managed by the following units: - MPMU (Main Power Management Unit) - APBC (APB clock unit) - APMU (Application Subsystem Power Management Unit) - DCIU (DMA Control and Interface Unit) Signed-off-by: Guodong Xu --- drivers/reset/spacemit/Kconfig | 11 ++ drivers/reset/spacemit/Makefile | 1 + drivers/reset/spacemit/reset-spacemit-k3.c | 229 +++++++++++++++++++++++++= ++++ 3 files changed, 241 insertions(+) diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig index 56a4858b30e1..545d6b41c6ca 100644 --- a/drivers/reset/spacemit/Kconfig +++ b/drivers/reset/spacemit/Kconfig @@ -22,4 +22,15 @@ config RESET_SPACEMIT_K1 unit (CCU) driver to provide reset control functionality for various peripherals and subsystems in the SoC. =20 +config RESET_SPACEMIT_K3 + tristate "Support for SpacemiT K3 SoC" + depends on SPACEMIT_K3_CCU + select RESET_SPACEMIT_COMMON + default SPACEMIT_K3_CCU + help + Support for reset controller in SpacemiT K3 SoC. + This driver works with the SpacemiT K3 clock controller + unit (CCU) driver to provide reset control functionality + for various peripherals and subsystems in the SoC. + endmenu diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makef= ile index fecda9f211b2..be2daa183152 100644 --- a/drivers/reset/spacemit/Makefile +++ b/drivers/reset/spacemit/Makefile @@ -2,4 +2,5 @@ obj-$(CONFIG_RESET_SPACEMIT_COMMON) +=3D reset-spacemit-common.o =20 obj-$(CONFIG_RESET_SPACEMIT_K1) +=3D reset-spacemit-k1.o +obj-$(CONFIG_RESET_SPACEMIT_K3) +=3D reset-spacemit-k3.o =20 diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spa= cemit/reset-spacemit-k3.c new file mode 100644 index 000000000000..d143e1d66309 --- /dev/null +++ b/drivers/reset/spacemit/reset-spacemit-k3.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/* SpacemiT K3 reset controller driver */ + +#include + +#include +#include + +#include "reset-spacemit-common.h" + +static const struct ccu_reset_data k3_mpmu_resets[] =3D { + [RESET_MPMU_WDT] =3D RESET_DATA(MPMU_WDTPCR, BIT(2), 0), + [RESET_MPMU_RIPC] =3D RESET_DATA(MPMU_RIPCCR, BIT(2), 0), +}; + +static const struct ccu_reset_controller_data k3_mpmu_reset_data =3D { + .reset_data =3D k3_mpmu_resets, + .count =3D ARRAY_SIZE(k3_mpmu_resets), +}; + +static const struct ccu_reset_data k3_apbc_resets[] =3D { + [RESET_APBC_UART0] =3D RESET_DATA(APBC_UART0_CLK_RST, BIT(2), 0), + [RESET_APBC_UART2] =3D RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0), + [RESET_APBC_UART3] =3D RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0), + [RESET_APBC_UART4] =3D RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0), + [RESET_APBC_UART5] =3D RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0), + [RESET_APBC_UART6] =3D RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0), + [RESET_APBC_UART7] =3D RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0), + [RESET_APBC_UART8] =3D RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0), + [RESET_APBC_UART9] =3D RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0), + [RESET_APBC_UART10] =3D RESET_DATA(APBC_UART10_CLK_RST, BIT(2), 0), + [RESET_APBC_GPIO] =3D RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM0] =3D RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM1] =3D RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM2] =3D RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM3] =3D RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM4] =3D RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM5] =3D RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM6] =3D RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM7] =3D RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM8] =3D RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM9] =3D RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM10] =3D RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM11] =3D RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM12] =3D RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM13] =3D RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM14] =3D RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM15] =3D RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM16] =3D RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM17] =3D RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM18] =3D RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), 0), + [RESET_APBC_PWM19] =3D RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), 0), + [RESET_APBC_SPI0] =3D RESET_DATA(APBC_SSP0_CLK_RST, BIT(2), 0), + [RESET_APBC_SPI1] =3D RESET_DATA(APBC_SSP1_CLK_RST, BIT(2), 0), + [RESET_APBC_SPI3] =3D RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0), + [RESET_APBC_RTC] =3D RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0), + [RESET_APBC_TWSI0] =3D RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0), + [RESET_APBC_TWSI1] =3D RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0), + [RESET_APBC_TWSI2] =3D RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0), + [RESET_APBC_TWSI4] =3D RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0), + [RESET_APBC_TWSI5] =3D RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0), + [RESET_APBC_TWSI6] =3D RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0), + [RESET_APBC_TWSI8] =3D RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0), + [RESET_APBC_TIMERS0] =3D RESET_DATA(APBC_TIMERS0_CLK_RST, BIT(2), 0), + [RESET_APBC_TIMERS1] =3D RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0), + [RESET_APBC_TIMERS2] =3D RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0), + [RESET_APBC_TIMERS3] =3D RESET_DATA(APBC_TIMERS3_CLK_RST, BIT(2), 0), + [RESET_APBC_TIMERS4] =3D RESET_DATA(APBC_TIMERS4_CLK_RST, BIT(2), 0), + [RESET_APBC_TIMERS5] =3D RESET_DATA(APBC_TIMERS5_CLK_RST, BIT(2), 0), + [RESET_APBC_TIMERS6] =3D RESET_DATA(APBC_TIMERS6_CLK_RST, BIT(2), 0), + [RESET_APBC_TIMERS7] =3D RESET_DATA(APBC_TIMERS7_CLK_RST, BIT(2), 0), + [RESET_APBC_AIB] =3D RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0), + [RESET_APBC_ONEWIRE] =3D RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0), + [RESET_APBC_I2S0] =3D RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0), + [RESET_APBC_I2S1] =3D RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0), + [RESET_APBC_I2S2] =3D RESET_DATA(APBC_SSPA2_CLK_RST, BIT(2), 0), + [RESET_APBC_I2S3] =3D RESET_DATA(APBC_SSPA3_CLK_RST, BIT(2), 0), + [RESET_APBC_I2S4] =3D RESET_DATA(APBC_SSPA4_CLK_RST, BIT(2), 0), + [RESET_APBC_I2S5] =3D RESET_DATA(APBC_SSPA5_CLK_RST, BIT(2), 0), + [RESET_APBC_DRO] =3D RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0), + [RESET_APBC_IR0] =3D RESET_DATA(APBC_IR0_CLK_RST, BIT(2), 0), + [RESET_APBC_IR1] =3D RESET_DATA(APBC_IR1_CLK_RST, BIT(2), 0), + [RESET_APBC_TSEN] =3D RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0), + [RESET_IPC_AP2AUD] =3D RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0), + [RESET_APBC_CAN0] =3D RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0), + [RESET_APBC_CAN1] =3D RESET_DATA(APBC_CAN1_CLK_RST, BIT(2), 0), + [RESET_APBC_CAN2] =3D RESET_DATA(APBC_CAN2_CLK_RST, BIT(2), 0), + [RESET_APBC_CAN3] =3D RESET_DATA(APBC_CAN3_CLK_RST, BIT(2), 0), + [RESET_APBC_CAN4] =3D RESET_DATA(APBC_CAN4_CLK_RST, BIT(2), 0), +}; + +static const struct ccu_reset_controller_data k3_apbc_reset_data =3D { + .reset_data =3D k3_apbc_resets, + .count =3D ARRAY_SIZE(k3_apbc_resets), +}; + +static const struct ccu_reset_data k3_apmu_resets[] =3D { + [RESET_APMU_CSI] =3D RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_CCIC2PHY] =3D RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(= 2)), + [RESET_APMU_CCIC3PHY] =3D RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(= 29)), + [RESET_APMU_ISP_CIBUS] =3D RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)), + [RESET_APMU_DSI_ESC] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)), + [RESET_APMU_LCD] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)), + [RESET_APMU_V2D] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)), + [RESET_APMU_LCD_MCLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)), + [RESET_APMU_LCD_DSCCLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(15)= ), + [RESET_APMU_SC2_HCLK] =3D RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_CCIC_4X] =3D RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_CCIC1_PHY] =3D RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)), + [RESET_APMU_SDH_AXI] =3D RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_SDH0] =3D RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_SDH1] =3D RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_SDH2] =3D RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_USB2] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, + BIT(1)|BIT(2)|BIT(3)), + [RESET_APMU_USB3_PORTA] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, + BIT(5)|BIT(6)|BIT(7)), + [RESET_APMU_USB3_PORTB] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, + BIT(9)|BIT(10)|BIT(11)), + [RESET_APMU_USB3_PORTC] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, + BIT(13)|BIT(14)|BIT(15)), + [RESET_APMU_USB3_PORTD] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, + BIT(17)|BIT(18)|BIT(19)), + [RESET_APMU_QSPI] =3D RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_QSPI_BUS] =3D RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_DMA] =3D RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_AES_WTM] =3D RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)), + [RESET_APMU_MCB_DCLK] =3D RESET_DATA(APMU_MCB_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_MCB_ACLK] =3D RESET_DATA(APMU_MCB_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_VPU] =3D RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_DTC] =3D RESET_DATA(APMU_DTC_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_GPU] =3D RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_MC] =3D RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)), + [RESET_APMU_CPU0_POP] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(0), 0), + [RESET_APMU_CPU0_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(1), 0), + [RESET_APMU_CPU1_POP] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(3), 0), + [RESET_APMU_CPU1_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(4), 0), + [RESET_APMU_CPU2_POP] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(6), 0), + [RESET_APMU_CPU2_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(7), 0), + [RESET_APMU_CPU3_POP] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(9), 0), + [RESET_APMU_CPU3_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(10), 0), + [RESET_APMU_C0_MPSUB_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(12), 0), + [RESET_APMU_CPU4_POP] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(16), 0), + [RESET_APMU_CPU4_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(17), 0), + [RESET_APMU_CPU5_POP] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(19), 0), + [RESET_APMU_CPU5_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(20), 0), + [RESET_APMU_CPU6_POP] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(22), 0), + [RESET_APMU_CPU6_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(23), 0), + [RESET_APMU_CPU7_POP] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(25), 0), + [RESET_APMU_CPU7_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(26), 0), + [RESET_APMU_C1_MPSUB_SW] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(28), 0), + [RESET_APMU_MPSUB_DBG] =3D RESET_DATA(APMU_PMU_CC2_AP, BIT(29), 0), + [RESET_APMU_UCIE] =3D RESET_DATA(APMU_UCIE_CTRL, + BIT(1) | BIT(2) | BIT(3), 0), + [RESET_APMU_RCPU] =3D RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, + BIT(3) | BIT(2) | BIT(0)), + [RESET_APMU_DSI4LN2_ESCCLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT= (3)), + [RESET_APMU_DSI4LN2_LCD_SW] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT= (4)), + [RESET_APMU_DSI4LN2_LCD_MCLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, B= IT(9)), + [RESET_APMU_DSI4LN2_LCD_DSCCLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0,= BIT(15)), + [RESET_APMU_DSI4LN2_DPU_ACLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL5, 0, B= IT(0)), + [RESET_APMU_DPU_ACLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL5, 0, BIT(15)), + [RESET_APMU_UFS_ACLK] =3D RESET_DATA(APMU_UFS_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_EDP0] =3D RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(0)), + [RESET_APMU_EDP1] =3D RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(16)), + [RESET_APMU_PCIE_PORTA] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, + BIT(5) | BIT(4) | BIT(3)), + [RESET_APMU_PCIE_PORTB] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, + BIT(5) | BIT(4) | BIT(3)), + [RESET_APMU_PCIE_PORTC] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, + BIT(5) | BIT(4) | BIT(3)), + [RESET_APMU_PCIE_PORTD] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, + BIT(5) | BIT(4) | BIT(3)), + [RESET_APMU_PCIE_PORTE] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, + BIT(5) | BIT(4) | BIT(3)), + [RESET_APMU_EMAC0] =3D RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_EMAC1] =3D RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_EMAC2] =3D RESET_DATA(APMU_EMAC2_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_ESPI_MCLK] =3D RESET_DATA(APMU_ESPI_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_ESPI_SCLK] =3D RESET_DATA(APMU_ESPI_CLK_RES_CTRL, 0, BIT(2)), +}; + +static const struct ccu_reset_controller_data k3_apmu_reset_data =3D { + .reset_data =3D k3_apmu_resets, + .count =3D ARRAY_SIZE(k3_apmu_resets), +}; + +static const struct ccu_reset_data k3_dciu_resets[] =3D { + [RESET_DCIU_HDMA] =3D RESET_DATA(DCIU_DMASYS_RSTN, 0, BIT(0)), + [RESET_DCIU_DMA350] =3D RESET_DATA(DCIU_DMASYS_SDMA_RSTN, 0, BIT(0)), + [RESET_DCIU_DMA350_0] =3D RESET_DATA(DCIU_DMASYS_S0_RSTN, 0, BIT(0)), + [RESET_DCIU_DMA350_1] =3D RESET_DATA(DCIU_DMASYS_S1_RSTN, 0, BIT(0)), + [RESET_DCIU_AXIDMA0] =3D RESET_DATA(DCIU_DMASYS_A0_RSTN, 0, BIT(0)), + [RESET_DCIU_AXIDMA1] =3D RESET_DATA(DCIU_DMASYS_A1_RSTN, 0, BIT(0)), + [RESET_DCIU_AXIDMA2] =3D RESET_DATA(DCIU_DMASYS_A2_RSTN, 0, BIT(0)), + [RESET_DCIU_AXIDMA3] =3D RESET_DATA(DCIU_DMASYS_A3_RSTN, 0, BIT(0)), + [RESET_DCIU_AXIDMA4] =3D RESET_DATA(DCIU_DMASYS_A4_RSTN, 0, BIT(0)), + [RESET_DCIU_AXIDMA5] =3D RESET_DATA(DCIU_DMASYS_A5_RSTN, 0, BIT(0)), + [RESET_DCIU_AXIDMA6] =3D RESET_DATA(DCIU_DMASYS_A6_RSTN, 0, BIT(0)), + [RESET_DCIU_AXIDMA7] =3D RESET_DATA(DCIU_DMASYS_A7_RSTN, 0, BIT(0)), +}; + +static const struct ccu_reset_controller_data k3_dciu_reset_data =3D { + .reset_data =3D k3_dciu_resets, + .count =3D ARRAY_SIZE(k3_dciu_resets), +}; + +#define K3_AUX_DEV_ID(_unit) SPACEMIT_AUX_DEV_ID(k3, _unit) + +static const struct auxiliary_device_id spacemit_k3_reset_ids[] =3D { + K3_AUX_DEV_ID(mpmu), + K3_AUX_DEV_ID(apbc), + K3_AUX_DEV_ID(apmu), + K3_AUX_DEV_ID(dciu), + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(auxiliary, spacemit_k3_reset_ids); + +static struct auxiliary_driver spacemit_k3_reset_driver =3D { + .probe =3D spacemit_reset_probe, + .id_table =3D spacemit_k3_reset_ids, +}; +module_auxiliary_driver(spacemit_k3_reset_driver); + +MODULE_IMPORT_NS("RESET_SPACEMIT"); +MODULE_AUTHOR("Guodong Xu "); +MODULE_DESCRIPTION("SpacemiT K3 reset controller driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0