From nobody Sun Feb 8 23:32:47 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C55BE2F39B4 for ; Mon, 29 Dec 2025 10:42:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767004975; cv=none; b=VGCR8vCXD7fbsK+HEHC69zA5VV6dEubzerUwK3VdriO7lMeppDqRCupio+EH008/P+7QIP2cQEO5wHyRsLnTAqNeWrKwChGuK3yRJVBX1QiFl+96D31dIDNaWBJH+GgVhpJHslq5xP2CQd+hg6T7gC/+xG8fBdm5HXOZ/bfpsuM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767004975; c=relaxed/simple; bh=PwDxGVqlPCalaJqsrWiJVP8Bkv6pzkcROQ1PZGyP8Eo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IhffASXexIypUc5ZaFjKniXRxjArchITjX9yZT+AcCp3GHG6wgeNCxqS9f3u8e4DnRqDhypxFK8nHUFvas5czU/2tdkQQD44U1lA6PFUHEKLGpTXPW8qWp0T1mvyHvHgKyvPzS5hNk/xWnJ4kEUZeg2Hjr5QOq5dub80y0RDQEs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=LZebAHCs; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=TdNzUBG5; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="LZebAHCs"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="TdNzUBG5" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BSMurtB013667 for ; Mon, 29 Dec 2025 10:42:52 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= HwdN1Hzsrc+ug6247grY+gZgtiGh816xfGCrunPfDc0=; b=LZebAHCsgQRJVWfr I+cljWa40/K1txRjB2F1ibvInYbxq983UDVddqPM9k1UAbOTBLXFAvHfnQS89F1P A6TUtBe/iIVTMEYbJedF43k2PqAJFTJm3F801Z16QeOVgTPp/ldrKxY/k+4QqG5f /mGgvvtW+CZH+iAfdQba0dhsy9fIYkOMlJ6bNZdts1ZATXvqNHwE3d0d+lT/lr/f LTmgzT6fF5aQlN8yLk8ihkOiOcpQw2tbs3an11Sj0pxSvm8oDmJh7BdRjnnOO5zT pRmeq6t/YNpKpqCZ0F9c/eibTCt1SS6piO9veETgBVu+iVuQ8ea5kn9v4HLEaAi3 mjURzQ== Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ba7u5m336-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 29 Dec 2025 10:42:52 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-29f26fc6476so148463265ad.1 for ; Mon, 29 Dec 2025 02:42:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1767004972; x=1767609772; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=HwdN1Hzsrc+ug6247grY+gZgtiGh816xfGCrunPfDc0=; b=TdNzUBG5s0GxYOLMRvj2EcBO0KMyGDDLT5xuqoWXRVquqhQp1O1fZ5kHFo1qJgTvWT 5GMZiMyb0IhmNmSWSrzwNAhv40/S5LIpyU8wYw54f8RnZ8bIUqIS63nZR81j5rYIsj+t 7v26Zs6jEKU6RT5P5zdJIfEvNH++Mrx/yXb8DIHxw7A3wbY0riCnAkqIEosIYRe7dSZc ikU1osePVjNKF1iFEnGR7IRH0KS1t776xZ9NDRwgg1E2z9MmSebKGGuG5ZcEX7y86LKZ iq68GtQkWliwBGRXd0LT1QBlL6IcsDJ0P16Ayxif+wGvZchxvW1dsEY+D20BnZCCTZAA vOlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767004972; x=1767609772; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=HwdN1Hzsrc+ug6247grY+gZgtiGh816xfGCrunPfDc0=; b=mzfTSKrB358zG12YaPCfthmifJ+9Vy+glM39mzBdTveJeL0ZkuwCKfXgrmjg5OBKvB AKdC/DOzWaDUx+rMReO5y1ymBgFOMi/7lYF7qzISTLoS33FAdmUkgYdVfh4fZJjnsd/R GKPwgcBPFgaibzEHciKWUCoKlf8ZMLnj3H8zuWGXz/ITA+Ci0+f0dvbta3T8WAxK0NUa ofm2WNAtqfuCXVbB06ypMi3NnGu28a0gSBHrvdgHcyFymnMiKKxbda92h6ZjFiuJQEQW r8WWGo95Ye+Wqf3PKuymn4Ua5Gw7GDsdNhsdOzPsQh5XNxsasO35KohLWkufE0othM8J 3Zew== X-Forwarded-Encrypted: i=1; AJvYcCVSYJIlXwMrBmQ/OSlw1qvhA32mHD8MBb8L985OAoat5EII6bNIyORpzWtKprja3FIuNVp7AyUNU01WY6U=@vger.kernel.org X-Gm-Message-State: AOJu0Yy+vOk5mjxX6SATFejggOhnbID/HlMwREWRjoQ6lSMrvUVb6cKc h/lUOn2f6P28E5jA/dkDjn/oRMb0CmobmkwwD92rLLP0DWwDy9clInkYO1tH9e+lE5t9hRRWb1T 8jd5mIy9pVgvfkCtKfgysmsKavlxOj0V1vlxkJqESGCs1DBK6TcKHoFjdkoj0rrSN0KI= X-Gm-Gg: AY/fxX6OkB6MeGs7H9LJaa4jnLCb8wJfy26RFoRlmwURhiwr3puT4dLRdcQcp9LIaLN EQE8smHTMe4FO4MsLKZ+9exlCsAgmXNbqspR2FYVbR3k41VbNryLmEzdPtdqvue2ZqxwJ7YqmxN VON7hRXw8MzZHx0mK33pQJvq5Ud3JJnBIbujOJEThIgmJrURCy3ScAQJrPYMmymmyBzptLmpnDE TmYZ/bSvH4IsTB8yIQgnBPVbjKyjjbrLXOFmE3EqH+pugoHcfTEFdMSZxFTCBNCZcL0R97Tl7rb ASm+xwB7B/eLs2NTwoskJQ22Fp/oi1aE08BScNvyZUXu5y9LdgaRO99gwCN3oGgv5Q8HazTSupd JDxfPpllT18Vrc8KwmdbUIff3368Ch7AGtvifNVuvPIFG X-Received: by 2002:a17:903:228b:b0:24e:3cf2:2453 with SMTP id d9443c01a7336-2a2f2c56453mr290588505ad.61.1767004971742; Mon, 29 Dec 2025 02:42:51 -0800 (PST) X-Google-Smtp-Source: AGHT+IEioKFGNJBNeeqVZgzXmhPFsUS0ACvTBBn1SY4kNRpxoJLiA7uLug0gT1p3bVGZUFUTysadJA== X-Received: by 2002:a17:903:228b:b0:24e:3cf2:2453 with SMTP id d9443c01a7336-2a2f2c56453mr290588295ad.61.1767004971298; Mon, 29 Dec 2025 02:42:51 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a2f3d4cbb7sm273412365ad.59.2025.12.29.02.42.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Dec 2025 02:42:50 -0800 (PST) From: Krishna Chaitanya Chundru Date: Mon, 29 Dec 2025 16:12:41 +0530 Subject: [PATCH v2 1/3] PCI: dwc: Fix skipped index 0 in outbound ATU setup Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251229-ecam_io_fix-v2-1-41a0e56a6faa@oss.qualcomm.com> References: <20251229-ecam_io_fix-v2-0-41a0e56a6faa@oss.qualcomm.com> In-Reply-To: <20251229-ecam_io_fix-v2-0-41a0e56a6faa@oss.qualcomm.com> To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Frank Li , Serge Semin Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, macro@orcam.me.uk, Krishna Chaitanya Chundru , stable@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767004963; l=1914; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=PwDxGVqlPCalaJqsrWiJVP8Bkv6pzkcROQ1PZGyP8Eo=; b=6/isTRmSRgxo+TugjzFqCVCXMPDX9AlprjcXjqTnJ4b5O/wACitsNUSm8zo/yTf6VtJbzGdx1 liJTqd4KMTKAvLR9DeUsgYhTVFsSOAw7YH9bmWMumneoELk0d/+bsEK X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: aw9oLEtGGlS_srVkuT1TBT9SxrXqk7nV X-Proofpoint-ORIG-GUID: aw9oLEtGGlS_srVkuT1TBT9SxrXqk7nV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI5MDA5OSBTYWx0ZWRfX0TE1huJ4FQ9q vWC3vBGRe1fUDrNMQGC0ago3TZGDhRRpEoK2qhvgW9UPMexGMzb8CzkE6Sfr1BFXMGlchhfGsD7 WNqKxn4Figi4rlYDm/GpkY2DZrLSxYwiyPWLxE7LAG+PJztTRoHnF7nOo4qQWYd19UNlPPeUcoB PrxXFcHKNey6R7tCzYIQ4UcBfs4BpEk9XLPpZK87fZvEM88xGpwsc3ixUAVUa31alNjViPX0sk7 ENg+q2/oNozf7ajkQWtP4/rZB+ndg9PJ20baHie+eV+tTZ4PyQlXPgiAalZuXF04CW7GH5Fz7mT lkSO9TJe6JSBxwp6be4zpgXuH46z7W3R3FZ89inqi5YDAyl7YlRtuokHSJHtX0tlrWoae64zxsv OKdDD+NAE1AUl6ynT2LtMXAlqc/RcffYK+m53dFVOA+XBEASGCW+zLxdhiBJ6ZgtmSbRsghOOKY L2UIIC2sFM9/gYFDxbQ== X-Authority-Analysis: v=2.4 cv=DptbOW/+ c=1 sm=1 tr=0 ts=69525b2c cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=5cqX_iqSVL2xjhDF-JMA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-29_03,2025-12-29_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 clxscore=1015 spamscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512290099 In dw_pcie_iatu_setup(), the outbound ATU loop uses a pre-increment on the index and starts programming from 1, effectively skipping index 0. This results in the first outbound window never being configured. Update the logic to start from index 0 and use post-increment (i++) when assigning atu.index. Fixes: ce06bf570390f ("PCI: dwc: Check iATU in/outbound range setup status") Cc: stable@vger.kernel.org Signed-off-by: Krishna Chaitanya Chundru --- Note:- The fix tag shown above is for applying this patch cleanly, further below versions we need to manually apply them, If any one intrested to apply this fix then we can submit another patch based on that kernel version. --- drivers/pci/controller/dwc/pcie-designware-host.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index e92513c5bda51bde3a7157033ddbd73afa370d78..32a26458ed8f1696fe2fdcf9df6= b795c4c761f1f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -896,10 +896,10 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) if (resource_type(entry->res) !=3D IORESOURCE_MEM) continue; =20 - if (pci->num_ob_windows <=3D ++i) + if (pci->num_ob_windows < i) break; =20 - atu.index =3D i; + atu.index =3D i++; atu.type =3D PCIE_ATU_TYPE_MEM; atu.parent_bus_addr =3D entry->res->start - pci->parent_bus_offset; atu.pci_addr =3D entry->res->start - entry->offset; @@ -920,7 +920,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) } =20 if (pp->io_size) { - if (pci->num_ob_windows > ++i) { + if (pci->num_ob_windows > i) { atu.index =3D i; atu.type =3D PCIE_ATU_TYPE_IO; atu.parent_bus_addr =3D pp->io_base - pci->parent_bus_offset; --=20 2.34.1 From nobody Sun Feb 8 23:32:47 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C93D212F98 for ; Mon, 29 Dec 2025 10:42:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767004978; cv=none; b=Te0WXzbxh5uqJJ5Krp8maGekqguAveUe+QFCltbzdqSlly8NDVaHxu3ktlKRj5GDiqSBwVU0XNTDyhdbNcrc09hjz/DJ0IF2fh4D3Ql54C0alTpdULYY0UyHWqSMD+1hxHiQbcGRd/QgwLNE2dFlZNDSOUl/Fx4TURyLnUjrGQE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767004978; c=relaxed/simple; bh=VP/aaC9vMzd9wjGQfa1FtCcLvjnP6IcYIJvaUpBKKaM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jTBpy1gbfMKO7ppkgdWpT3v8cfuqGb57rxzplWnSyNuoFhx5CIYc5W+I0HxHYP53WNkdOjVKHZKr24XmSspXfHXa7cXix0dWqlcOqSocqihTa+OlQIwzsKs/5bdRfByFaCneAaBCempXaNEIhbwmze5453gwsOnFXO5X2XHb+Js= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=BsV5wpN2; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=gz/QtgMN; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="BsV5wpN2"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="gz/QtgMN" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BTA50Ot956298 for ; Mon, 29 Dec 2025 10:42:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= kzja3z4Vcipbec9fpYHnYBIDS9e3pJxHPIAzLcYh1Ig=; b=BsV5wpN2Z0kUVuXG HZvkOHzofXSnbjmJRxt50ni5ke7VnC4c4cFpjsLdsr0NRENC/ffIdvcqIGxPAYSy SF+8nTa7UnkbJFuONJRbRRlYzFZqIgCoA4ma8KQDn1ZssX+19CMn844lXdwIq1sD I13zPPoWzdQ6+UClr9R97IKoJ1nfIJ3gPIRAPYEjneUt0s+Ub6AbiZG9msyDKwhf yu/hCCsF0yFlloq2BZ7phd635OhPwI7rQ4NDGSf6BU8I4qe0VLSd6xuMRfBVnkMw Bb4/rfQXSpj08dGQJ7xVzR/oh/JLF6TWat9f1+CUHMvpZhnV+BHS/gQWDA2/Vw3J gsMqmw== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bbqk1826g-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 29 Dec 2025 10:42:56 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-2a0a0bad5dfso188628615ad.0 for ; Mon, 29 Dec 2025 02:42:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1767004975; x=1767609775; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kzja3z4Vcipbec9fpYHnYBIDS9e3pJxHPIAzLcYh1Ig=; b=gz/QtgMNRk9R0DsP++Vv6J3wAo5CzKPWvGHOn4w+x6KsQ7dV552tD36VXalPosKI0X AeGkzmGtNG3C1yxmtQefGjE8a6XIZ3Ai2dj9f5Yg0Hi1DU5HAzPhGmZM1SpsYVGA317V OrMsOdarJwgyuw9OjIJ66wWvC2D1lJq+4QUNJahHirEzrQLMTnLszTe+NVvGZwYpJggW vuar9+xp5qEQ5isjnAryFlWMODQrCzrZcz9LzthObhDYfeOkNuTVDMSJqpHNSewdZHJq N5WE1GQNCcXRGa8eNy+MY40dVg16vOmybdkuvKgljV3ZPf8kKJQhl9iyFDwuRWbPHae6 w79w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767004975; x=1767609775; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=kzja3z4Vcipbec9fpYHnYBIDS9e3pJxHPIAzLcYh1Ig=; b=ha6osfvRt6giMvWJOVlMWGp80VEddUfSJQ/9WBavSWRKwjs2zR9gfBKxeQ1MsF6Zp8 JPkN7IvV/rN1gosIJvEsCHIL7AxMoPoiKFT7xObBhREF3hepJ/eOKaLVDyLlD3SQSpgP 9T+RvLGtKn+ukn4/3vFvQam5ktEovADTYLE1fQsbNMtSYvU2KzDLg9tXtZzmHIsNvHkP NoOjb2vvIsenr3YmwZ3GuZoSV6s/iJGWSJOj7rKhaVKuxmFg+VbqBUrG9h3zOMno62H/ 0TpBWssKuTILdjns1vgHV3hWvBlU5l/GorohCAkTgRfWJX2djKvO6QyHB9ljDAE6BYx1 Qndg== X-Forwarded-Encrypted: i=1; AJvYcCWzUevu2KggAEyi7Gw47TzTJlYutRfLn+ntRkk7Nzsk//RMe5DTFrd8ImcmigDR2wFKa5fyFe8gLag2p4c=@vger.kernel.org X-Gm-Message-State: AOJu0YzczAyE3akxsZftw1r2GsOmtbrknjpQQkNKXTTHjaCSHqjVxXON JFxH8Vpynoh+YEwpSLxwmhkAlrLR9KAu0bnxXUiscLXg0XtcYGLksevhKPVETYOUQ5fgUZtXRFR AE/jws5GeeAOBG7kT8nB6cVSokYBN9l5uVMR393hYBgTW1cT2uK6WB39+PluG7dqqa/A= X-Gm-Gg: AY/fxX5N7ErWEi1AFi82fnaaxQ9VDHxf80yoSSMaOlaPFVrqewfnKBL5i2CMHCsmwJP hvTQa56heysC6j2AZjSm6p6zzVynx29HnzEbVsV88N2Ufd6EQwlp9Bql33QUWhIU4Y4Xy7DdTRB okEsq09HVEPGNDH+u4kisVgKshkaD2AnkFfZd/zK6IvnL7lsEi5RRZBIeClMAapq2EA4+TzCrT6 pM67oiXS+bUUv3rlr29C677UuatzNGl6ThIQnX9g2sKRKscfSqSC5WhiVveuhnbTIu2cHHwVxl8 HV0LTi94miHhzX5mlP9SYMkREc8cqeH+yP9b1ALkMkjbEXCncuM78txiTs8fw1h/p9CrS5Sc0Gn DMR4lh5cT5B0OTSzrEedyY0um2QO4CMyLdK4Mv59sfkgo X-Received: by 2002:a17:902:d2d2:b0:294:f310:5218 with SMTP id d9443c01a7336-2a2f1f904a0mr319171815ad.0.1767004975459; Mon, 29 Dec 2025 02:42:55 -0800 (PST) X-Google-Smtp-Source: AGHT+IGX7GUdGEZTM1wCnh9H8UUdz+oyV97UmsieHwnd9pMEPTwPfmI0XqXNyycSVuRPz16mzTauSQ== X-Received: by 2002:a17:902:d2d2:b0:294:f310:5218 with SMTP id d9443c01a7336-2a2f1f904a0mr319171605ad.0.1767004975027; Mon, 29 Dec 2025 02:42:55 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a2f3d4cbb7sm273412365ad.59.2025.12.29.02.42.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Dec 2025 02:42:54 -0800 (PST) From: Krishna Chaitanya Chundru Date: Mon, 29 Dec 2025 16:12:42 +0530 Subject: [PATCH v2 2/3] PCI: dwc: Correct iATU index increment for MSG TLP region Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251229-ecam_io_fix-v2-2-41a0e56a6faa@oss.qualcomm.com> References: <20251229-ecam_io_fix-v2-0-41a0e56a6faa@oss.qualcomm.com> In-Reply-To: <20251229-ecam_io_fix-v2-0-41a0e56a6faa@oss.qualcomm.com> To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Frank Li , Serge Semin Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, macro@orcam.me.uk, Krishna Chaitanya Chundru , stable@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767004963; l=2252; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=VP/aaC9vMzd9wjGQfa1FtCcLvjnP6IcYIJvaUpBKKaM=; b=5dUFO/et0Tm1sWu2Ern1mNDF2HinrMfFcY3HFlg6+t4OXMB4gYxy3hq1LQUsu4wKAAJmf4nI3 JKhG1OFq0JeCQnEY2b804iLM9o0zCWBinU1Wl1GekVq08EO63X5Zv0B X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-ORIG-GUID: IXado9pUtXLK5yMGI4lkCOlKhxIxtRWF X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI5MDA5OSBTYWx0ZWRfX0yLcERRHinwN xqhLBo/u82tM4M32xbHDPpXJfA+fvrSJ7aFptO8n1dZVlm147ACK4RB9LWD9Gsv8F0mM/+sqF+k yr1JwBWVCh5fJH/S4T4ZXC2a8zRW2/7BMN+9eBYBbahF7G4mVUdbWLtEFQNhBAu05PGFxqJz+hv Ty9UvbpHm9/nWFBq0e5/JRl1VyKFqdV1ibWVouzXjmfWrcNOF4/3VMkVRQCiQHIs2+rNcTB/C2i KGwThsAQuisuiRgarlAXzFfKvhma4ljaJ0eEBBmAaI3VpOtz0Ckiit1Zv80jgtmR/stLKhD/Pxu EMovPA7t3nZ9M/eLLe25+DaViVaqjwR+/SLr29pJjiNPgr2yX6dNutRZATDmdFR3/EK9hBqNeF6 7wNFa8p071x3CxR+ZRQxFTNZ+bXp9vARQzO69eUfYr5nJUVtrjS0EwbrBFr4LeLn2C7VMAHPHa8 N6K8YOOGuNKf38HQcWA== X-Authority-Analysis: v=2.4 cv=Tf6bdBQh c=1 sm=1 tr=0 ts=69525b30 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=BcPKCTjPAAAA:8 a=8AirrxEcAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=FLJoTJX8p8-1ICVlPiMA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=MNXww67FyIVnWKX2fotq:22 a=ST-jHhOKWsTCqRlWije3:22 X-Proofpoint-GUID: IXado9pUtXLK5yMGI4lkCOlKhxIxtRWF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-29_03,2025-12-29_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 impostorscore=0 suspectscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512290099 Commit e1a4ec1a9520 ("PCI: dwc: Add generic MSG TLP support for sending PME_Turn_Off when system suspend") introduced a mechanism to reserve an iATU window for MSG TLP transactions. However, the code incorrectly assigned pp->msg_atu_index =3D i without incrementing i first, causing the MSG TLP region to reuse the last configured outbound window instead of the next available one. This can cause issue with IO transfers as this can over write iATU configured for IO memory. Fix this by incrementing i before assigning it to msg_atu_index so that the MSG TLP region uses a dedicated iATU entry. Added error logs in dw_pcie_pme_turn_off(). Fixes: e1a4ec1a9520 ("PCI: dwc: Add generic MSG TLP support for sending PME= _Turn_Off when system suspend") Tested-by: Maciej W. Rozycki Reviewed-by: Frank Li Cc: stable@vger.kernel.org Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 32a26458ed8f1696fe2fdcf9df6b795c4c761f1f..88b6ace0607e97bf6dd6bf7886b= aaa13bf267e6e 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -942,7 +942,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n", pci->num_ob_windows); =20 - pp->msg_atu_index =3D i; + pp->msg_atu_index =3D ++i; =20 i =3D 0; resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) { @@ -1113,11 +1113,15 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) void __iomem *mem; int ret; =20 - if (pci->num_ob_windows <=3D pci->pp.msg_atu_index) + if (pci->num_ob_windows <=3D pci->pp.msg_atu_index) { + dev_err(pci->dev, "No available iATU enteries\n"); return -ENOSPC; + } =20 - if (!pci->pp.msg_res) + if (!pci->pp.msg_res) { + dev_err(pci->dev, "Msg resource is not allocated\n"); return -ENOSPC; + } =20 atu.code =3D PCIE_MSG_CODE_PME_TURN_OFF; atu.routing =3D PCIE_MSG_TYPE_R_BC; --=20 2.34.1 From nobody Sun Feb 8 23:32:47 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B80AE2F6596 for ; Mon, 29 Dec 2025 10:43:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767004983; cv=none; b=F+oL3SSmrgiPlii8HPGGAYLSqZahqNVlkioBIZb9mO5o0qAX7/U7fJ4/cosxnz6i5AKYdTRUfDgnqcPqX6GcTssqalQB32IafPa7xyRuq7rL7Do0/H+Kfi3h/v422bYjLlhzseGfluSygf16C0JILqvTqDKZwDqNlxQF7UGWreQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767004983; c=relaxed/simple; bh=hUoI9bnVtJsUGfvg2BaMO4nB7gpZPlLk6e7RaaGAyq0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rCAvuQSxa0UdGxJZJ5s0sxxt941UBa9VMlHDY3lA7ZdtSyU+OrvrSxwLBzoP1XLxwnot2Ryi5Fv+9sRJQCJl+ltoP5gDrl6SyWD9Fyd/15ERPW2zBYsxmK7L5KOGIJ65aM2AWjTFyiYwsFTyTD+Tauwv8/FCT792M0LRpo1DFX8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=dR8+G2Ot; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=ToBjh6wO; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="dR8+G2Ot"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="ToBjh6wO" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BT9UTK21459065 for ; Mon, 29 Dec 2025 10:43:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= n+AJFwEI+sbiPk8ABgsu6UQdCuUqwsgPHB05A+dmaTQ=; b=dR8+G2OtP/rMcTjN 4xIkfO8avBMwnEwQxClRs9H0MZMXdMrmqvMw+3cSIPe1Iw0m+qTTeBPSsFpSDPf8 0id50iVQNLINo8AhHE/H6F1aezd4nQnSUfEAeMrAYvTPGnEYYh+SxjOE/n2lU/eC y5g7iu3qYCnso5Eqqnetg8n161NvBMV/eY2dH9O0WIA2lT3aWvwSmdYxUGf5ultl xY3B8kgGtjReSWyz2oneRcwZwGsnlSoTdDK1frpiDX01rz/ETGuETWBjVlmF073j JJ77bKFuO8LLsIBckm04GHL1nl2jxYMRV8MAN4d3FYDO2fcHJs9tq51Ex+0gVehq kjaEzQ== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bavrj2ju8-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 29 Dec 2025 10:42:59 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-2a0dabc192eso210829625ad.0 for ; Mon, 29 Dec 2025 02:42:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1767004979; x=1767609779; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=n+AJFwEI+sbiPk8ABgsu6UQdCuUqwsgPHB05A+dmaTQ=; b=ToBjh6wOB5gcddtH/w72TY4svvUHVkkglV0AS8W9Wmklfa7fSlN9p7nFmyTOvWHOXC DyxoVFPWXl1TFKXOef4jacPNyrd4MQPZyulhRYtp/1sjflwT/A7X/bG5L4yJyeGOp9O4 Pp1W5brJu7kE/lm2najbFfJueDpZxxHzlTW7UrVYTg5p8cDNxxwZYa1OhrA4ZIRaiLP3 yi3oWqf8IjGVXAJf77SNlcTmMkuzbQXxohiFN9oi0qAy+ShK0AOdgVN/wRxV5nehVB54 LUUoO8p0WHvDUvbtcrBcoKzLGxBx5ONnGvthSOJfJCBePoc7iFOYCLVB/HQcFZLR0eh0 oq2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767004979; x=1767609779; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=n+AJFwEI+sbiPk8ABgsu6UQdCuUqwsgPHB05A+dmaTQ=; b=KOd9bnPZHYhsICspcoFv0IXP75lDRvVBNLOyYzMZrzA2Sd7H8jLkK+GgNYJp0ZABbd F15arZecSxYXkJv/uPxIHZkFrE01OqOwjPi5PN0ri8R1bmFlYBxTPbpI2SRYqZEe0IaA nGMhktkyIqmrtX7kdYqrA0NAE69AZfAj2V1SxsPRVVhDoCxAXaFtZgXR3v8Nms3b78Ec wH3rzRJw2atezH2Wqw1lJU2wuj9sbsdNd3aegnK71/mZzZNER5lzB7Jg6cU+Br1SukxL 1Gb4TVe0tWsat4Uaw8y+DfpSI3Ct2j/48IgWBl5zthK/P/0cF2EbAbIapGUtxZkwq/YQ obZw== X-Forwarded-Encrypted: i=1; AJvYcCWZMPcQoYBwr/r6CjB46uFwd8tbeK6/RbV3zCFacEM0Tbos+WhmFACHKMB5xAnHLMf5nacSyTAcbBMm7wU=@vger.kernel.org X-Gm-Message-State: AOJu0YyYyx7y2856DtfmhWdDe5jjic15NXsyrSsTeEAvwL7DYR76ARgJ M7i2dY87csTzEGkZfsoEruVYdgMaHLPg/la7s1KSPkFngu6cA2SAwWi4ty7dMgbCNM4Z2PwGpUk 4U7cH3c+xTbsLKilyfBX9oVodi8s0QxlaJWU90ozw0592kWWMEdLW6dZzfZBNFRvzBRA= X-Gm-Gg: AY/fxX5pcrQwtIuNyarELTK5KSldE2LzBJd31D3HwBNmGVqcy8x6BUzoA84pzPpsMPO e1LvvPm7IT3Sl3uXIFJ79YEvqfkTufpmKbzzzgJSYmrOVEzojtjelK+C4cjbwQLczaM93vV92JA DPKim1/HjX9GNesrVkNAplZDAb7PreQZOpO+ef0ljlSKXqk3eWhU8ZZAFEzhckzDv1DrluNHw5a /ez/u3sztk3BVgtObElFiIG30p/Sh2IRqsglBOtIRguU312gPo9nt3iEGzsZxwPRhryeq9HR3AB 4dhn9iqvE4zoYLeA1MrONFUnXJzmyDMGTWH3/vJK0G/CbXs8cA9BZZkS1TAqyUoTUpvo8FJbiTQ LhRk1BYZfFXWVI5z7v5+KmSq3p3lLsHwpasY2nGOU4ofR X-Received: by 2002:a17:903:2301:b0:294:f6b4:9a42 with SMTP id d9443c01a7336-2a2f21fad06mr240902185ad.9.1767004979129; Mon, 29 Dec 2025 02:42:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IFK2JAXp6jiF2G/SzUfcNJxYSaeUtWfOmyekVWWyTt9ngR/qKufhrxqS8eoLKj8J3oZe9EZ1A== X-Received: by 2002:a17:903:2301:b0:294:f6b4:9a42 with SMTP id d9443c01a7336-2a2f21fad06mr240902045ad.9.1767004978627; Mon, 29 Dec 2025 02:42:58 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a2f3d4cbb7sm273412365ad.59.2025.12.29.02.42.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Dec 2025 02:42:58 -0800 (PST) From: Krishna Chaitanya Chundru Date: Mon, 29 Dec 2025 16:12:43 +0530 Subject: [PATCH v2 3/3] PCI: dwc: Fix missing iATU setup when ECAM is enabled Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251229-ecam_io_fix-v2-3-41a0e56a6faa@oss.qualcomm.com> References: <20251229-ecam_io_fix-v2-0-41a0e56a6faa@oss.qualcomm.com> In-Reply-To: <20251229-ecam_io_fix-v2-0-41a0e56a6faa@oss.qualcomm.com> To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Frank Li , Serge Semin Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, macro@orcam.me.uk, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767004963; l=6757; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=hUoI9bnVtJsUGfvg2BaMO4nB7gpZPlLk6e7RaaGAyq0=; b=al7P/isFpZ/QZO+wz6kSBvOg0aA9uGmCPSM7TZqUgYJZyWxrnrqXTee00SHNwLnddKcMUnGnb xOruE3dzhOtAqDNrmjL9O850mKsqGk8a1tqbYNrUx5Oou9fovrH2Au9 X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-ORIG-GUID: w_WE0QXgINdLOFMjfz6DBjKvd_-ezsbt X-Proofpoint-GUID: w_WE0QXgINdLOFMjfz6DBjKvd_-ezsbt X-Authority-Analysis: v=2.4 cv=coiWUl4i c=1 sm=1 tr=0 ts=69525b33 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=BcPKCTjPAAAA:8 a=EUspDBNiAAAA:8 a=opeatF3ZsncwF_PLLlkA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=MNXww67FyIVnWKX2fotq:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI5MDA5OSBTYWx0ZWRfX0rMHGZTaowLI e/HuekX0PLnmpAhbNKYfBelHZDLivd/I91UZ0nCfBx4YAnlResc8EluJquwSbJaf4kXhyNNkuJv nP6LHTL9qagk3sY2KHa9UmN0bEdGQDdyrtDNb0fvtmmUOe4/CwkzwjucXdnXuAHDMpMYE00yVRw icyTJv64FM5uMyCTymJTD51f/xqwewffPQuR2f75xdvI/okwsL1alqX7q1oouTW2LyuXaeZfuMz KkVnamRRiGkPwiJ0eh/ti2yX5lE/t2M2sX+aYJD6SQ9QEmtVj+/kTh9tjqZ+cdDAoHcCDsdhVp2 iZzbppV2uQs4kcuCY8HltXVps05ufbQT5nxRvdVCKHQHw+1uQM6TZ92/4YiGliXgNx3FPxx7bfa N5FA5UOM2K+Fv7AztQ+KDfE0hnttT5B9RLDwaFmRQgrIcjVmT+Ol5eKCr8iWvJ4ylOk5nVJcJ1d T+mxSNwN10djAzUTqvQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-29_03,2025-12-29_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 malwarescore=0 phishscore=0 adultscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512290099 When ECAM is enabled, the driver skipped calling dw_pcie_iatu_setup() before configuring ECAM iATU entries. This left IO and MEM outbound windows unprogrammed, resulting in broken IO transactions. Additionally, dw_pcie_config_ecam_iatu() was only called during host initialization, so ECAM-related iATU entries were not restored after suspend/resume, leading to failures in configuration space access To resolve these issues, the ECAM iATU configuration is moved into dw_pcie_setup_rc(). At the same time, dw_pcie_iatu_setup() is invoked when ECAM is enabled. Rename msg_atu_index to ob_atu_index to track the next available outbound iATU index for ECAM and MSG TLP windows. Furthermore, an error check is added in dw_pcie_prog_outbound_atu() to avoid programming beyond num_ob_windows. Fixes: f6fd357f7afb ("PCI: dwc: Prepare the driver for enabling ECAM mechan= ism using iATU 'CFG Shift Feature'") Reported-by: Maciej W. Rozycki Closes: https://lore.kernel.org/all/alpine.DEB.2.21.2511280256260.36486@ang= ie.orcam.me.uk/ Tested-by: Maciej W. Rozycki Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 41 ++++++++++++++-----= ---- drivers/pci/controller/dwc/pcie-designware.c | 3 ++ drivers/pci/controller/dwc/pcie-designware.h | 2 +- 3 files changed, 29 insertions(+), 17 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 88b6ace0607e97bf6dd6bf7886baaa13bf267e6e..cb1b5b2a2fe61eb5901e57a60f8= f333b1c3e766b 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -430,10 +430,10 @@ static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp= *pp) /* * Root bus under the host bridge doesn't require any iATU configuration * as DBI region will be used to access root bus config space. - * Immediate bus under Root Bus, needs type 0 iATU configuration and + * Immediate bus under Root Bus needs type 0 iATU configuration and * remaining buses need type 1 iATU configuration. */ - atu.index =3D 0; + atu.index =3D pci->ob_atu_index; atu.type =3D PCIE_ATU_TYPE_CFG0; atu.parent_bus_addr =3D pp->cfg0_base + SZ_1M; /* 1MiB is to cover 1 (bus) * 32 (devices) * 8 (functions) */ @@ -443,6 +443,8 @@ static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp *= pp) if (ret) return ret; =20 + pci->ob_atu_index++; + bus_range_max =3D resource_size(bus->res); =20 if (bus_range_max < 2) @@ -455,7 +457,13 @@ static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp = *pp) atu.size =3D (SZ_1M * bus_range_max) - SZ_2M; atu.ctrl2 =3D PCIE_ATU_CFG_SHIFT_MODE_ENABLE; =20 - return dw_pcie_prog_outbound_atu(pci, &atu); + ret =3D dw_pcie_prog_outbound_atu(pci, &atu); + if (ret) + return ret; + + pci->ob_atu_index++; + + return 0; } =20 static int dw_pcie_create_ecam_window(struct dw_pcie_rp *pp, struct resour= ce *res) @@ -630,14 +638,6 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (ret) goto err_free_msi; =20 - if (pp->ecam_enabled) { - ret =3D dw_pcie_config_ecam_iatu(pp); - if (ret) { - dev_err(dev, "Failed to configure iATU in ECAM mode\n"); - goto err_free_msi; - } - } - /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends @@ -942,7 +942,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n", pci->num_ob_windows); =20 - pp->msg_atu_index =3D ++i; + pci->ob_atu_index =3D ++i; =20 i =3D 0; resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) { @@ -1084,14 +1084,23 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) /* * If the platform provides its own child bus config accesses, it means * the platform uses its own address translation component rather than - * ATU, so we should not program the ATU here. + * ATU, so we should not program the ATU here. If ECAM is enabled, + * config space access goes through ATU, so set up ATU here. */ - if (pp->bridge->child_ops =3D=3D &dw_child_pcie_ops) { + if (pp->bridge->child_ops =3D=3D &dw_child_pcie_ops || pp->ecam_enabled) { ret =3D dw_pcie_iatu_setup(pp); if (ret) return ret; } =20 + if (pp->ecam_enabled) { + ret =3D dw_pcie_config_ecam_iatu(pp); + if (ret) { + dev_err(pci->dev, "Failed to configure iATU in ECAM mode\n"); + return ret; + } + } + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); =20 /* Program correct class for RC */ @@ -1113,7 +1122,7 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) void __iomem *mem; int ret; =20 - if (pci->num_ob_windows <=3D pci->pp.msg_atu_index) { + if (pci->num_ob_windows <=3D pci->ob_atu_index) { dev_err(pci->dev, "No available iATU enteries\n"); return -ENOSPC; } @@ -1127,7 +1136,7 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) atu.routing =3D PCIE_MSG_TYPE_R_BC; atu.type =3D PCIE_ATU_TYPE_MSG; atu.size =3D resource_size(pci->pp.msg_res); - atu.index =3D pci->pp.msg_atu_index; + atu.index =3D pci->ob_atu_index; =20 atu.parent_bus_addr =3D pci->pp.msg_res->start - pci->parent_bus_offset; =20 diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index c644216995f69cbf065e61a0392bf1e5e32cf56e..f9f3c2f3532e0d0e9f8e4f42d8c= 5c9db68d55272 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -476,6 +476,9 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u32 retries, val; u64 limit_addr; =20 + if (atu->index > pci->num_ob_windows) + return -ENOSPC; + limit_addr =3D parent_bus_addr + atu->size - 1; =20 if ((limit_addr & ~pci->region_limit) !=3D (parent_bus_addr & ~pci->regio= n_limit) || diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index e995f692a1ecd10130d3be3358827f801811387f..efbcc141a26e179cb2e4acf6d2d= 19d75535ddb91 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -424,7 +424,6 @@ struct dw_pcie_rp { raw_spinlock_t lock; DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); bool use_atu_msg; - int msg_atu_index; struct resource *msg_res; bool use_linkup_irq; struct pci_eq_presets presets; @@ -502,6 +501,7 @@ struct dw_pcie { resource_size_t atu_phys_addr; size_t atu_size; resource_size_t parent_bus_offset; + int ob_atu_index; u32 num_ib_windows; u32 num_ob_windows; u32 region_align; --=20 2.34.1