From nobody Mon Feb 9 07:57:32 2026 Received: from smtp.gentoo.org (woodpecker.gentoo.org [140.211.166.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F5A031327E; Mon, 29 Dec 2025 12:47:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=140.211.166.183 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767012446; cv=none; b=rTaImbkygea3LOoWmXxR9/kRvN4UOf430z2M8pJ5D1Kk31H744GSSMnQATwXV6wKRZtY0KO1V0NLOpeeVKoSEDcxSSbD8Ph8WfS02IXsRIk4GsVU3nCS3o77CkbhdUVkthhya08KgGTIWDd3Cqa2QjuAUBmycXJzwqkT01LYsjM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767012446; c=relaxed/simple; bh=3Gk6q/GnszEdN5C4ic9teAA1/nlkqjFF8harrMGyQTg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eG7rn22JdqUYXXUkaLbdXzDFM0biH5xXP6i12P3Tf28ajLdpM7AkUc3bCxt5y+t85nw9NRtdpFcYJCrcFxB+vAiB7ofv+fWQrHDoDEaz4Y8lcHJdy6b/n5nYTZNmp4TOYaQhLu8lYcH4fSs9AgslT+El4Php7UkP5WGjE1hHPs4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gentoo.org; spf=pass smtp.mailfrom=gentoo.org; arc=none smtp.client-ip=140.211.166.183 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gentoo.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gentoo.org Received: from [127.0.0.1] (unknown [116.232.18.222]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dlan) by smtp.gentoo.org (Postfix) with ESMTPSA id 12006340E2A; Mon, 29 Dec 2025 12:47:19 +0000 (UTC) From: Yixun Lan Date: Mon, 29 Dec 2025 20:46:38 +0800 Subject: [PATCH 1/2] dt-bindings: gpio: spacemit: add compatible name for K3 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251229-02-k3-gpio-v1-1-269e76785abb@gentoo.org> References: <20251229-02-k3-gpio-v1-0-269e76785abb@gentoo.org> In-Reply-To: <20251229-02-k3-gpio-v1-0-269e76785abb@gentoo.org> To: Bartosz Golaszewski , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Yixun Lan X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=780; i=dlan@gentoo.org; h=from:subject:message-id; bh=3Gk6q/GnszEdN5C4ic9teAA1/nlkqjFF8harrMGyQTg=; b=owEB6QIW/ZANAwAKATGq6kdZTbvtAcsmYgBpUnhMjHomYPwXglxIczDQWC8aDotR/ybUJNN4w I38SmUU7WCJAq8EAAEKAJkWIQS1urjJwxtxFWcCI9wxqupHWU277QUCaVJ4TBsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMSwyLDJfFIAAAAAALgAoaXNzdWVyLWZwckBub3RhdGlvbnMub3BlbnBncC5 maWZ0aGhvcnNlbWFuLm5ldEI1QkFCOEM5QzMxQjcxMTU2NzAyMjNEQzMxQUFFQTQ3NTk0REJCRU QACgkQMarqR1lNu+0iJA/7BTCBPNPm1sPBLl0v4cH2cc0djOiTaVFPUxBfpebvvPrvQvRski0vN i4R1m3b0AWXJGcsJmrQ5Xkf0ELpFkJOs4/GbAJHUyIvDcaxgNo9Wy35oKQpSxsVAi1lfpFoCUtt pSW9Q1nh1QcawWLNs/dQ9rSYcSbs8NjcbvCcFppdZwq2E8QmgiLlw881h6iaScYd2w71EjjChS6 w0i1m4xmz8GxdwZ2frb0/3qkwLI591DHdsUz57SBwJPimp5x14e9vCz8SZDLOPcu0lKmDQUe8UX BYpiIJRnYkd13pzTf4WJ0zBiTZF/4HkhI4sGpZEx6lv9Yb7Xh+6ITFGqIKfQPHHB0MvYsrzDRXk uFVKXRTdvLVU5xmSZUAb1ySW/ak8eQKvgHON1tzuiJaTDYOGEiYWNeRIYFWS3jf0zDGboUt4xax fZi9VheGSbY83oF+oNGkzlCq8DXDbRzW83nnC3fu+k/3zvZtJsnOkS4gbz5hbP3iWZsTuT/8eYn faJ+tDLwLxwc570LMQnVwArnlHc7rYrb4UI9JPGGgXaD+S/lsbCX0FbEkofhELdCx+9TSVw38Do 8Exc3pcS0L09CXWR5ZqDYpC/XEruIBvuvF0K/a40lMhsvKp91AEgZvekFzT+tTbn3kAMZZG4aZA AIImMbRw81dx50gE5XmEZdZDN1tgII= X-Developer-Key: i=dlan@gentoo.org; a=openpgp; fpr=50B03A1A5CBCD33576EF8CD7920C0DBCAABEFD55 Add new compatible string for SpacemiT K3 SoC's GPIO controller. Signed-off-by: Yixun Lan Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml b= /Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml index 83e0b2d14c9f..24d22d95665f 100644 --- a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml @@ -19,7 +19,9 @@ properties: pattern: "^gpio@[0-9a-f]+$" =20 compatible: - const: spacemit,k1-gpio + enum: + - spacemit,k1-gpio + - spacemit,k3-gpio =20 reg: maxItems: 1 --=20 2.52.0 From nobody Mon Feb 9 07:57:32 2026 Received: from smtp.gentoo.org (woodpecker.gentoo.org [140.211.166.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67DF3313E23; Mon, 29 Dec 2025 12:47:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=140.211.166.183 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767012450; cv=none; b=ijCJGg/hN1mjgZ+YILUAHMNF2xvn0d53ZejIH0ABsrYQ2ZatJoj/+pF8+zN33i6ZZ6JnwL7a06lOlgqdb1whoAMp07UNBpMPKTLQF0xji2p1XzYQw6M1bevdiSuM7z/rVtuOdjyt9Z9uZ7q495q4qaKoeLOVqzTeMGmnBU3D/6Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767012450; c=relaxed/simple; bh=cUG+351/SqJFzMLi6ntkQtD1YOdIRvw1GHtqppBmLbw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JmnPZmUKUvI7hFBNNvVALPiT6LS5faEvxyVlqRGl/KKenqmoxKnS+Uy3SX8vIXdzEc44AnC1e3Zvvg/UN4dwJdqkxcU2Bq6YRZeqzy7u/kkjR0tDDuTGoNPq7HUp1bI8OPqA2ILdQToZcPkX117hOyw19lFWNRVV1xp1GVg2UHU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gentoo.org; spf=pass smtp.mailfrom=gentoo.org; arc=none smtp.client-ip=140.211.166.183 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gentoo.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gentoo.org Received: from [127.0.0.1] (unknown [116.232.18.222]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dlan) by smtp.gentoo.org (Postfix) with ESMTPSA id 93FD5340E0F; Mon, 29 Dec 2025 12:47:24 +0000 (UTC) From: Yixun Lan Date: Mon, 29 Dec 2025 20:46:39 +0800 Subject: [PATCH 2/2] gpio: spacemit: Add GPIO support for K3 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251229-02-k3-gpio-v1-2-269e76785abb@gentoo.org> References: <20251229-02-k3-gpio-v1-0-269e76785abb@gentoo.org> In-Reply-To: <20251229-02-k3-gpio-v1-0-269e76785abb@gentoo.org> To: Bartosz Golaszewski , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Yixun Lan X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=10389; i=dlan@gentoo.org; h=from:subject:message-id; bh=cUG+351/SqJFzMLi6ntkQtD1YOdIRvw1GHtqppBmLbw=; b=owEB6QIW/ZANAwAKATGq6kdZTbvtAcsmYgBpUnhPRx8jW8+ltNgtvnOauDuKzzW2Mj5AGNLZd xqAFKcLZW2JAq8EAAEKAJkWIQS1urjJwxtxFWcCI9wxqupHWU277QUCaVJ4TxsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMSwyLDJfFIAAAAAALgAoaXNzdWVyLWZwckBub3RhdGlvbnMub3BlbnBncC5 maWZ0aGhvcnNlbWFuLm5ldEI1QkFCOEM5QzMxQjcxMTU2NzAyMjNEQzMxQUFFQTQ3NTk0REJCRU QACgkQMarqR1lNu+1g4g//Yz/70gPbLjO5xOTgTVaFaIhL/Suw2P6HrfZJhAcoVLBkMpEsqzbRn FAMnX8jREtRpbnh2zhK1Kw4bNNULyDHWLTdWQZtX5+BKFU/rYFLq2EalgRTgaoQnFc0zIPfOSEI 3TW7qfK5ORK02WfFr4y7IFNtxzd9lhIaKvjmgtE/sx5NOpX9uYQvh+27xMzltMWpkPN859WUYuR qJbko9RSOuIMMrG7zlw9IhVGzCHHk0gknHeLqNm4rQx8VnR6IO86TFoBWM05TsP0c0zaUhLP/VT 4cqTSod8YDtOS45truD332hwfXDJYwFDHLftQYaiVzW3uWyw8gOgra3xQVzPJWbQsg3mzuDbpd0 ENFuSNJ0H4VdLEDE0p08yHIJE/WPfFutkJ75RPmhqIl064c+8Q0eNIN4hqIwahhDMy/p2iqvUFc A0yqRFvQopfizmh+PXHPDUnKOM/d04CUk+T8CXlFZfXIw4qeX9mtz4fozJ7xkPJpvVKHRv22K+L 918JF1L/0zro68FM/1pN9JqeebRNLVxC0SwJltI8BkcRShlt/uzNXQX0/O1HhF0gUIgyUhU1dVA YPpxCmzOS7U+MzXZubSyJXNKGuKVD6Dj50b199d9mDNRjyPNabTwSBQWHIqyP+7VTC566HHdnoe MJHYY+tllmC2MMXWaBucnZC2zn92KA= X-Developer-Key: i=dlan@gentoo.org; a=openpgp; fpr=50B03A1A5CBCD33576EF8CD7920C0DBCAABEFD55 SpacemiT K3 SoC has changed gpio register layout while comparing with previous generation, the register offset and bank offset need to be adjusted, introduce a compatible data to extend the driver to support this. Signed-off-by: Yixun Lan --- drivers/gpio/gpio-spacemit-k1.c | 150 ++++++++++++++++++++++++++++--------= ---- 1 file changed, 106 insertions(+), 44 deletions(-) diff --git a/drivers/gpio/gpio-spacemit-k1.c b/drivers/gpio/gpio-spacemit-k= 1.c index eb66a15c002f..02cc5c11b617 100644 --- a/drivers/gpio/gpio-spacemit-k1.c +++ b/drivers/gpio/gpio-spacemit-k1.c @@ -15,28 +15,19 @@ #include #include =20 -/* register offset */ -#define SPACEMIT_GPLR 0x00 /* port level - R */ -#define SPACEMIT_GPDR 0x0c /* port direction - R/W */ -#define SPACEMIT_GPSR 0x18 /* port set - W */ -#define SPACEMIT_GPCR 0x24 /* port clear - W */ -#define SPACEMIT_GRER 0x30 /* port rising edge R/W */ -#define SPACEMIT_GFER 0x3c /* port falling edge R/W */ -#define SPACEMIT_GEDR 0x48 /* edge detect status - R/W1C */ -#define SPACEMIT_GSDR 0x54 /* (set) direction - W */ -#define SPACEMIT_GCDR 0x60 /* (clear) direction - W */ -#define SPACEMIT_GSRER 0x6c /* (set) rising edge detect enable - W */ -#define SPACEMIT_GCRER 0x78 /* (clear) rising edge detect enable - W */ -#define SPACEMIT_GSFER 0x84 /* (set) falling edge detect enable - W */ -#define SPACEMIT_GCFER 0x90 /* (clear) falling edge detect enable - W */ -#define SPACEMIT_GAPMASK 0x9c /* interrupt mask , 0 disable, 1 enable - R/= W */ - #define SPACEMIT_NR_BANKS 4 #define SPACEMIT_NR_GPIOS_PER_BANK 32 =20 #define to_spacemit_gpio_bank(x) container_of((x), struct spacemit_gpio_ba= nk, gc) +#define to_spacemit_gpio_regs(sg) ((sg)->data->reg_offsets) =20 struct spacemit_gpio; +struct spacemit_gpio_reg_offsets; + +struct spacemit_gpio_data { + struct spacemit_gpio_reg_offsets *reg_offsets; + u32 bank_offsets[4]; +}; =20 struct spacemit_gpio_bank { struct gpio_generic_chip chip; @@ -49,9 +40,28 @@ struct spacemit_gpio_bank { =20 struct spacemit_gpio { struct device *dev; + const struct spacemit_gpio_data *data; struct spacemit_gpio_bank sgb[SPACEMIT_NR_BANKS]; }; =20 +struct spacemit_gpio_reg_offsets { + u32 gplr; /* port level - R */ + u32 gpdr; /* port direction - R/W */ + u32 gpsr; /* port set - W */ + u32 gpcr; /* port clear - W */ + u32 grer; /* port rising edge R/W */ + u32 gfer; /* port falling edge R/W */ + u32 gedr; /* edge detect status - R/W1C */ + u32 gsdr; /* (set) direction - W */ + u32 gcdr; /* (clear) direction - W */ + u32 gsrer; /* (set) rising edge detect enable - W */ + u32 gcrer; /* (clear) rising edge detect enable - W */ + u32 gsfer; /* (set) falling edge detect enable - W */ + u32 gcfer; /* (clear) falling edge detect enable - W */ + u32 gapmask; /* interrupt mask , 0 disable, 1 enable - R/W */ + u32 gcpmask; /* interrupt mask for K3 */ +}; + static u32 spacemit_gpio_bank_index(struct spacemit_gpio_bank *gb) { return (u32)(gb - gb->sg->sgb); @@ -60,13 +70,14 @@ static u32 spacemit_gpio_bank_index(struct spacemit_gpi= o_bank *gb) static irqreturn_t spacemit_gpio_irq_handler(int irq, void *dev_id) { struct spacemit_gpio_bank *gb =3D dev_id; + struct spacemit_gpio *sg =3D gb->sg; unsigned long pending; u32 n, gedr; =20 - gedr =3D readl(gb->base + SPACEMIT_GEDR); + gedr =3D readl(gb->base + to_spacemit_gpio_regs(sg)->gedr); if (!gedr) return IRQ_NONE; - writel(gedr, gb->base + SPACEMIT_GEDR); + writel(gedr, gb->base + to_spacemit_gpio_regs(sg)->gedr); =20 pending =3D gedr & gb->irq_mask; if (!pending) @@ -81,60 +92,64 @@ static irqreturn_t spacemit_gpio_irq_handler(int irq, v= oid *dev_id) static void spacemit_gpio_irq_ack(struct irq_data *d) { struct spacemit_gpio_bank *gb =3D irq_data_get_irq_chip_data(d); + struct spacemit_gpio *sg =3D gb->sg; =20 - writel(BIT(irqd_to_hwirq(d)), gb->base + SPACEMIT_GEDR); + writel(BIT(irqd_to_hwirq(d)), gb->base + to_spacemit_gpio_regs(sg)->gedr); } =20 static void spacemit_gpio_irq_mask(struct irq_data *d) { struct spacemit_gpio_bank *gb =3D irq_data_get_irq_chip_data(d); + struct spacemit_gpio *sg =3D gb->sg; u32 bit =3D BIT(irqd_to_hwirq(d)); =20 gb->irq_mask &=3D ~bit; - writel(gb->irq_mask, gb->base + SPACEMIT_GAPMASK); + writel(gb->irq_mask, gb->base + to_spacemit_gpio_regs(sg)->gapmask); =20 if (bit & gb->irq_rising_edge) - writel(bit, gb->base + SPACEMIT_GCRER); + writel(bit, gb->base + to_spacemit_gpio_regs(sg)->gcrer); =20 if (bit & gb->irq_falling_edge) - writel(bit, gb->base + SPACEMIT_GCFER); + writel(bit, gb->base + to_spacemit_gpio_regs(sg)->gcfer); } =20 static void spacemit_gpio_irq_unmask(struct irq_data *d) { struct spacemit_gpio_bank *gb =3D irq_data_get_irq_chip_data(d); + struct spacemit_gpio *sg =3D gb->sg; u32 bit =3D BIT(irqd_to_hwirq(d)); =20 gb->irq_mask |=3D bit; =20 if (bit & gb->irq_rising_edge) - writel(bit, gb->base + SPACEMIT_GSRER); + writel(bit, gb->base + to_spacemit_gpio_regs(sg)->gsrer); =20 if (bit & gb->irq_falling_edge) - writel(bit, gb->base + SPACEMIT_GSFER); + writel(bit, gb->base + to_spacemit_gpio_regs(sg)->gsfer); =20 - writel(gb->irq_mask, gb->base + SPACEMIT_GAPMASK); + writel(gb->irq_mask, gb->base + to_spacemit_gpio_regs(sg)->gapmask); } =20 static int spacemit_gpio_irq_set_type(struct irq_data *d, unsigned int typ= e) { struct spacemit_gpio_bank *gb =3D irq_data_get_irq_chip_data(d); + struct spacemit_gpio *sg =3D gb->sg; u32 bit =3D BIT(irqd_to_hwirq(d)); =20 if (type & IRQ_TYPE_EDGE_RISING) { gb->irq_rising_edge |=3D bit; - writel(bit, gb->base + SPACEMIT_GSRER); + writel(bit, gb->base + to_spacemit_gpio_regs(sg)->gsrer); } else { gb->irq_rising_edge &=3D ~bit; - writel(bit, gb->base + SPACEMIT_GCRER); + writel(bit, gb->base + to_spacemit_gpio_regs(sg)->gcrer); } =20 if (type & IRQ_TYPE_EDGE_FALLING) { gb->irq_falling_edge |=3D bit; - writel(bit, gb->base + SPACEMIT_GSFER); + writel(bit, gb->base + to_spacemit_gpio_regs(sg)->gsfer); } else { gb->irq_falling_edge &=3D ~bit; - writel(bit, gb->base + SPACEMIT_GCFER); + writel(bit, gb->base + to_spacemit_gpio_regs(sg)->gcfer); } =20 return 0; @@ -179,15 +194,15 @@ static int spacemit_gpio_add_bank(struct spacemit_gpi= o *sg, struct device *dev =3D sg->dev; struct gpio_irq_chip *girq; void __iomem *dat, *set, *clr, *dirin, *dirout; - int ret, bank_base[] =3D { 0x0, 0x4, 0x8, 0x100 }; + int ret; =20 - gb->base =3D regs + bank_base[index]; + gb->base =3D regs + sg->data->bank_offsets[index]; =20 - dat =3D gb->base + SPACEMIT_GPLR; - set =3D gb->base + SPACEMIT_GPSR; - clr =3D gb->base + SPACEMIT_GPCR; - dirin =3D gb->base + SPACEMIT_GCDR; - dirout =3D gb->base + SPACEMIT_GSDR; + dat =3D gb->base + to_spacemit_gpio_regs(sg)->gplr; + set =3D gb->base + to_spacemit_gpio_regs(sg)->gpsr; + clr =3D gb->base + to_spacemit_gpio_regs(sg)->gpcr; + dirin =3D gb->base + to_spacemit_gpio_regs(sg)->gcdr; + dirout =3D gb->base + to_spacemit_gpio_regs(sg)->gsdr; =20 config =3D (struct gpio_generic_chip_config) { .dev =3D dev, @@ -223,13 +238,13 @@ static int spacemit_gpio_add_bank(struct spacemit_gpi= o *sg, gpio_irq_chip_set_chip(girq, &spacemit_gpio_chip); =20 /* Disable Interrupt */ - writel(0, gb->base + SPACEMIT_GAPMASK); + writel(0, gb->base + to_spacemit_gpio_regs(sg)->gapmask); /* Disable Edge Detection Settings */ - writel(0x0, gb->base + SPACEMIT_GRER); - writel(0x0, gb->base + SPACEMIT_GFER); + writel(0x0, gb->base + to_spacemit_gpio_regs(sg)->grer); + writel(0x0, gb->base + to_spacemit_gpio_regs(sg)->gfer); /* Clear Interrupt */ - writel(0xffffffff, gb->base + SPACEMIT_GCRER); - writel(0xffffffff, gb->base + SPACEMIT_GCFER); + writel(0xffffffff, gb->base + to_spacemit_gpio_regs(sg)->gcrer); + writel(0xffffffff, gb->base + to_spacemit_gpio_regs(sg)->gcfer); =20 ret =3D devm_request_threaded_irq(dev, irq, NULL, spacemit_gpio_irq_handler, @@ -260,6 +275,10 @@ static int spacemit_gpio_probe(struct platform_device = *pdev) if (!sg) return -ENOMEM; =20 + sg->data =3D of_device_get_match_data(dev); + if (!sg->data) + return dev_err_probe(dev, -EINVAL, "No available compatible data."); + regs =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(regs)) return PTR_ERR(regs); @@ -287,8 +306,51 @@ static int spacemit_gpio_probe(struct platform_device = *pdev) return 0; } =20 +static const struct spacemit_gpio_data k1_gpio_data =3D { + .reg_offsets =3D &(struct spacemit_gpio_reg_offsets) { + .gplr =3D 0x00, + .gpdr =3D 0x0c, + .gpsr =3D 0x18, + .gpcr =3D 0x24, + .grer =3D 0x30, + .gfer =3D 0x3c, + .gedr =3D 0x48, + .gsdr =3D 0x54, + .gcdr =3D 0x60, + .gsrer =3D 0x6c, + .gcrer =3D 0x78, + .gsfer =3D 0x84, + .gcfer =3D 0x90, + .gapmask =3D 0x9c, + .gcpmask =3D 0xA8, + }, + .bank_offsets =3D { 0x0, 0x4, 0x8, 0x100 }, +}; + +static const struct spacemit_gpio_data k3_gpio_data =3D { + .reg_offsets =3D &(struct spacemit_gpio_reg_offsets) { + .gplr =3D 0x0, + .gpdr =3D 0x4, + .gpsr =3D 0x8, + .gpcr =3D 0xc, + .grer =3D 0x10, + .gfer =3D 0x14, + .gedr =3D 0x18, + .gsdr =3D 0x1c, + .gcdr =3D 0x20, + .gsrer =3D 0x24, + .gcrer =3D 0x28, + .gsfer =3D 0x2c, + .gcfer =3D 0x30, + .gapmask =3D 0x34, + .gcpmask =3D 0x38, + }, + .bank_offsets =3D { 0x0, 0x40, 0x80, 0x100 }, +}; + static const struct of_device_id spacemit_gpio_dt_ids[] =3D { - { .compatible =3D "spacemit,k1-gpio" }, + { .compatible =3D "spacemit,k1-gpio", .data =3D &k1_gpio_data }, + { .compatible =3D "spacemit,k3-gpio", .data =3D &k3_gpio_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, spacemit_gpio_dt_ids); @@ -296,12 +358,12 @@ MODULE_DEVICE_TABLE(of, spacemit_gpio_dt_ids); static struct platform_driver spacemit_gpio_driver =3D { .probe =3D spacemit_gpio_probe, .driver =3D { - .name =3D "k1-gpio", + .name =3D "spacemit-gpio", .of_match_table =3D spacemit_gpio_dt_ids, }, }; module_platform_driver(spacemit_gpio_driver); =20 MODULE_AUTHOR("Yixun Lan "); -MODULE_DESCRIPTION("GPIO driver for SpacemiT K1 SoC"); +MODULE_DESCRIPTION("GPIO driver for SpacemiT K1/K3 SoC"); MODULE_LICENSE("GPL"); --=20 2.52.0