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So add the graph port to establish link between the SATA Port and the connector node. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/ata/sata-common.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/ata/sata-common.yaml b/Docum= entation/devicetree/bindings/ata/sata-common.yaml index 58c9342b9925..97cd69ebf331 100644 --- a/Documentation/devicetree/bindings/ata/sata-common.yaml +++ b/Documentation/devicetree/bindings/ata/sata-common.yaml @@ -54,4 +54,7 @@ $defs: each port can have a Port Multiplier attached thus allowing to access more than one drive by means of a single SATA port. =20 + port: + $ref: /schemas/graph.yaml#/properties/port + ... --=20 2.48.1 From nobody Sun Feb 8 20:28:24 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F3E11D86FF for ; Sun, 28 Dec 2025 17:01:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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This connector provides interfaces like PCIe and SATA to attach the Solid State Drives (SSDs) to the host machine along with additional interfaces like USB, and SMBus for debugging and supplementary features. At any point of time, the connector can only support either PCIe or SATA as the primary host interface. The connector provides a primary power supply of 3.3v, along with an optional 1.8v VIO supply for the Adapter I/O buffer circuitry operating at 1.8v sideband signaling. The connector also supplies optional signals in the form of GPIOs for fine grained power management. Reviewed-by: Frank Li Signed-off-by: Manivannan Sadhasivam --- .../bindings/connector/pcie-m2-m-connector.yaml | 133 +++++++++++++++++= ++++ 1 file changed, 133 insertions(+) diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-m-connecto= r.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-m-connector.ya= ml new file mode 100644 index 000000000000..e912ee6f6a59 --- /dev/null +++ b/Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/connector/pcie-m2-m-connector.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe M.2 Mechanical Key M Connector + +maintainers: + - Manivannan Sadhasivam + +description: + A PCIe M.2 M connector node represents a physical PCIe M.2 Mechanical Ke= y M + connector. The Mechanical Key M connectors are used to connect SSDs to t= he + host system over PCIe/SATA interfaces. These connectors also offer optio= nal + interfaces like USB, SMBus. + +properties: + compatible: + const: pcie-m2-m-connector + + vpcie3v3-supply: + description: A phandle to the regulator for 3.3v supply. + + vpcie1v8-supply: + description: A phandle to the regulator for VIO 1.8v supply. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: OF graph bindings modeling the interfaces exposed on the + connector. Since a single connector can have multiple interfaces, ev= ery + interface has an assigned OF graph port number as described below. + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Host interfaces of the connector + + properties: + endpoint@0: + $ref: /schemas/graph.yaml#/properties/endpoint + description: PCIe interface + + endpoint@1: + $ref: /schemas/graph.yaml#/properties/endpoint + description: SATA interface + + anyOf: + - required: + - endpoint@0 + - required: + - endpoint@1 + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: USB 2.0 interface + + i2c-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: SMBus interface + + required: + - port@0 + + clocks: + description: 32.768 KHz Suspend Clock (SUSCLK) input from the host sys= tem to + the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.= 1 for + more details. + maxItems: 1 + + pedet-gpios: + description: GPIO input to PEDET signal. This signal is used by the ho= st + systems to determine the communication protocol that the M.2 card us= es; + SATA signaling (low) or PCIe signaling (high). Refer, PCI Express M.2 + Specification r4.0, sec 3.3.4.2 for more details. + maxItems: 1 + + viocfg-gpios: + description: GPIO output to IO voltage configuration (VIO_CFG) signal.= This + signal is used by the M.2 card to indicate to the host system that t= he + card supports an independent IO voltage domain for the sideband sign= als. + Refer, PCI Express M.2 Specification r4.0, sec 3.1.15.1 for more det= ails. + maxItems: 1 + + pwrdis-gpios: + description: GPIO input to Power Disable (PWRDIS) signal. This signal = is + used by the host system to disable power on the M.2 card. Refer, PCI + Express M.2 Specification r4.0, sec 3.3.5.2 for more details. + maxItems: 1 + + pln-gpios: + description: GPIO output to Power Loss Notification (PLN#) signal. This + signal is use to notify the M.2 card by the host system that the pow= er + loss event is expected to occur. Refer, PCI Express M.2 Specification + r4.0, sec 3.2.17.1 for more details. + maxItems: 1 + + plas3-gpios: + description: GPIO output to Power Loss Acknowledge (PLA_S3#) signal. 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These connectors are exposed as the Power Sequencing devices as they often support multiple interfaces like PCIe/SATA, USB/UART to the host machine and each interfaces could be driven by different client drivers at the same time. This driver handles the PCIe interface of these connectors. It first checks for the presence of the graph port in the Root Port node with the help of of_graph_is_present() API, if present, it acquires/poweres ON the corresponding pwrseq device. Once the pwrseq device is powered ON, the driver will skip parsing the Root Port/Slot resources and registers with the pwrctrl framework. Reviewed-by: Bartosz Golaszewski Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pwrctrl/Kconfig | 1 + drivers/pci/pwrctrl/slot.c | 35 ++++++++++++++++++++++++++++++----- 2 files changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pwrctrl/Kconfig b/drivers/pci/pwrctrl/Kconfig index e0f999f299bb..cd3aa15bad00 100644 --- a/drivers/pci/pwrctrl/Kconfig +++ b/drivers/pci/pwrctrl/Kconfig @@ -13,6 +13,7 @@ config PCI_PWRCTRL_PWRSEQ =20 config PCI_PWRCTRL_SLOT tristate "PCI Power Control driver for PCI slots" + select POWER_SEQUENCING select PCI_PWRCTRL help Say Y here to enable the PCI Power Control driver to control the power diff --git a/drivers/pci/pwrctrl/slot.c b/drivers/pci/pwrctrl/slot.c index 3320494b62d8..d46c2365208a 100644 --- a/drivers/pci/pwrctrl/slot.c +++ b/drivers/pci/pwrctrl/slot.c @@ -8,8 +8,10 @@ #include #include #include +#include #include #include +#include #include #include =20 @@ -17,12 +19,18 @@ struct pci_pwrctrl_slot_data { struct pci_pwrctrl ctx; struct regulator_bulk_data *supplies; int num_supplies; + struct pwrseq_desc *pwrseq; }; =20 static void devm_pci_pwrctrl_slot_power_off(void *data) { struct pci_pwrctrl_slot_data *slot =3D data; =20 + if (slot->pwrseq) { + pwrseq_power_off(slot->pwrseq); + return; + } + regulator_bulk_disable(slot->num_supplies, slot->supplies); regulator_bulk_free(slot->num_supplies, slot->supplies); } @@ -38,6 +46,20 @@ static int pci_pwrctrl_slot_probe(struct platform_device= *pdev) if (!slot) return -ENOMEM; =20 + if (of_graph_is_present(dev_of_node(dev))) { + slot->pwrseq =3D devm_pwrseq_get(dev, "pcie"); + if (IS_ERR(slot->pwrseq)) + return dev_err_probe(dev, PTR_ERR(slot->pwrseq), + "Failed to get the power sequencer\n"); + + ret =3D pwrseq_power_on(slot->pwrseq); + if (ret) + return dev_err_probe(dev, ret, + "Failed to power-on the device\n"); + + goto skip_resources; + } + ret =3D of_regulator_bulk_get_all(dev, dev_of_node(dev), &slot->supplies); if (ret < 0) { @@ -53,17 +75,20 @@ static int pci_pwrctrl_slot_probe(struct platform_devic= e *pdev) return ret; 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Sun, 28 Dec 2025 09:01:47 -0800 (PST) X-Google-Smtp-Source: AGHT+IFrFBAwpRDeK5SpGMu/WURMQFkmH/rBO1N5gl3+Rtim67wxOerSuh7rYUNCU/Yz175dCg6eEQ== X-Received: by 2002:aa7:8703:0:b0:800:902d:9fdb with SMTP id d2e1a72fcca58-800902dc39bmr17813995b3a.5.1766941307368; Sun, 28 Dec 2025 09:01:47 -0800 (PST) Received: from work.lan ([2409:4091:a0f4:6806:90aa:5191:e297:e185]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7ff7ae354easm27053925b3a.16.2025.12.28.09.01.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Dec 2025 09:01:46 -0800 (PST) From: Manivannan Sadhasivam Date: Sun, 28 Dec 2025 22:31:05 +0530 Subject: [PATCH v4 5/5] power: sequencing: Add the Power Sequencing driver for the PCIe M.2 connectors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251228-pci-m2-v4-5-5684868b0d5f@oss.qualcomm.com> References: <20251228-pci-m2-v4-0-5684868b0d5f@oss.qualcomm.com> In-Reply-To: <20251228-pci-m2-v4-0-5684868b0d5f@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Damien Le Moal , Niklas Cassel , Linus Walleij , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, linux-ide@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7625; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=YDOJ/NTVDZQEW6th5GrtjXuNNG90jTG+ctIlTugC3ps=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpUWJZMkE1gKu3pRx1PbBdCNpryzEyM3Tv+/xho V/ATsJ7h3OJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaVFiWQAKCRBVnxHm/pHO 9SJ7B/9hLXgm1uzuIo0dlmCZ0CFsbqpnwhntFVWC6f0XPx2ASivaQXJ7V5E9xZgGZ2BwY2JN72u YRvsU5yg7DxHEJ4rvBIlNf3O+kxKFq9Sw502o+nPYSsDHSHUjYOJN27eM9EskkFhlDaUWCOXANw HOHe1DEH5x9/Db4YKBmckyoYRXePABE72c2QV+R5M7VoJ7PTr3C4yYdm7I3htrLalC9QODUtMtF lYSQ8wHzTPm7DmFT6oDlwKrof2XDfTQP0bWPPavsN+CHrqNG2HgE41umUCkT2YT9gkA7t1d2myC Zy7SnGPW8M5+EY1ioyiNUufswuki5uv2VLJ/am4MubMQwEcq X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Proofpoint-GUID: L7ioOL-25A1LhQ77_Dl--hOaC_wI4kjG X-Proofpoint-ORIG-GUID: L7ioOL-25A1LhQ77_Dl--hOaC_wI4kjG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI4MDE1NiBTYWx0ZWRfX4dvbWCdnh0jE W6TPlzZ+XtAbP2JpPdyp7qZEUKy3+IgS3Tae9qIL6gf0CmxGH8a+QhoowuFekuVNp++MCSJ9CbU nNCKw1nUNDo4k8B5JzyFD6W2x1UqI3PwcOZRg7UJGHnUqw7DKVzKurE7W3qPoPR6Nw8AjPe8Xmf lPiE5s20SR3u2AqUmk+0Hr1yvwK2gYouf64S/0sCKCUwUpDsg1l4fZ+3dG24KyctNtOYRNojD0M NNfkrd6KL/dH0jWIP4cJ/wk/3RNpJfb23cle3ApiClREhU/EbvweI3AnCkFXq3nevbn/U5Rse1M cZnQGEGF0sqQ+OILxwZtUffZGp84ptvx0jjPfKexBLXSAtT0wdG3eS5MfhPUtyMhpqI3r93rq8x p6KUaMpMSdU8hgJJTVc4iPgc8aqmWPBgBJy5Dcf4MiK0u8/CSe1kZczMrdpm0I+kd5r1Jb16OiS CJU9PShcjCsiXRdgiVA== X-Authority-Analysis: v=2.4 cv=YuEChoYX c=1 sm=1 tr=0 ts=6951627d cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=7CQSdrXTAAAA:8 a=Mi8d0xCGeq3gkRWnbWsA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-28_06,2025-12-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 adultscore=0 phishscore=0 spamscore=0 clxscore=1015 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512280156 This driver is used to control the PCIe M.2 connectors of different Mechanical Keys attached to the host machines and supporting different interfaces like PCIe/SATA, USB/UART etc... Currently, this driver supports only the Mechanical Key M connectors with PCIe interface. The driver also only supports driving the mandatory 3.3v and optional 1.8v power supplies. The optional signals of the Key M connectors are not currently supported. Signed-off-by: Manivannan Sadhasivam --- MAINTAINERS | 7 ++ drivers/power/sequencing/Kconfig | 8 ++ drivers/power/sequencing/Makefile | 1 + drivers/power/sequencing/pwrseq-pcie-m2.c | 160 ++++++++++++++++++++++++++= ++++ 4 files changed, 176 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5b11839cba9d..2eb7b6d26573 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20791,6 +20791,13 @@ F: Documentation/driver-api/pwrseq.rst F: drivers/power/sequencing/ F: include/linux/pwrseq/ =20 +PCIE M.2 POWER SEQUENCING +M: Manivannan Sadhasivam +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml +F: drivers/power/sequencing/pwrseq-pcie-m2.c + POWER STATE COORDINATION INTERFACE (PSCI) M: Mark Rutland M: Lorenzo Pieralisi diff --git a/drivers/power/sequencing/Kconfig b/drivers/power/sequencing/Kc= onfig index 280f92beb5d0..f5fff84566ba 100644 --- a/drivers/power/sequencing/Kconfig +++ b/drivers/power/sequencing/Kconfig @@ -35,4 +35,12 @@ config POWER_SEQUENCING_TH1520_GPU GPU. This driver handles the complex clock and reset sequence required to power on the Imagination BXM GPU on this platform. =20 +config POWER_SEQUENCING_PCIE_M2 + tristate "PCIe M.2 connector power sequencing driver" + depends on OF || COMPILE_TEST + help + Say Y here to enable the power sequencing driver for PCIe M.2 + connectors. This driver handles the power sequencing for the M.2 + connectors exposing multiple interfaces like PCIe, SATA, UART, etc... + endif diff --git a/drivers/power/sequencing/Makefile b/drivers/power/sequencing/M= akefile index 96c1cf0a98ac..0911d4618298 100644 --- a/drivers/power/sequencing/Makefile +++ b/drivers/power/sequencing/Makefile @@ -5,3 +5,4 @@ pwrseq-core-y :=3D core.o =20 obj-$(CONFIG_POWER_SEQUENCING_QCOM_WCN) +=3D pwrseq-qcom-wcn.o obj-$(CONFIG_POWER_SEQUENCING_TH1520_GPU) +=3D pwrseq-thead-gpu.o +obj-$(CONFIG_POWER_SEQUENCING_PCIE_M2) +=3D pwrseq-pcie-m2.o diff --git a/drivers/power/sequencing/pwrseq-pcie-m2.c b/drivers/power/sequ= encing/pwrseq-pcie-m2.c new file mode 100644 index 000000000000..4835d099d967 --- /dev/null +++ b/drivers/power/sequencing/pwrseq-pcie-m2.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct pwrseq_pcie_m2_pdata { + const struct pwrseq_target_data **targets; +}; + +struct pwrseq_pcie_m2_ctx { + struct pwrseq_device *pwrseq; + struct device_node *of_node; + const struct pwrseq_pcie_m2_pdata *pdata; + struct regulator_bulk_data *regs; + size_t num_vregs; + struct notifier_block nb; +}; + +static int pwrseq_pcie_m2_m_vregs_enable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + return regulator_bulk_enable(ctx->num_vregs, ctx->regs); +} + +static int pwrseq_pcie_m2_m_vregs_disable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + return regulator_bulk_disable(ctx->num_vregs, ctx->regs); +} + +static const struct pwrseq_unit_data pwrseq_pcie_m2_vregs_unit_data =3D { + .name =3D "regulators-enable", + .enable =3D pwrseq_pcie_m2_m_vregs_enable, + .disable =3D pwrseq_pcie_m2_m_vregs_disable, +}; + +static const struct pwrseq_unit_data *pwrseq_pcie_m2_m_unit_deps[] =3D { + &pwrseq_pcie_m2_vregs_unit_data, + NULL +}; + +static const struct pwrseq_unit_data pwrseq_pcie_m2_m_pcie_unit_data =3D { + .name =3D "pcie-enable", + .deps =3D pwrseq_pcie_m2_m_unit_deps, +}; + +static const struct pwrseq_target_data pwrseq_pcie_m2_m_pcie_target_data = =3D { + .name =3D "pcie", + .unit =3D &pwrseq_pcie_m2_m_pcie_unit_data, +}; + +static const struct pwrseq_target_data *pwrseq_pcie_m2_m_targets[] =3D { + &pwrseq_pcie_m2_m_pcie_target_data, + NULL +}; + +static const struct pwrseq_pcie_m2_pdata pwrseq_pcie_m2_m_of_data =3D { + .targets =3D pwrseq_pcie_m2_m_targets, +}; + +static int pwrseq_pcie_m2_match(struct pwrseq_device *pwrseq, + struct device *dev) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + struct device_node *endpoint __free(device_node) =3D NULL; + + /* + * Traverse the 'remote-endpoint' nodes and check if the remote node's + * parent matches the OF node of 'dev'. + */ + for_each_endpoint_of_node(ctx->of_node, endpoint) { + struct device_node *remote __free(device_node) =3D + of_graph_get_remote_port_parent(endpoint); + if (remote && (remote =3D=3D dev_of_node(dev))) + return PWRSEQ_MATCH_OK; + } + + return PWRSEQ_NO_MATCH; +} + +static int pwrseq_pcie_m2_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pwrseq_pcie_m2_ctx *ctx; + struct pwrseq_config config =3D {}; + int ret; + + ctx =3D devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->of_node =3D dev_of_node(dev); + ctx->pdata =3D device_get_match_data(dev); + if (!ctx->pdata) + return dev_err_probe(dev, -ENODEV, + "Failed to obtain platform data\n"); + + /* + * Currently, of_regulator_bulk_get_all() is the only regulator API that + * allows to get all supplies in the devicetree node without manually + * specifying them. + */ + ret =3D of_regulator_bulk_get_all(dev, dev_of_node(dev), &ctx->regs); + if (ret < 0) + return dev_err_probe(dev, ret, + "Failed to get all regulators\n"); + + ctx->num_vregs =3D ret; + + config.parent =3D dev; + config.owner =3D THIS_MODULE; + config.drvdata =3D ctx; + config.match =3D pwrseq_pcie_m2_match; + config.targets =3D ctx->pdata->targets; + + ctx->pwrseq =3D devm_pwrseq_device_register(dev, &config); + if (IS_ERR(ctx->pwrseq)) { + regulator_bulk_free(ctx->num_vregs, ctx->regs); + return dev_err_probe(dev, PTR_ERR(ctx->pwrseq), + "Failed to register the power sequencer\n"); + } + + return 0; +} + +static const struct of_device_id pwrseq_pcie_m2_of_match[] =3D { + { + .compatible =3D "pcie-m2-m-connector", + .data =3D &pwrseq_pcie_m2_m_of_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, pwrseq_pcie_m2_of_match); + +static struct platform_driver pwrseq_pcie_m2_driver =3D { + .driver =3D { + .name =3D "pwrseq-pcie-m2", + .of_match_table =3D pwrseq_pcie_m2_of_match, + }, + .probe =3D pwrseq_pcie_m2_probe, +}; +module_platform_driver(pwrseq_pcie_m2_driver); + +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_DESCRIPTION("Power Sequencing driver for PCIe M.2 connector"); +MODULE_LICENSE("GPL"); --=20 2.48.1