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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-59a185d5f07sm7840348e87.12.2025.12.27.20.02.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Dec 2025 20:02:43 -0800 (PST) From: Dmitry Baryshkov Date: Sun, 28 Dec 2025 06:02:28 +0200 Subject: [PATCH v4 2/3] drm/msm/dpu: fix CMD panels on DPU 1.x - 3.x Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251228-mdp5-drop-dpu3-v4-2-7497c3d39179@oss.qualcomm.com> References: <20251228-mdp5-drop-dpu3-v4-0-7497c3d39179@oss.qualcomm.com> In-Reply-To: <20251228-mdp5-drop-dpu3-v4-0-7497c3d39179@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Alexey Minnekhanov , David Airlie , Simona Vetter , Alexey Minnekhanov Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1598; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=RENHaPNgcH0iuo7H+XDIB0LIYFTLt0BPC5NR3Q0GN40=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpUKvcWCP4K0Kq1NCdfrPs1+uJvqSIxbD6sfe9S 4aIlu4qH+mJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaVCr3AAKCRCLPIo+Aiko 1VLMCACzQfW5MgfWUmueEI7oznLTNbRiASK3WTJL6aQimnQbyp25lS03Vjkm/P0XLoHhy7frcrx yKcPahIZZ5VHs/yhMWXJyelO5BsJLflT/qJcZcqewX6t4ZGcM4jNkxUcQbckqX3bCu5PZe1x2Lm riumUoawXMBevLJfxa1d/9YJUzbhBMdYu50tZTXcrBkiurZfkPGVQdoA9193AAAEdMsKoinKivV U0nNIFf9wWnW9V2TDGIjXFvZLbDl+uMcQ2XBlhPe56iE3RjkCUYukvv69Ndh8aPU91sgBJklp4t 6SOS8wMbys2y4G2ihLOpW65qn9ndulV7bBxEg3UQblTM8fN3 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: YENH0W4KbfWa6xM-po0W6YynOiVyF_KI X-Proofpoint-ORIG-GUID: YENH0W4KbfWa6xM-po0W6YynOiVyF_KI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI4MDAzNSBTYWx0ZWRfX9eegXKqbvJMv 3Ho8DUVczHKav0f2yDlv3cbSGenD6PIPM6NWt4onFmL6Xb5ZJagcvlzB17gntjjOupDA2/0UgvC lU6dTVtpnMVZx+uZRp5QU11Y/BPZJfMcjePs5AbgeQN6KGeQurza47dcpmhwhgJE+8xk6uwEfbB kh3vPNsY2HHR9RG3a8cHrW2YXjvsfONG/AcEVSI65u5548ZVQZedcREG4p8TE0Duz9zKVOMAqMr 0ogR1dG/VB3vpRuMaf7fJkO6LyGlW7WWggAabLN7faSmH/sDQwX2iQTj8idZqPj5gFjwidsDOEa tSVc1QQ9nKe168SqGWsV/lBDas6rnzeY5ahrmcQdvfsi/zvgnWcold7wwGM2bll7/SJ2mn+lzvU prfkj96huXnGhrDooKF2O+reOUGbyZmiM0urLry6jd0f2pEww9KDGwn6bPqrri9XVT64VBLBsEv 5Y56N1l7y9fcJa9hgbg== X-Authority-Analysis: v=2.4 cv=DptbOW/+ c=1 sm=1 tr=0 ts=6950abe6 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=Gbw9aFdXAAAA:8 a=EUspDBNiAAAA:8 a=CRoN-q7HyvHBVqPpVUgA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 a=9vIz8raoGPyDa4jBFAYH:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-28_02,2025-12-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 clxscore=1015 spamscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512280035 DPU units before 4.x don't have a separate CTL_START IRQ to mark the begin of the data transfer. In such a case, wait for the frame transfer to complete rather than trying to wait for the CTL_START interrupt (and obviously hitting the timeout). Fixes: 050770cbbd26 ("drm/msm/dpu: Fix timeout issues on command mode panel= s") Reported-by: Alexey Minnekhanov Closes: https://lore.kernel.org/r/8e1d33ff-d902-4ae9-9162-e00d17a5e6d1@post= marketos.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers= /gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 0ec6d67c7c70..93db1484f606 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -681,10 +681,11 @@ static int dpu_encoder_phys_cmd_wait_for_commit_done( if (!dpu_encoder_phys_cmd_is_master(phys_enc)) return 0; =20 - if (phys_enc->hw_ctl->ops.is_started(phys_enc->hw_ctl)) - return dpu_encoder_phys_cmd_wait_for_tx_complete(phys_enc); + if (phys_enc->irq[INTR_IDX_CTL_START] && + !phys_enc->hw_ctl->ops.is_started(phys_enc->hw_ctl)) + return _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc); =20 - return _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc); + return dpu_encoder_phys_cmd_wait_for_tx_complete(phys_enc); } =20 static void dpu_encoder_phys_cmd_handle_post_kickoff( --=20 2.47.3