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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-59a185d5d37sm7883586e87.7.2025.12.27.19.57.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Dec 2025 19:57:18 -0800 (PST) From: Dmitry Baryshkov Date: Sun, 28 Dec 2025 05:57:11 +0200 Subject: [PATCH v5 1/2] drm/msm/dpu: Set vsync source irrespective of mdp top support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251228-intf-fix-wd-v5-1-f6fce628e6f2@oss.qualcomm.com> References: <20251228-intf-fix-wd-v5-0-f6fce628e6f2@oss.qualcomm.com> In-Reply-To: <20251228-intf-fix-wd-v5-0-f6fce628e6f2@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Teguh Sobirin Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2331; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=s/p//pRO52a+gehzMR/sFVop1oTXxVfxhzjK9LP7fJQ=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpUKqaQcCnxzpAERYuI1BkP4lP7s4Y8SjZQWi9c iJnaxelohCJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaVCqmgAKCRCLPIo+Aiko 1TXZB/0eNQwsLafwu3hdu9ZMr78lj7pdHE9t8stem2p/yTVUxVfIVEuM52t9jHqqgVRViVJ5MwU gqO/ovI+BWvkHZH6NUPsGLz0cNqRTMEZKwh0qy7umCa1NAkWUGq+k8tHHxOtyXWF1CP/2C5vGT7 NFlTKK3Ffv7KRBLSFkto20diOUTY2IGLaR5iATRcmkreFGfUui/QON1Ua5bwqnXMT4A7mlVq/Gn q/zysNMTd+1qlK7bbl9kJtMXVyZ73cxVppHi/jvfosWIyDlUD4VUMnahBxJOjWW3wK93044vhSB j+a4lwzvp+m26J3mNsx1vSeArw/QjlXcaEDN5bWeuyMT9Die X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI4MDAzMyBTYWx0ZWRfXzMSiaMBbQkDS c0DrCQEOlKDrb0GaEd9SbP/en55f28ShtqPKodT2cuoCZEOCy8ZLuxCs9bVizbQ06+Y+e3iO0gd nrc1ihCZcHpjdaOKtTOneFAsKMm/B3rabgk81Ful1uzLSlaxw/yv+cxuhq00BksyeNplylNGjAd NkfVfj8HPEnL7F7FRAZbyeiiDRaMVGPuJASLET51vIzj7AcgjMnraNBgQwi2rVy5GqMjjh8Kbe6 DjixJjdGUvnSmeTncgc/jZzuO9+I5qqJ/JSFucKUr+zIr54/qPOt8FLuFriBiqXW44XTCoY6zid ubgz1v/avkS0c2dXQCpUqHjOO4zNaudADwtfy4zqSHqKrZ/UdMpDh/v/jO8uEFHvHJoyXUA4Xtq MEJb8Qu3vqo0gTNQa49O30j+c2DnvwqaTdDPH4R7DLdsEYsPrRFDNDl1NR4YfC8SRUlatxuucVG v38nGDd7r8y3HE3dY1w== X-Authority-Analysis: v=2.4 cv=UMDQ3Sfy c=1 sm=1 tr=0 ts=6950aaa1 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=tVI0ZWmoAAAA:8 a=EUspDBNiAAAA:8 a=JyrEbUn3yN3s6GbRLFEA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 a=-BPWgnxRz2uhmvdm1NTO:22 X-Proofpoint-ORIG-GUID: HH42BuPzscdyV3D2DACDhKXXQmWIQ-Q7 X-Proofpoint-GUID: HH42BuPzscdyV3D2DACDhKXXQmWIQ-Q7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-28_01,2025-12-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 phishscore=0 adultscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512280033 From: Teguh Sobirin Since DPU 5.x the vsync source TE setup is split between MDP TOP and INTF blocks. Currently all code to setup vsync_source is only executed if MDP TOP implements the setup_vsync_source() callback. However on DPU >=3D 8.x this callback is not implemented, making DPU driver skip all vsync setup. Move the INTF part out of this condition, letting DPU driver to setup TE vsync selection on all new DPU devices. Signed-off-by: Teguh Sobirin Fixes: 2f69e5458447 ("drm/msm/dpu: skip watchdog timer programming through = TOP on >=3D SM8450") [DB: restored top->ops.setup_vsync_source call] Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index d1cfe81a3373..3921c15aee98 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -774,6 +774,8 @@ static void _dpu_encoder_update_vsync_source(struct dpu= _encoder_virt *dpu_enc, return; } =20 + vsync_cfg.vsync_source =3D disp_info->vsync_source; + if (hw_mdptop->ops.setup_vsync_source) { for (i =3D 0; i < dpu_enc->num_phys_encs; i++) vsync_cfg.ppnumber[i] =3D dpu_enc->hw_pp[i]->idx; @@ -781,17 +783,15 @@ static void _dpu_encoder_update_vsync_source(struct d= pu_encoder_virt *dpu_enc, vsync_cfg.pp_count =3D dpu_enc->num_phys_encs; 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Support programming the timer in the INTF block. Fixes tag points to the commit which removed register access to thos registers on DPU 8.x+ (and which also should have added proper support for WD timer on those devices). Fixes: 43e3293fc614 ("drm/msm/dpu: add support for MDP_TOP blackhole") Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 48 +++++++++++++++++++++++++= ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 7 ----- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 7 +++++ 5 files changed, 56 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 3921c15aee98..058a7c8727f7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -775,13 +775,13 @@ static void _dpu_encoder_update_vsync_source(struct d= pu_encoder_virt *dpu_enc, } =20 vsync_cfg.vsync_source =3D disp_info->vsync_source; + vsync_cfg.frame_rate =3D drm_mode_vrefresh(&dpu_enc->base.crtc->state->ad= justed_mode); =20 if (hw_mdptop->ops.setup_vsync_source) { for (i =3D 0; i < dpu_enc->num_phys_encs; i++) vsync_cfg.ppnumber[i] =3D dpu_enc->hw_pp[i]->idx; =20 vsync_cfg.pp_count =3D dpu_enc->num_phys_encs; - vsync_cfg.frame_rate =3D drm_mode_vrefresh(&dpu_enc->base.crtc->state->a= djusted_mode); =20 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); } @@ -791,7 +791,7 @@ static void _dpu_encoder_update_vsync_source(struct dpu= _encoder_virt *dpu_enc, =20 if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel) phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf, - vsync_cfg.vsync_source); + &vsync_cfg); } } =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_intf.c index a80ac82a9625..7967d9bd2f44 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -67,6 +67,10 @@ #define INTF_MISR_CTRL 0x180 #define INTF_MISR_SIGNATURE 0x184 =20 +#define INTF_WD_TIMER_0_CTL 0x230 +#define INTF_WD_TIMER_0_CTL2 0x234 +#define INTF_WD_TIMER_0_LOAD_VALUE 0x238 + #define INTF_MUX 0x25C #define INTF_STATUS 0x26C #define INTF_AVR_CONTROL 0x270 @@ -475,7 +479,7 @@ static int dpu_hw_intf_get_vsync_info(struct dpu_hw_int= f *intf, } =20 static void dpu_hw_intf_vsync_sel(struct dpu_hw_intf *intf, - enum dpu_vsync_source vsync_source) + struct dpu_vsync_source_cfg *cfg) { struct dpu_hw_blk_reg_map *c; =20 @@ -484,7 +488,42 @@ static void dpu_hw_intf_vsync_sel(struct dpu_hw_intf *= intf, =20 c =3D &intf->hw; =20 - DPU_REG_WRITE(c, INTF_TEAR_MDP_VSYNC_SEL, (vsync_source & 0xf)); + DPU_REG_WRITE(c, INTF_TEAR_MDP_VSYNC_SEL, (cfg->vsync_source & 0xf)); +} + +static void dpu_hw_intf_vsync_sel_v8(struct dpu_hw_intf *intf, + struct dpu_vsync_source_cfg *cfg) +{ + struct dpu_hw_blk_reg_map *c; + + if (!intf) + return; + + c =3D &intf->hw; + + if (cfg->vsync_source >=3D DPU_VSYNC_SOURCE_WD_TIMER_4 && + cfg->vsync_source <=3D DPU_VSYNC_SOURCE_WD_TIMER_1) { + pr_warn_once("DPU 8.x supports only GPIOs and timer0 as TE sources\n"); + return; + } + + if (cfg->vsync_source =3D=3D DPU_VSYNC_SOURCE_WD_TIMER_0) { + u32 reg; + + DPU_REG_WRITE(c, INTF_WD_TIMER_0_LOAD_VALUE, + CALCULATE_WD_LOAD_VALUE(cfg->frame_rate)); + + DPU_REG_WRITE(c, INTF_WD_TIMER_0_CTL, BIT(0)); /* clear timer */ + reg =3D DPU_REG_READ(c, INTF_WD_TIMER_0_CTL2); + reg |=3D BIT(8); /* enable heartbeat timer */ + reg |=3D BIT(0); /* enable WD timer */ + DPU_REG_WRITE(c, INTF_WD_TIMER_0_CTL2, reg); + + /* make sure that timers are enabled/disabled for vsync state */ + wmb(); + } + + dpu_hw_intf_vsync_sel(intf, cfg); } =20 static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf, @@ -598,7 +637,10 @@ struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device= *dev, c->ops.enable_tearcheck =3D dpu_hw_intf_enable_te; c->ops.disable_tearcheck =3D dpu_hw_intf_disable_te; c->ops.connect_external_te =3D dpu_hw_intf_connect_external_te; - c->ops.vsync_sel =3D dpu_hw_intf_vsync_sel; + if (mdss_rev->core_major_ver >=3D 8) + c->ops.vsync_sel =3D dpu_hw_intf_vsync_sel_v8; + else + c->ops.vsync_sel =3D dpu_hw_intf_vsync_sel; c->ops.disable_autorefresh =3D dpu_hw_intf_disable_autorefresh; } =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_intf.h index f31067a9aaf1..e84ab849d71a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -12,6 +12,7 @@ #include "dpu_hw_util.h" =20 struct dpu_hw_intf; +struct dpu_vsync_source_cfg; =20 /* intf timing settings */ struct dpu_hw_intf_timing_params { @@ -107,7 +108,7 @@ struct dpu_hw_intf_ops { =20 int (*connect_external_te)(struct dpu_hw_intf *intf, bool enable_external= _te); =20 - void (*vsync_sel)(struct dpu_hw_intf *intf, enum dpu_vsync_source vsync_s= ource); + void (*vsync_sel)(struct dpu_hw_intf *intf, struct dpu_vsync_source_cfg *= cfg); =20 /** * Disable autorefresh if enabled diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_top.c index 96dc10589bee..1ebd75d4f9be 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -22,13 +22,6 @@ #define TRAFFIC_SHAPER_WR_CLIENT(num) (0x060 + (num * 4)) #define TRAFFIC_SHAPER_FIXPOINT_FACTOR 4 =20 -#define MDP_TICK_COUNT 16 -#define XO_CLK_RATE 19200 -#define MS_TICKS_IN_SEC 1000 - -#define CALCULATE_WD_LOAD_VALUE(fps) \ - ((uint32_t)((MS_TICKS_IN_SEC * XO_CLK_RATE)/(MDP_TICK_COUNT * fps))) - static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp, struct split_pipe_cfg *cfg) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_util.h index 67b08e99335d..6fe65bc3bff4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h @@ -21,6 +21,13 @@ =20 #define TO_S15D16(_x_)((_x_) << 7) =20 +#define MDP_TICK_COUNT 16 +#define XO_CLK_RATE 19200 +#define MS_TICKS_IN_SEC 1000 + +#define CALCULATE_WD_LOAD_VALUE(fps) \ + ((uint32_t)((MS_TICKS_IN_SEC * XO_CLK_RATE)/(MDP_TICK_COUNT * fps))) + extern const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L; extern const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L; extern const struct dpu_csc_cfg dpu_csc10_rgb2yuv_601l; --=20 2.47.3