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Sat, 27 Dec 2025 09:57:44 -0800 (PST) Received: from localhost.localdomain ([2a02:a31b:20c3:6680:3d12:d2ea:4ee0:347a]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8037de1421sm2793889166b.41.2025.12.27.09.57.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Dec 2025 09:57:43 -0800 (PST) From: Dmytro Maluka To: David Woodhouse , Lu Baolu , iommu@lists.linux.dev Cc: Joerg Roedel , Will Deacon , Robin Murphy , linux-kernel@vger.kernel.org, "Vineeth Pillai (Google)" , Aashish Sharma , Grzegorz Jaszczyk , Chuanxiao Dong , Kevin Tian , Dmytro Maluka Subject: [PATCH v2 4/5] iommu/vt-d: Use smp_wmb() before setting context/pasid present bit Date: Sat, 27 Dec 2025 18:57:27 +0100 Message-ID: <20251227175728.4358-5-dmaluka@chromium.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251227175728.4358-1-dmaluka@chromium.org> References: <20251227175728.4358-1-dmaluka@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the previous patch we already ensure that the present bit in context or PASID entries is not set earlier than setting/clearing other needed bits (assuming that setting/clearing any bits in them is always done via WRITE_ONCE, which is enough to ensure ordering between them on x86). However, it also doesn't hurt to add an explicit smp_wmb() barrier (which on x86 is merely a compiler barrier) before setting the present bit, as an extra safety measure in case we still forget to use WRITE_ONCE when updating any other bits in context/PASID entries in the future, plus for documentation purposes. Suggested-by: Lu Baolu Signed-off-by: Dmytro Maluka --- drivers/iommu/intel/iommu.h | 10 ++++++++++ drivers/iommu/intel/pasid.h | 6 ++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 5bc69ffc7c8e..75576885314b 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -909,6 +909,16 @@ static inline void entry_set_bits(u64 *ptr, u64 mask, = u64 bits) =20 static inline void context_set_present(struct context_entry *context) { + /* + * Make sure to not set the present bit earlier than updating other + * bits. + * + * This barrier may be redundant, but only as long as any context + * entry modifications use WRITE_ONCE(), which is enough to ensure + * ordering between them on x86 hardware. + */ + smp_wmb(); + entry_set_bits(&context->lo, 1ULL << 0, 1ULL); } =20 diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h index f8fc73676192..0d50959a0495 100644 --- a/drivers/iommu/intel/pasid.h +++ b/drivers/iommu/intel/pasid.h @@ -228,6 +228,12 @@ static inline void pasid_set_wpe(struct pasid_entry *p= e) */ static inline void pasid_set_present(struct pasid_entry *pe) { + /* + * Make sure to not set the present bit earlier than updating other + * bits. See also the comment in context_set_present(). + */ + smp_wmb(); + entry_set_bits(&pe->val[0], 1 << 0, 1); } =20 --=20 2.47.3