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charset="utf-8" When setting PASID entry bits via pasid_set_*() helpers, apply the specified mask to the specified bits to be set, as a safety measure in case the caller accidentally passes a value that exceeds the specified mask. Also warn if that happens. Suggested-by: Lu Baolu Signed-off-by: Dmytro Maluka --- drivers/iommu/intel/pasid.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h index b4c85242dc79..39acd3efa3ab 100644 --- a/drivers/iommu/intel/pasid.h +++ b/drivers/iommu/intel/pasid.h @@ -113,8 +113,10 @@ static inline void pasid_set_bits(u64 *ptr, u64 mask, = u64 bits) { u64 old; =20 + WARN_ON_ONCE(bits & ~mask); + old =3D READ_ONCE(*ptr); - WRITE_ONCE(*ptr, (old & ~mask) | bits); + WRITE_ONCE(*ptr, (old & ~mask) | (bits & mask)); } =20 static inline u64 pasid_get_bits(u64 *ptr) --=20 2.47.3 From nobody Sun Feb 8 05:20:09 2026 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 987693191C2 for ; Sat, 27 Dec 2025 17:57:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" To prepare for reusing the pasid_set_bits() for context entries as well, rename it to entry_set_bits() and move its definition to iommu.h. Signed-off-by: Dmytro Maluka --- drivers/iommu/intel/iommu.h | 9 ++++++++ drivers/iommu/intel/pasid.h | 42 +++++++++++++++---------------------- 2 files changed, 26 insertions(+), 25 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 25c5e22096d4..2fab7ff4b932 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -897,6 +897,15 @@ static inline int pfn_level_offset(u64 pfn, int level) return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK; } =20 +static inline void entry_set_bits(u64 *ptr, u64 mask, u64 bits) +{ + u64 old; + + WARN_ON_ONCE(bits & ~mask); + + old =3D READ_ONCE(*ptr); + WRITE_ONCE(*ptr, (old & ~mask) | (bits & mask)); +} =20 static inline void context_set_present(struct context_entry *context) { diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h index 39acd3efa3ab..f8fc73676192 100644 --- a/drivers/iommu/intel/pasid.h +++ b/drivers/iommu/intel/pasid.h @@ -10,6 +10,8 @@ #ifndef __INTEL_PASID_H #define __INTEL_PASID_H =20 +#include "iommu.h" + #define PASID_MAX 0x100000 #define PASID_PTE_MASK 0x3F #define PASID_PTE_PRESENT 1 @@ -109,16 +111,6 @@ static inline void pasid_clear_entry_with_fpd(struct p= asid_entry *pe) WRITE_ONCE(pe->val[7], 0); } =20 -static inline void pasid_set_bits(u64 *ptr, u64 mask, u64 bits) -{ - u64 old; - - WARN_ON_ONCE(bits & ~mask); - - old =3D READ_ONCE(*ptr); - WRITE_ONCE(*ptr, (old & ~mask) | (bits & mask)); -} - static inline u64 pasid_get_bits(u64 *ptr) { return READ_ONCE(*ptr); @@ -131,7 +123,7 @@ static inline u64 pasid_get_bits(u64 *ptr) static inline void pasid_set_domain_id(struct pasid_entry *pe, u64 value) { - pasid_set_bits(&pe->val[1], GENMASK_ULL(15, 0), value); + entry_set_bits(&pe->val[1], GENMASK_ULL(15, 0), value); } =20 /* @@ -150,7 +142,7 @@ pasid_get_domain_id(struct pasid_entry *pe) static inline void pasid_set_slptr(struct pasid_entry *pe, u64 value) { - pasid_set_bits(&pe->val[0], VTD_PAGE_MASK, value); + entry_set_bits(&pe->val[0], VTD_PAGE_MASK, value); } =20 /* @@ -160,7 +152,7 @@ pasid_set_slptr(struct pasid_entry *pe, u64 value) static inline void pasid_set_address_width(struct pasid_entry *pe, u64 value) { - pasid_set_bits(&pe->val[0], GENMASK_ULL(4, 2), value << 2); + entry_set_bits(&pe->val[0], GENMASK_ULL(4, 2), value << 2); } =20 /* @@ -170,7 +162,7 @@ pasid_set_address_width(struct pasid_entry *pe, u64 val= ue) static inline void pasid_set_translation_type(struct pasid_entry *pe, u64 value) { - pasid_set_bits(&pe->val[0], GENMASK_ULL(8, 6), value << 6); + entry_set_bits(&pe->val[0], GENMASK_ULL(8, 6), value << 6); } =20 /* @@ -179,7 +171,7 @@ pasid_set_translation_type(struct pasid_entry *pe, u64 = value) */ static inline void pasid_set_fault_enable(struct pasid_entry *pe) { - pasid_set_bits(&pe->val[0], 1 << 1, 0); + entry_set_bits(&pe->val[0], 1 << 1, 0); } =20 /* @@ -189,7 +181,7 @@ static inline void pasid_set_fault_enable(struct pasid_= entry *pe) */ static inline void pasid_set_ssade(struct pasid_entry *pe) { - pasid_set_bits(&pe->val[0], 1 << 9, 1 << 9); + entry_set_bits(&pe->val[0], 1 << 9, 1 << 9); } =20 /* @@ -199,7 +191,7 @@ static inline void pasid_set_ssade(struct pasid_entry *= pe) */ static inline void pasid_clear_ssade(struct pasid_entry *pe) { - pasid_set_bits(&pe->val[0], 1 << 9, 0); + entry_set_bits(&pe->val[0], 1 << 9, 0); } =20 /* @@ -218,7 +210,7 @@ static inline bool pasid_get_ssade(struct pasid_entry *= pe) */ static inline void pasid_set_sre(struct pasid_entry *pe) { - pasid_set_bits(&pe->val[2], 1 << 0, 1); + entry_set_bits(&pe->val[2], 1 << 0, 1); } =20 /* @@ -227,7 +219,7 @@ static inline void pasid_set_sre(struct pasid_entry *pe) */ static inline void pasid_set_wpe(struct pasid_entry *pe) { - pasid_set_bits(&pe->val[2], 1 << 4, 1 << 4); + entry_set_bits(&pe->val[2], 1 << 4, 1 << 4); } =20 /* @@ -236,7 +228,7 @@ static inline void pasid_set_wpe(struct pasid_entry *pe) */ static inline void pasid_set_present(struct pasid_entry *pe) { - pasid_set_bits(&pe->val[0], 1 << 0, 1); + entry_set_bits(&pe->val[0], 1 << 0, 1); } =20 /* @@ -245,7 +237,7 @@ static inline void pasid_set_present(struct pasid_entry= *pe) */ static inline void pasid_set_page_snoop(struct pasid_entry *pe, bool value) { - pasid_set_bits(&pe->val[1], 1 << 23, value << 23); + entry_set_bits(&pe->val[1], 1 << 23, value << 23); } =20 /* @@ -255,7 +247,7 @@ static inline void pasid_set_page_snoop(struct pasid_en= try *pe, bool value) static inline void pasid_set_pgsnp(struct pasid_entry *pe) { - pasid_set_bits(&pe->val[1], 1ULL << 24, 1ULL << 24); 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charset="utf-8" We do take care to not set the present bit in a context table entry via context_set_present() earlier than setting up all other bits in it. However, we don't do anything to actually ensure this order, i.e. to prevent the compiler from reordering it. And since context entries may be updated at runtime when translation is already enabled, this is a potential source of bugs or security issues. To easily fix this, convert the context_set_*() and context_clear_*() helpers to use entry_set_bits() which uses READ_ONCE/WRITE_ONCE, to ensure that the ordering between updates of individual bits in context entries matches the order of calling those helpers, just like we already do that for PASID table entries. Link: https://lore.kernel.org/all/aTG7gc7I5wExai3S@google.com/ Signed-off-by: Dmytro Maluka --- drivers/iommu/intel/iommu.h | 30 ++++++++++++++---------------- drivers/iommu/intel/pasid.c | 3 ++- 2 files changed, 16 insertions(+), 17 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 2fab7ff4b932..5bc69ffc7c8e 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -869,7 +869,7 @@ static inline bool dma_pte_superpage(struct dma_pte *pt= e) =20 static inline bool context_present(struct context_entry *context) { - return (context->lo & 1); + return READ_ONCE(context->lo) & 1; } =20 #define LEVEL_STRIDE (9) @@ -909,43 +909,41 @@ static inline void entry_set_bits(u64 *ptr, u64 mask,= u64 bits) =20 static inline void context_set_present(struct context_entry *context) { - context->lo |=3D 1; + entry_set_bits(&context->lo, 1ULL << 0, 1ULL); } =20 static inline void context_set_fault_enable(struct context_entry *context) { - context->lo &=3D (((u64)-1) << 2) | 1; + entry_set_bits(&context->lo, 1ULL << 1, 0ULL); } =20 static inline void context_set_translation_type(struct context_entry *cont= ext, unsigned long value) { - context->lo &=3D (((u64)-1) << 4) | 3; - context->lo |=3D (value & 3) << 2; + entry_set_bits(&context->lo, GENMASK_ULL(3, 2), value << 2); } =20 static inline void context_set_address_root(struct context_entry *context, unsigned long value) { - context->lo &=3D ~VTD_PAGE_MASK; - context->lo |=3D value & VTD_PAGE_MASK; + entry_set_bits(&context->lo, VTD_PAGE_MASK, value); } =20 static inline void context_set_address_width(struct context_entry *context, unsigned long value) { - context->hi |=3D value & 7; + entry_set_bits(&context->hi, GENMASK_ULL(2, 0), value); } =20 static inline void context_set_domain_id(struct context_entry *context, unsigned long value) { - context->hi |=3D (value & ((1 << 16) - 1)) << 8; + entry_set_bits(&context->hi, GENMASK_ULL(23, 8), value << 8); } =20 static inline void context_set_pasid(struct context_entry *context) { - context->lo |=3D CONTEXT_PASIDE; + entry_set_bits(&context->lo, CONTEXT_PASIDE, CONTEXT_PASIDE); } =20 static inline int context_domain_id(struct context_entry *c) @@ -955,8 +953,8 @@ static inline int context_domain_id(struct context_entr= y *c) =20 static inline void context_clear_entry(struct context_entry *context) { - context->lo =3D 0; - context->hi =3D 0; + WRITE_ONCE(context->lo, 0); + WRITE_ONCE(context->hi, 0); } =20 #ifdef CONFIG_INTEL_IOMMU @@ -989,7 +987,7 @@ clear_context_copied(struct intel_iommu *iommu, u8 bus,= u8 devfn) static inline void context_set_sm_rid2pasid(struct context_entry *context, unsigned long pasi= d) { - context->hi |=3D pasid & ((1 << 20) - 1); + entry_set_bits(&context->hi, GENMASK_ULL(19, 0), pasid); } =20 /* @@ -998,7 +996,7 @@ context_set_sm_rid2pasid(struct context_entry *context,= unsigned long pasid) */ static inline void context_set_sm_dte(struct context_entry *context) { - context->lo |=3D BIT_ULL(2); + entry_set_bits(&context->lo, BIT_ULL(2), BIT_ULL(2)); } =20 /* @@ -1007,7 +1005,7 @@ static inline void context_set_sm_dte(struct context_= entry *context) */ static inline void context_set_sm_pre(struct context_entry *context) { - context->lo |=3D BIT_ULL(4); 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charset="utf-8" With the previous patch we already ensure that the present bit in context or PASID entries is not set earlier than setting/clearing other needed bits (assuming that setting/clearing any bits in them is always done via WRITE_ONCE, which is enough to ensure ordering between them on x86). However, it also doesn't hurt to add an explicit smp_wmb() barrier (which on x86 is merely a compiler barrier) before setting the present bit, as an extra safety measure in case we still forget to use WRITE_ONCE when updating any other bits in context/PASID entries in the future, plus for documentation purposes. Suggested-by: Lu Baolu Signed-off-by: Dmytro Maluka --- drivers/iommu/intel/iommu.h | 10 ++++++++++ drivers/iommu/intel/pasid.h | 6 ++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 5bc69ffc7c8e..75576885314b 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -909,6 +909,16 @@ static inline void entry_set_bits(u64 *ptr, u64 mask, = u64 bits) =20 static inline void context_set_present(struct context_entry *context) { + /* + * Make sure to not set the present bit earlier than updating other + * bits. + * + * This barrier may be redundant, but only as long as any context + * entry modifications use WRITE_ONCE(), which is enough to ensure + * ordering between them on x86 hardware. + */ + smp_wmb(); + entry_set_bits(&context->lo, 1ULL << 0, 1ULL); } =20 diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h index f8fc73676192..0d50959a0495 100644 --- a/drivers/iommu/intel/pasid.h +++ b/drivers/iommu/intel/pasid.h @@ -228,6 +228,12 @@ static inline void pasid_set_wpe(struct pasid_entry *p= e) */ static inline void pasid_set_present(struct pasid_entry *pe) { + /* + * Make sure to not set the present bit earlier than updating other + * bits. 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Sat, 27 Dec 2025 09:57:45 -0800 (PST) From: Dmytro Maluka To: David Woodhouse , Lu Baolu , iommu@lists.linux.dev Cc: Joerg Roedel , Will Deacon , Robin Murphy , linux-kernel@vger.kernel.org, "Vineeth Pillai (Google)" , Aashish Sharma , Grzegorz Jaszczyk , Chuanxiao Dong , Kevin Tian , Dmytro Maluka Subject: [PATCH v2 5/5] iommu/vt-d: Use WRITE_ONCE for setting root table entries Date: Sat, 27 Dec 2025 18:57:28 +0100 Message-ID: <20251227175728.4358-6-dmaluka@chromium.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251227175728.4358-1-dmaluka@chromium.org> References: <20251227175728.4358-1-dmaluka@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Like context table entries (addressed in the previous patches), root table entries may also be set up at runtime, when DMA translation is already enabled (e.g. due to a device hotplug). So to stay on the safe side, use WRITE_ONCE when setting a root table entry, to prevent the compiler from doing store tearing which could result in setting the present bit earlier than the context table address bits. Signed-off-by: Dmytro Maluka --- drivers/iommu/intel/iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 134302fbcd92..fe4d0d210a5f 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -374,7 +374,7 @@ struct context_entry *iommu_context_addr(struct intel_i= ommu *iommu, u8 bus, =20 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE); phy_addr =3D virt_to_phys((void *)context); - *entry =3D phy_addr | 1; + WRITE_ONCE(*entry, phy_addr | 1); __iommu_flush_cache(iommu, entry, sizeof(*entry)); } return &context[devfn]; --=20 2.47.3