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([87.200.95.144]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4324ea1b1bdsm44182107f8f.8.2025.12.26.03.31.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Dec 2025 03:31:56 -0800 (PST) From: Christian Hewitt To: Detlev Casanova , =?UTF-8?q?Olivier=20Cr=C3=AAte?= , Ezequiel Garcia , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Diederik de Haas , Dmitry Osipenko , Thomas Gleixner , Dragan Simic , Chukun Pan , linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Diederik de Haas , Piotr Oniszczuk Subject: [PATCH v2 3/3] arm64: dts: rockchip: Add the vdpu346 Video Decoders on RK356X Date: Fri, 26 Dec 2025 11:31:40 +0000 Message-Id: <20251226113140.573759-4-christianshewitt@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251226113140.573759-1-christianshewitt@gmail.com> References: <20251226113140.573759-1-christianshewitt@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the vdpu346 Video Decoders to the rk356x-base devicetree to enable support on RK3566 and RK3568 boards. Also add the needed sram and vdec_mmu nodes. Suggested-by: Diederik de Haas Suggested-by: Piotr Oniszczuk Signed-off-by: Christian Hewitt --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk356x-base.dtsi index 8893b7b6cc9f..b37eea56c221 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -383,6 +383,19 @@ usb2phy1_grf: syscon@fdca8000 { reg =3D <0x0 0xfdca8000 0x0 0x8000>; }; =20 + sram@fdcc0000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0xfdcc0000 0x0 0xb000>; + ranges =3D <0x0 0x0 0xfdcc0000 0xb000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + vdec_sram: rkvdec-sram@0 { + reg =3D <0x0 0xb000>; + pool; + }; + }; + pmucru: clock-controller@fdd00000 { compatible =3D "rockchip,rk3568-pmucru"; reg =3D <0x0 0xfdd00000 0x0 0x1000>; @@ -619,6 +632,42 @@ vepu_mmu: iommu@fdee0800 { #iommu-cells =3D <0>; }; =20 + vdec: video-codec@fdf80100 { + compatible =3D "rockchip,rk3568-vdec"; + reg =3D <0x0 0xfdf80200 0x0 0x500>, + <0x0 0xfdf80100 0x0 0x100>, + <0x0 0xfdf80700 0x0 0x100>; + reg-names =3D "function", "link", "cache"; + interrupts =3D ; + clocks =3D <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, + <&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_CORE>, + <&cru CLK_RKVDEC_HEVC_CA>; + clock-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks =3D <&cru ACLK_RKVDEC>, + <&cru CLK_RKVDEC_CORE>, + <&cru CLK_RKVDEC_CA>, + <&cru CLK_RKVDEC_HEVC_CA>; + assigned-clock-rates =3D <297000000>, <297000000>, + <297000000>, <600000000>; + iommus =3D <&vdec_mmu>; + power-domains =3D <&power RK3568_PD_RKVDEC>; + resets =3D <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>, + <&cru SRST_RKVDEC_CA>, <&cru SRST_RKVDEC_CORE>, + <&cru SRST_RKVDEC_HEVC_CA>; + reset-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram =3D <&vdec_sram>; + }; + + vdec_mmu: iommu@fdf80800 { + compatible =3D "rockchip,rk3568-iommu"; + reg =3D <0x0 0xfdf80800 0x0 0x40>, <0x0 0xfdf80840 0x0 0x40>; + interrupts =3D ; + clocks =3D <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; + clock-names =3D "aclk", "iface"; + power-domains =3D <&power RK3568_PD_RKVDEC>; + #iommu-cells =3D <0>; + }; + vicap: video-capture@fdfe0000 { compatible =3D "rockchip,rk3568-vicap"; reg =3D <0x0 0xfdfe0000 0x0 0x200>; --=20 2.34.1