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([87.200.95.144]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4324ea1b1bdsm44182107f8f.8.2025.12.26.03.31.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Dec 2025 03:31:48 -0800 (PST) From: Christian Hewitt To: Detlev Casanova , =?UTF-8?q?Olivier=20Cr=C3=AAte?= , Ezequiel Garcia , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Diederik de Haas , Dmitry Osipenko , Thomas Gleixner , Dragan Simic , Chukun Pan , linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/3] media: dt-bindings: rockchip: Add RK3568 Video Decoder bindings Date: Fri, 26 Dec 2025 11:31:38 +0000 Message-Id: <20251226113140.573759-2-christianshewitt@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251226113140.573759-1-christianshewitt@gmail.com> References: <20251226113140.573759-1-christianshewitt@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The video decoder in RK356X (vdpu346) is described in the same way as the one in RK3588 (vdpu381). A new compatible is added as the decoder capabilities are a subset of the vdpu381 capabilities. Signed-off-by: Christian Hewitt Acked-by: Rob Herring (Arm) Tested-by: Dang Huynh --- Documentation/devicetree/bindings/media/rockchip,vdec.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/D= ocumentation/devicetree/bindings/media/rockchip,vdec.yaml index 809fda45b3bd..656ceb1f116e 100644 --- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml +++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml @@ -18,6 +18,7 @@ properties: oneOf: - const: rockchip,rk3288-vdec - const: rockchip,rk3399-vdec + - const: rockchip,rk3568-vdec - const: rockchip,rk3576-vdec - const: rockchip,rk3588-vdec - items: @@ -107,6 +108,7 @@ allOf: compatible: contains: enum: + - rockchip,rk3568-vdec - rockchip,rk3576-vdec - rockchip,rk3588-vdec then: --=20 2.34.1 From nobody Sun Feb 8 04:23:38 2026 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E137831B80A for ; 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([87.200.95.144]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4324ea1b1bdsm44182107f8f.8.2025.12.26.03.31.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Dec 2025 03:31:52 -0800 (PST) From: Christian Hewitt To: Detlev Casanova , =?UTF-8?q?Olivier=20Cr=C3=AAte?= , Ezequiel Garcia , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Diederik de Haas , Dmitry Osipenko , Thomas Gleixner , Dragan Simic , Chukun Pan , linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Nicolas Dufresne Subject: [PATCH v2 2/3] media: rkvdec: Add support for the VDPU346 variant Date: Fri, 26 Dec 2025 11:31:39 +0000 Message-Id: <20251226113140.573759-3-christianshewitt@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251226113140.573759-1-christianshewitt@gmail.com> References: <20251226113140.573759-1-christianshewitt@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" VDPU346 is similar to VDPU381 but with a single core and limited to 4K60 media. It is also limited to H264 L5.1 and omits AV1 and AVS2 capabilities. VDPU346 is used with RK3566 and RK3568. Signed-off-by: Christian Hewitt Reviewed-by: Nicolas Dufresne Tested-by: Dang Huynh --- .../media/platform/rockchip/rkvdec/rkvdec.c | 103 ++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/medi= a/platform/rockchip/rkvdec/rkvdec.c index e547057dc75f..6b39e99d8a8b 100644 --- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c @@ -236,6 +236,62 @@ static const struct rkvdec_ctrls rkvdec_hevc_ctrls =3D= { .num_ctrls =3D ARRAY_SIZE(rkvdec_hevc_ctrl_descs), }; =20 +static const struct rkvdec_ctrl_desc vdpu346_hevc_ctrl_descs[] =3D { + { + .cfg.id =3D V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, + }, + { + .cfg.id =3D V4L2_CID_STATELESS_HEVC_SPS, + .cfg.ops =3D &rkvdec_ctrl_ops, + }, + { + .cfg.id =3D V4L2_CID_STATELESS_HEVC_PPS, + }, + { + .cfg.id =3D V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, + }, + { + .cfg.id =3D V4L2_CID_STATELESS_HEVC_DECODE_MODE, + .cfg.min =3D V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, + .cfg.max =3D V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, + .cfg.def =3D V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, + }, + { + .cfg.id =3D V4L2_CID_STATELESS_HEVC_START_CODE, + .cfg.min =3D V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, + .cfg.def =3D V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, + .cfg.max =3D V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, + }, + { + .cfg.id =3D V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, + .cfg.min =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .cfg.max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + .cfg.menu_skip_mask =3D + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE), + .cfg.def =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + }, + { + .cfg.id =3D V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, + .cfg.min =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .cfg.max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, + }, + { + .cfg.id =3D V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS, + .cfg.ops =3D &rkvdec_ctrl_ops, + .cfg.dims =3D { 65 }, + }, + { + .cfg.id =3D V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS, + .cfg.ops =3D &rkvdec_ctrl_ops, + .cfg.dims =3D { 65 }, + }, +}; + +static const struct rkvdec_ctrls vdpu346_hevc_ctrls =3D { + .ctrls =3D vdpu346_hevc_ctrl_descs, + .num_ctrls =3D ARRAY_SIZE(vdpu346_hevc_ctrl_descs), +}; + static const struct rkvdec_ctrl_desc vdpu38x_hevc_ctrl_descs[] =3D { { .cfg.id =3D V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, @@ -463,6 +519,41 @@ static const struct rkvdec_coded_fmt_desc rk3288_coded= _fmts[] =3D { } }; =20 +static const struct rkvdec_coded_fmt_desc vdpu346_coded_fmts[] =3D { + { + .fourcc =3D V4L2_PIX_FMT_HEVC_SLICE, + .frmsize =3D { + .min_width =3D 64, + .max_width =3D 65472, + .step_width =3D 64, + .min_height =3D 64, + .max_height =3D 65472, + .step_height =3D 16, + }, + .ctrls =3D &vdpu346_hevc_ctrls, + .ops =3D &rkvdec_vdpu381_hevc_fmt_ops, + .num_decoded_fmts =3D ARRAY_SIZE(rkvdec_hevc_decoded_fmts), + .decoded_fmts =3D rkvdec_hevc_decoded_fmts, + .subsystem_flags =3D VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, + }, + { + .fourcc =3D V4L2_PIX_FMT_H264_SLICE, + .frmsize =3D { + .min_width =3D 64, + .max_width =3D 65520, + .step_width =3D 64, + .min_height =3D 64, + .max_height =3D 65520, + .step_height =3D 16, + }, + .ctrls =3D &rkvdec_h264_ctrls, + .ops =3D &rkvdec_vdpu381_h264_fmt_ops, + .num_decoded_fmts =3D ARRAY_SIZE(rkvdec_h264_decoded_fmts), + .decoded_fmts =3D rkvdec_h264_decoded_fmts, + .subsystem_flags =3D VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, + }, +}; + static const struct rkvdec_coded_fmt_desc vdpu381_coded_fmts[] =3D { { .fourcc =3D V4L2_PIX_FMT_HEVC_SLICE, @@ -1643,6 +1734,14 @@ static const struct rkvdec_variant_ops vdpu381_varia= nt_ops =3D { .flatten_matrices =3D transpose_and_flatten_matrices, }; =20 +static const struct rkvdec_variant vdpu346_variant =3D { + .coded_fmts =3D vdpu346_coded_fmts, + .num_coded_fmts =3D ARRAY_SIZE(vdpu346_coded_fmts), + .rcb_sizes =3D vdpu381_rcb_sizes, + .num_rcb_sizes =3D ARRAY_SIZE(vdpu381_rcb_sizes), + .ops =3D &vdpu381_variant_ops, +}; + static const struct rkvdec_variant vdpu381_variant =3D { .coded_fmts =3D vdpu381_coded_fmts, .num_coded_fmts =3D ARRAY_SIZE(vdpu381_coded_fmts), @@ -1691,6 +1790,10 @@ static const struct of_device_id of_rkvdec_match[] = =3D { .compatible =3D "rockchip,rk3399-vdec", .data =3D &rk3399_rkvdec_variant, }, + { + .compatible =3D "rockchip,rk3568-vdec", + .data =3D &vdpu346_variant, + }, { .compatible =3D "rockchip,rk3588-vdec", .data =3D &vdpu381_variant, --=20 2.34.1 From nobody Sun Feb 8 04:23:38 2026 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37360286415 for ; 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([87.200.95.144]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4324ea1b1bdsm44182107f8f.8.2025.12.26.03.31.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Dec 2025 03:31:56 -0800 (PST) From: Christian Hewitt To: Detlev Casanova , =?UTF-8?q?Olivier=20Cr=C3=AAte?= , Ezequiel Garcia , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Diederik de Haas , Dmitry Osipenko , Thomas Gleixner , Dragan Simic , Chukun Pan , linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Diederik de Haas , Piotr Oniszczuk Subject: [PATCH v2 3/3] arm64: dts: rockchip: Add the vdpu346 Video Decoders on RK356X Date: Fri, 26 Dec 2025 11:31:40 +0000 Message-Id: <20251226113140.573759-4-christianshewitt@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251226113140.573759-1-christianshewitt@gmail.com> References: <20251226113140.573759-1-christianshewitt@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the vdpu346 Video Decoders to the rk356x-base devicetree to enable support on RK3566 and RK3568 boards. Also add the needed sram and vdec_mmu nodes. Suggested-by: Diederik de Haas Suggested-by: Piotr Oniszczuk Signed-off-by: Christian Hewitt Tested-by: Dang Huynh --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk356x-base.dtsi index 8893b7b6cc9f..b37eea56c221 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -383,6 +383,19 @@ usb2phy1_grf: syscon@fdca8000 { reg =3D <0x0 0xfdca8000 0x0 0x8000>; }; =20 + sram@fdcc0000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0xfdcc0000 0x0 0xb000>; + ranges =3D <0x0 0x0 0xfdcc0000 0xb000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + vdec_sram: rkvdec-sram@0 { + reg =3D <0x0 0xb000>; + pool; + }; + }; + pmucru: clock-controller@fdd00000 { compatible =3D "rockchip,rk3568-pmucru"; reg =3D <0x0 0xfdd00000 0x0 0x1000>; @@ -619,6 +632,42 @@ vepu_mmu: iommu@fdee0800 { #iommu-cells =3D <0>; }; =20 + vdec: video-codec@fdf80100 { + compatible =3D "rockchip,rk3568-vdec"; + reg =3D <0x0 0xfdf80200 0x0 0x500>, + <0x0 0xfdf80100 0x0 0x100>, + <0x0 0xfdf80700 0x0 0x100>; + reg-names =3D "function", "link", "cache"; + interrupts =3D ; + clocks =3D <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, + <&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_CORE>, + <&cru CLK_RKVDEC_HEVC_CA>; + clock-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks =3D <&cru ACLK_RKVDEC>, + <&cru CLK_RKVDEC_CORE>, + <&cru CLK_RKVDEC_CA>, + <&cru CLK_RKVDEC_HEVC_CA>; + assigned-clock-rates =3D <297000000>, <297000000>, + <297000000>, <600000000>; + iommus =3D <&vdec_mmu>; + power-domains =3D <&power RK3568_PD_RKVDEC>; + resets =3D <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>, + <&cru SRST_RKVDEC_CA>, <&cru SRST_RKVDEC_CORE>, + <&cru SRST_RKVDEC_HEVC_CA>; + reset-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram =3D <&vdec_sram>; + }; + + vdec_mmu: iommu@fdf80800 { + compatible =3D "rockchip,rk3568-iommu"; + reg =3D <0x0 0xfdf80800 0x0 0x40>, <0x0 0xfdf80840 0x0 0x40>; + interrupts =3D ; + clocks =3D <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; + clock-names =3D "aclk", "iface"; + power-domains =3D <&power RK3568_PD_RKVDEC>; + #iommu-cells =3D <0>; + }; + vicap: video-capture@fdfe0000 { compatible =3D "rockchip,rk3568-vicap"; reg =3D <0x0 0xfdfe0000 0x0 0x200>; --=20 2.34.1