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Fri, 26 Dec 2025 10:30:30 -0800 (PST) Received: from hu-akhilpo-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34e70d65653sm23808883a91.5.2025.12.26.10.30.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Dec 2025 10:30:29 -0800 (PST) From: Akhil P Oommen Date: Fri, 26 Dec 2025 23:59:37 +0530 Subject: [PATCH v5 4/8] dt-bindings: display/msm/rgmu: Document A612 RGMU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251226-qcs615-spin-2-v5-4-354d86460ccb@oss.qualcomm.com> References: <20251226-qcs615-spin-2-v5-0-354d86460ccb@oss.qualcomm.com> In-Reply-To: <20251226-qcs615-spin-2-v5-0-354d86460ccb@oss.qualcomm.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Jessica Zhang , Gaurav Kohli Cc: Dan Carpenter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jie Zhang , Akhil P Oommen , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Compared to GMU, it doesn't manage GPU clock, voltage scaling, bw voting or any other functionalities. All it does is detect an idle GPU and toggle the GDSC switch. As it doesn't access DDR space, it doesn't require iommu. So far, only Adreno 612 GPU has an RGMU core. Document it in qcom,adreno-rgmu.yaml. Signed-off-by: Jie Zhang Signed-off-by: Akhil P Oommen Reviewed-by: Krzysztof Kozlowski --- .../bindings/display/msm/qcom,adreno-rgmu.yaml | 126 +++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 127 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,adreno-rgmu= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,adreno-rgmu.yaml new file mode 100644 index 0000000000000000000000000000000000000000..bacc5b32e6d7b2f2b9e0424e772= 36e6a0ebe9a19 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,adreno-rgmu.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/display/msm/qcom,adreno-rgmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RGMU attached to certain Adreno GPUs + +maintainers: + - Rob Clark + +description: + RGMU (Reduced Graphics Management Unit) IP is present in some GPUs that + belong to Adreno A6xx family. It is a small state machine that helps to + toggle the GX GDSC (connected to CX rail) to implement IFPC feature and = save + power. + +properties: + compatible: + items: + - const: qcom,adreno-rgmu-612.0 + - const: qcom,adreno-rgmu + + reg: + items: + - description: Core RGMU registers + + clocks: + items: + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + - description: GPU SMMU vote clock + + clock-names: + items: + - const: gmu + - const: cxo + - const: axi + - const: memnoc + - const: smmu_vote + + power-domains: + items: + - description: CX GDSC power domain + - description: GX GDSC power domain + + power-domain-names: + items: + - const: cx + - const: gx + + interrupts: + items: + - description: GMU OOB interrupt + - description: GMU interrupt + + interrupt-names: + items: + - const: oob + - const: gmu + + operating-points-v2: true + opp-table: + type: object + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + - power-domain-names + - interrupts + - interrupt-names + - operating-points-v2 + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + gmu@506a000 { + compatible =3D "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu"; + + reg =3D <0x05000000 0x90000>; + + clocks =3D <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names =3D "gmu", + "cxo", + "axi", + "memnoc", + "smmu_vote"; + + power-domains =3D <&gpucc CX_GDSC>, + <&gpucc GX_GDSC>; + power-domain-names =3D "cx", + "gx"; + + interrupts =3D , + ; + interrupt-names =3D "oob", + "gmu"; + + operating-points-v2 =3D <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index dc731d37c8feeff25613c59fe9c929927dadaa7e..ee09fc2a6e597f2432691b268d9= 956846789f39e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7982,6 +7982,7 @@ S: Maintained B: https://gitlab.freedesktop.org/drm/msm/-/issues T: git https://gitlab.freedesktop.org/drm/msm.git F: Documentation/devicetree/bindings/display/msm/gpu.yaml +F: Documentation/devicetree/bindings/display/msm/qcom,adreno-rgmu.yaml F: Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml F: drivers/gpu/drm/msm/adreno/ F: drivers/gpu/drm/msm/msm_gpu.* --=20 2.51.0