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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4f4ac62d53dsm160612891cf.19.2025.12.26.01.19.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Dec 2025 01:19:27 -0800 (PST) From: Wenmeng Liu Date: Fri, 26 Dec 2025 17:19:10 +0800 Subject: [PATCH v7 1/3] media: qcom: camss: Add common TPG support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251226-camss_tpg-v7-1-ccb536734805@oss.qualcomm.com> References: <20251226-camss_tpg-v7-0-ccb536734805@oss.qualcomm.com> In-Reply-To: <20251226-camss_tpg-v7-0-ccb536734805@oss.qualcomm.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, Wenmeng Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766740760; l=24206; i=wenmeng.liu@oss.qualcomm.com; s=20250925; h=from:subject:message-id; bh=eUTZebr6aiB4pg6g5xYDgte/ZopxkH1aSYFsLZvc6rc=; b=CAkNA/RrA39fpmTKXaxFyL5nr70BFDVTcVQjWJ2CTeI2t+gLG7dUzD9FmSsARE50Vr66HHdkR hwLpj0JoxUKDfi3rVOkER7vsSG5rX0LTvZbUCFmOxCjhkBsvqGBdPXX X-Developer-Key: i=wenmeng.liu@oss.qualcomm.com; a=ed25519; pk=fQJjf9C3jGDjE1zj2kO3NQLTbQEaZObVcXAzx5WLPX0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI2MDA4NiBTYWx0ZWRfX14SbgG02WBNN u7Q3z12blNyOep3TVQ36ZyXpMLjJxJmT35i1uSbl90B9sz7VJgjmZXyL/yx3HgR8gEXArnEi74B UYYGqropwADsW3QwU5FB0+t1ZcBkz/xzPaVoQetu+QFlHy0Pbe8Ntvlr7GSyM7+xQImZ1BCw1U9 qHMth0I0jodVabnRjF4ffsOsDetpDitoq+sQjbgOROCNp+BJsW6/7dUZbYBaX9+pIHZwKAwwtif /6OTBNkKYlIGK9xsrbT8CXFPpioyfCVb7kYug/P1SwZjbklIraTr2dD7wCdACqXgZXZpnF8pZcR 4VyNh7RPonh/IhRd2ukR+PcAft3E2TGIrt1oBW6EG8uzLn4MpRGuWlwKiPjmaqprJtHaaP3n6R5 fQpSEUebJp2XCpPVVc8UiWHZCiCc3ZxQK+i09U439Pf9GNlrM7vD5kU62fuZ8a4IOwQvPVqK5le O6eQy8p/KAuPe/fxW9A== X-Proofpoint-GUID: msQSo60KrFQv7HaTlxPD0U6KhqKOo-W7 X-Authority-Analysis: v=2.4 cv=MKVtWcZl c=1 sm=1 tr=0 ts=694e5322 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=9-4OygZIhI6akIEH2MEA:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-ORIG-GUID: msQSo60KrFQv7HaTlxPD0U6KhqKOo-W7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-26_03,2025-12-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 bulkscore=0 impostorscore=0 phishscore=0 adultscore=0 clxscore=1015 suspectscore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512260086 Introduce a new common Test Pattern Generator (TPG) implementation for Qualcomm CAMSS. This module provides a generic interface for pattern generation that can be reused by multiple platforms. Unlike CSID-integrated TPG, this TPG acts as a standalone block that emulates both CSIPHY and sensor behavior, enabling flexible test patterns without external hardware. Signed-off-by: Wenmeng Liu --- drivers/media/platform/qcom/camss/Makefile | 1 + drivers/media/platform/qcom/camss/camss-tpg.c | 710 ++++++++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss-tpg.h | 127 +++++ drivers/media/platform/qcom/camss/camss.h | 5 + 4 files changed, 843 insertions(+) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index 5e349b4915130c71dbff90e73102e46dfede1520..d355e67c25700ac061b878543c3= 2ed8defc03ad0 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -27,5 +27,6 @@ qcom-camss-objs +=3D \ camss-vfe.o \ camss-video.o \ camss-format.o \ + camss-tpg.o \ =20 obj-$(CONFIG_VIDEO_QCOM_CAMSS) +=3D qcom-camss.o diff --git a/drivers/media/platform/qcom/camss/camss-tpg.c b/drivers/media/= platform/qcom/camss/camss-tpg.c new file mode 100644 index 0000000000000000000000000000000000000000..f4c015aafa202e5b64fafa3c543= 128fda6440b11 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-tpg.c @@ -0,0 +1,710 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * + * Qualcomm MSM Camera Subsystem - TPG Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "camss-tpg.h" +#include "camss.h" + +const char * const testgen_payload_modes[] =3D { + "Disabled", + "Incrementing", + "Alternating 0x55/0xAA", + "Reserved", + "Reserved", + "Pseudo-random Data", + "User Specified", + "Reserved", + "Reserved", + "Color bars", + "Reserved" +}; + +static const struct tpg_format_info formats_gen1[] =3D { + { + MEDIA_BUS_FMT_SBGGR8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + 8, + }, + { + MEDIA_BUS_FMT_SGBRG8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + 8, + }, + { + MEDIA_BUS_FMT_SGRBG8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + 8, + }, + { + MEDIA_BUS_FMT_SRGGB8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + 8, + }, + { + MEDIA_BUS_FMT_SBGGR10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + 10, + }, + { + MEDIA_BUS_FMT_SGBRG10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + 10, + }, + { + MEDIA_BUS_FMT_SGRBG10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + 10, + }, + { + MEDIA_BUS_FMT_SRGGB10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + 10, + }, + { + MEDIA_BUS_FMT_SBGGR12_1X12, + DATA_TYPE_RAW_12BIT, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + 12, + }, + { + MEDIA_BUS_FMT_SGBRG12_1X12, + DATA_TYPE_RAW_12BIT, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + 12, + }, + { + MEDIA_BUS_FMT_SGRBG12_1X12, + DATA_TYPE_RAW_12BIT, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + 12, + }, + { + MEDIA_BUS_FMT_SRGGB12_1X12, + DATA_TYPE_RAW_12BIT, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + 12, + }, + { + MEDIA_BUS_FMT_Y8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + 8, + }, + { + MEDIA_BUS_FMT_Y10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + 10, + }, +}; + +const struct tpg_formats tpg_formats_gen1 =3D { + .nformats =3D ARRAY_SIZE(formats_gen1), + .formats =3D formats_gen1 +}; + +const struct tpg_format_info *tpg_get_fmt_entry(struct tpg_device *tpg, + const struct tpg_format_info *formats, + unsigned int nformats, + u32 code) +{ + struct device *dev =3D tpg->camss->dev; + size_t i; + + for (i =3D 0; i < nformats; i++) + if (code =3D=3D formats[i].code) + return &formats[i]; + + dev_warn(dev, "Unknown pixel format code=3D0x%08x\n", code); + + return ERR_PTR(-EINVAL); +} + +/* + * tpg_set_clock_rates - set clock rates on tpg module + * @tpg: tpg device + */ +static int tpg_set_clock_rates(struct tpg_device *tpg) +{ + struct device *dev =3D tpg->camss->dev; + int ret; + int i; + + for (i =3D 0; i < tpg->nclocks; i++) { + struct camss_clock *clock =3D &tpg->clock[i]; + long round_rate; + + if (clock->freq) { + round_rate =3D clk_round_rate(clock->clk, clock->freq[0]); + if (round_rate < 0) { + dev_err(dev, "clk round rate failed: %ld\n", + round_rate); + return -EINVAL; + } + + ret =3D clk_set_rate(clock->clk, round_rate); + if (ret < 0) { + dev_err(dev, "clk set rate failed: %d\n", ret); + return ret; + } + } + } + + return 0; +} + +/* + * tpg_set_power - Power on/off tpg module + * @sd: tpg V4L2 subdevice + * @on: Requested power state + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_set_power(struct v4l2_subdev *sd, int on) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct device *dev =3D tpg->camss->dev; + + if (on) { + int ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + + ret =3D tpg_set_clock_rates(tpg); + if (ret < 0) { + pm_runtime_put_sync(dev); + return ret; + } + + ret =3D camss_enable_clocks(tpg->nclocks, tpg->clock, dev); + if (ret < 0) { + pm_runtime_put_sync(dev); + return ret; + } + + tpg->res->hw_ops->reset(tpg); + + tpg->res->hw_ops->hw_version(tpg); + } else { + camss_disable_clocks(tpg->nclocks, tpg->clock); + + pm_runtime_put_sync(dev); + } + + return 0; +} + +/* + * tpg_set_stream - Enable/disable streaming on tpg module + * @sd: tpg V4L2 subdevice + * @enable: Requested streaming state + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_set_stream(struct v4l2_subdev *sd, int enable) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + int ret =3D 0; + + if (enable) { + ret =3D v4l2_ctrl_handler_setup(&tpg->ctrls); + if (ret < 0) { + dev_err(tpg->camss->dev, + "could not sync v4l2 controls: %d\n", ret); + return ret; + } + } + + ret =3D tpg->res->hw_ops->configure_stream(tpg, enable); + + return ret; +} + +/* + * __tpg_get_format - Get pointer to format structure + * @tpg: tpg device + * @cfg: V4L2 subdev pad configuration + * @pad: pad from which format is requested + * @which: TRY or ACTIVE format + * + * Return pointer to TRY or ACTIVE format structure + */ +static struct v4l2_mbus_framefmt * +__tpg_get_format(struct tpg_device *tpg, + struct v4l2_subdev_state *sd_state, + unsigned int pad, + enum v4l2_subdev_format_whence which) +{ + if (which =3D=3D V4L2_SUBDEV_FORMAT_TRY) + return v4l2_subdev_state_get_format(sd_state, + pad); + + return &tpg->fmt[pad]; +} + +/* + * tpg_try_format - Handle try format by pad subdev method + * @tpg: tpg device + * @cfg: V4L2 subdev pad configuration + * @pad: pad on which format is requested + * @fmt: pointer to v4l2 format structure + * @which: wanted subdev format + */ +static void tpg_try_format(struct tpg_device *tpg, + struct v4l2_subdev_state *sd_state, + unsigned int pad, + struct v4l2_mbus_framefmt *fmt, + enum v4l2_subdev_format_whence which) +{ + unsigned int i; + + switch (pad) { + case MSM_TPG_PAD_SINK: + for (i =3D 0; i < tpg->res->formats->nformats; i++) + if (tpg->res->formats->formats[i].code =3D=3D fmt->code) + break; + + /* If not found, use SBGGR8 as default */ + if (i >=3D tpg->res->formats->nformats) + fmt->code =3D MEDIA_BUS_FMT_SBGGR8_1X8; + + fmt->width =3D clamp_t(u32, fmt->width, 1, 8191); + fmt->height =3D clamp_t(u32, fmt->height, 1, 8191); + + fmt->field =3D V4L2_FIELD_NONE; + fmt->colorspace =3D V4L2_COLORSPACE_SRGB; + + break; + case MSM_TPG_PAD_SRC: + *fmt =3D *__tpg_get_format(tpg, sd_state, + MSM_TPG_PAD_SINK, + which); + + break; + } +} + +/* + * tpg_enum_mbus_code - Handle format enumeration + * @sd: tpg V4L2 subdevice + * @cfg: V4L2 subdev pad configuration + * @code: pointer to v4l2_subdev_mbus_code_enum structure + * return -EINVAL or zero on success + */ +static int tpg_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *format; + + if (code->pad =3D=3D MSM_TPG_PAD_SINK) { + if (code->index >=3D tpg->res->formats->nformats) + return -EINVAL; + + code->code =3D tpg->res->formats->formats[code->index].code; + } else { + if (code->index > 0) + return -EINVAL; + + format =3D __tpg_get_format(tpg, sd_state, + MSM_TPG_PAD_SINK, + code->which); + + code->code =3D format->code; + } + + return 0; +} + +/* + * tpg_enum_frame_size - Handle frame size enumeration + * @sd: tpg V4L2 subdevice + * @cfg: V4L2 subdev pad configuration + * @fse: pointer to v4l2_subdev_frame_size_enum structure + * return -EINVAL or zero on success + */ +static int tpg_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt format; + + if (fse->index !=3D 0) + return -EINVAL; + + format.code =3D fse->code; + format.width =3D 1; + format.height =3D 1; + tpg_try_format(tpg, sd_state, fse->pad, &format, fse->which); + fse->min_width =3D format.width; + fse->min_height =3D format.height; + + if (format.code !=3D fse->code) + return -EINVAL; + + format.code =3D fse->code; + format.width =3D -1; + format.height =3D -1; + tpg_try_format(tpg, sd_state, fse->pad, &format, fse->which); + fse->max_width =3D format.width; + fse->max_height =3D format.height; + + return 0; +} + +/* + * tpg_get_format - Handle get format by pads subdev method + * @sd: tpg V4L2 subdevice + * @cfg: V4L2 subdev pad configuration + * @fmt: pointer to v4l2 subdev format structure + * + * Return -EINVAL or zero on success + */ +static int tpg_get_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *format; + + format =3D __tpg_get_format(tpg, sd_state, fmt->pad, fmt->which); + if (!format) + return -EINVAL; + + fmt->format =3D *format; + + return 0; +} + +/* + * tpg_set_format - Handle set format by pads subdev method + * @sd: tpg V4L2 subdevice + * @cfg: V4L2 subdev pad configuration + * @fmt: pointer to v4l2 subdev format structure + * + * Return -EINVAL or zero on success + */ +static int tpg_set_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *format; + + format =3D __tpg_get_format(tpg, sd_state, fmt->pad, fmt->which); + if (!format) + return -EINVAL; + + tpg_try_format(tpg, sd_state, fmt->pad, &fmt->format, + fmt->which); + *format =3D fmt->format; + + if (fmt->pad =3D=3D MSM_TPG_PAD_SINK) { + format =3D __tpg_get_format(tpg, sd_state, + MSM_TPG_PAD_SRC, + fmt->which); + + *format =3D fmt->format; + tpg_try_format(tpg, sd_state, MSM_TPG_PAD_SRC, + format, + fmt->which); + } + return 0; +} + +/* + * tpg_init_formats - Initialize formats on all pads + * @sd: tpg V4L2 subdevice + * @fh: V4L2 subdev file handle + * + * Initialize all pad formats with default values. + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_init_formats(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + struct v4l2_subdev_format format =3D { + .pad =3D MSM_TPG_PAD_SINK, + .which =3D fh ? V4L2_SUBDEV_FORMAT_TRY : + V4L2_SUBDEV_FORMAT_ACTIVE, + .format =3D { + .code =3D MEDIA_BUS_FMT_SBGGR8_1X8, + .width =3D 1920, + .height =3D 1080 + } + }; + + return tpg_set_format(sd, fh ? fh->state : NULL, &format); +} + +/* + * tpg_set_test_pattern - Set test generator's pattern mode + * @tpg: TPG device + * @value: desired test pattern mode + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_set_test_pattern(struct tpg_device *tpg, s32 value) +{ + return tpg->res->hw_ops->configure_testgen_pattern(tpg, value); +} + +/* + * tpg_s_ctrl - Handle set control subdev method + * @ctrl: pointer to v4l2 control structure + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct tpg_device *tpg =3D container_of(ctrl->handler, + struct tpg_device, ctrls); + int ret =3D -EINVAL; + + switch (ctrl->id) { + case V4L2_CID_TEST_PATTERN: + ret =3D tpg_set_test_pattern(tpg, ctrl->val); + break; + } + + return ret; +} + +static const struct v4l2_ctrl_ops tpg_ctrl_ops =3D { + .s_ctrl =3D tpg_s_ctrl, +}; + +/* + * msm_tpg_subdev_init - Initialize tpg device structure and resources + * @tpg: tpg device + * @res: tpg module resources table + * @id: tpg module id + * + * Return 0 on success or a negative error code otherwise + */ +int msm_tpg_subdev_init(struct camss *camss, + struct tpg_device *tpg, + const struct camss_subdev_resources *res, u8 id) +{ + struct platform_device *pdev; + struct device *dev; + int i, j; + + dev =3D camss->dev; + pdev =3D to_platform_device(dev); + + tpg->camss =3D camss; + tpg->id =3D id; + tpg->res =3D &res->tpg; + tpg->res->hw_ops->subdev_init(tpg); + + tpg->base =3D devm_platform_ioremap_resource_byname(pdev, res->reg[0]); + if (IS_ERR(tpg->base)) + return PTR_ERR(tpg->base); + + tpg->nclocks =3D 0; + while (res->clock[tpg->nclocks]) + tpg->nclocks++; + + if (tpg->nclocks) { + tpg->clock =3D devm_kcalloc(dev, + tpg->nclocks, sizeof(*tpg->clock), + GFP_KERNEL); + if (!tpg->clock) + return -ENOMEM; + + for (i =3D 0; i < tpg->nclocks; i++) { + struct camss_clock *clock =3D &tpg->clock[i]; + + clock->clk =3D devm_clk_get(dev, res->clock[i]); + if (IS_ERR(clock->clk)) + return PTR_ERR(clock->clk); + + clock->name =3D res->clock[i]; + + clock->nfreqs =3D 0; + while (res->clock_rate[i][clock->nfreqs]) + clock->nfreqs++; + + if (!clock->nfreqs) { + clock->freq =3D NULL; + continue; + } + + clock->freq =3D devm_kcalloc(dev, + clock->nfreqs, + sizeof(*clock->freq), + GFP_KERNEL); + if (!clock->freq) + return -ENOMEM; + + for (j =3D 0; j < clock->nfreqs; j++) + clock->freq[j] =3D res->clock_rate[i][j]; + } + } + + return 0; +} + +/* + * tpg_link_setup - Setup tpg connections + * @entity: Pointer to media entity structure + * @local: Pointer to local pad + * @remote: Pointer to remote pad + * @flags: Link flags + * + * Return 0 on success + */ +static int tpg_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + if (flags & MEDIA_LNK_FL_ENABLED) + if (media_pad_remote_pad_first(local)) + return -EBUSY; + + return 0; +} + +static const struct v4l2_subdev_core_ops tpg_core_ops =3D { + .s_power =3D tpg_set_power, +}; + +static const struct v4l2_subdev_video_ops tpg_video_ops =3D { + .s_stream =3D tpg_set_stream, +}; + +static const struct v4l2_subdev_pad_ops tpg_pad_ops =3D { + .enum_mbus_code =3D tpg_enum_mbus_code, + .enum_frame_size =3D tpg_enum_frame_size, + .get_fmt =3D tpg_get_format, + .set_fmt =3D tpg_set_format, +}; + +static const struct v4l2_subdev_ops tpg_v4l2_ops =3D { + .core =3D &tpg_core_ops, + .video =3D &tpg_video_ops, + .pad =3D &tpg_pad_ops, +}; + +static const struct v4l2_subdev_internal_ops tpg_v4l2_internal_ops =3D { + .open =3D tpg_init_formats, +}; + +static const struct media_entity_operations tpg_media_ops =3D { + .link_setup =3D tpg_link_setup, + .link_validate =3D v4l2_subdev_link_validate, +}; + +/* + * msm_tpg_register_entity - Register subdev node for tpg module + * @tpg: tpg device + * @v4l2_dev: V4L2 device + * + * Return 0 on success or a negative error code otherwise + */ +int msm_tpg_register_entity(struct tpg_device *tpg, + struct v4l2_device *v4l2_dev) +{ + struct v4l2_subdev *sd =3D &tpg->subdev; + struct media_pad *pads =3D tpg->pads; + struct device *dev =3D tpg->camss->dev; + int ret; + + v4l2_subdev_init(sd, &tpg_v4l2_ops); + sd->internal_ops =3D &tpg_v4l2_internal_ops; + sd->flags |=3D V4L2_SUBDEV_FL_HAS_DEVNODE | + V4L2_SUBDEV_FL_HAS_EVENTS; + snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d", + MSM_TPG_NAME, tpg->id); + sd->grp_id =3D TPG_GUP_ID; + v4l2_set_subdevdata(sd, tpg); + + ret =3D v4l2_ctrl_handler_init(&tpg->ctrls, 1); + if (ret < 0) { + dev_err(dev, "Failed to init ctrl handler: %d\n", ret); + return ret; + } + + tpg->testgen_mode =3D v4l2_ctrl_new_std_menu_items(&tpg->ctrls, + &tpg_ctrl_ops, V4L2_CID_TEST_PATTERN, + tpg->testgen.nmodes, 0, 0, + tpg->testgen.modes); + + if (tpg->ctrls.error) { + dev_err(dev, "Failed to init ctrl: %d\n", tpg->ctrls.error); + ret =3D tpg->ctrls.error; + goto free_ctrl; + } + + tpg->subdev.ctrl_handler =3D &tpg->ctrls; + + ret =3D tpg_init_formats(sd, NULL); + if (ret < 0) { + dev_err(dev, "Failed to init format: %d\n", ret); + goto free_ctrl; + } + + pads[MSM_TPG_PAD_SINK].flags =3D MEDIA_PAD_FL_SINK; + pads[MSM_TPG_PAD_SRC].flags =3D MEDIA_PAD_FL_SOURCE; + + sd->entity.function =3D MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; + sd->entity.ops =3D &tpg_media_ops; + ret =3D media_entity_pads_init(&sd->entity, MSM_TPG_PADS_NUM, pads); + if (ret < 0) { + dev_err(dev, "Failed to init media entity: %d\n", ret); + goto free_ctrl; + } + + ret =3D v4l2_device_register_subdev(v4l2_dev, sd); + if (ret < 0) { + dev_err(dev, "Failed to register subdev: %d\n", ret); + media_entity_cleanup(&sd->entity); + goto free_ctrl; + } + + return 0; + +free_ctrl: + v4l2_ctrl_handler_free(&tpg->ctrls); + + return ret; +} + +/* + * msm_tpg_unregister_entity - Unregister tpg module subdev node + * @tpg: tpg device + */ +void msm_tpg_unregister_entity(struct tpg_device *tpg) +{ + v4l2_device_unregister_subdev(&tpg->subdev); + media_entity_cleanup(&tpg->subdev.entity); + v4l2_ctrl_handler_free(&tpg->ctrls); +} diff --git a/drivers/media/platform/qcom/camss/camss-tpg.h b/drivers/media/= platform/qcom/camss/camss-tpg.h new file mode 100644 index 0000000000000000000000000000000000000000..1a16addac19418f2f11d0b8abb1= c865c99888bde --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-tpg.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * camss-tpg.h + * + * Qualcomm MSM Camera Subsystem - TPG Module + * + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#ifndef QC_MSM_CAMSS_TPG_H +#define QC_MSM_CAMSS_TPG_H + +#include +#include +#include +#include +#include +#include + +#define MSM_TPG_PAD_SINK 0 +#define MSM_TPG_PAD_SRC 1 +#define MSM_TPG_PADS_NUM 2 + +#define DATA_TYPE_RAW_8BIT 0x2a +#define DATA_TYPE_RAW_10BIT 0x2b +#define DATA_TYPE_RAW_12BIT 0x2c + +#define ENCODE_FORMAT_UNCOMPRESSED_8_BIT 0x1 +#define ENCODE_FORMAT_UNCOMPRESSED_10_BIT 0x2 +#define ENCODE_FORMAT_UNCOMPRESSED_12_BIT 0x3 +#define ENCODE_FORMAT_UNCOMPRESSED_14_BIT 0x4 +#define ENCODE_FORMAT_UNCOMPRESSED_16_BIT 0x5 +#define ENCODE_FORMAT_UNCOMPRESSED_20_BIT 0x6 +#define ENCODE_FORMAT_UNCOMPRESSED_24_BIT 0x7 + +#define TPG_GUP_ID 0 +#define MSM_TPG_NAME "msm_tpg" + +enum tpg_testgen_mode { + TPG_PAYLOAD_MODE_DISABLED =3D 0, + TPG_PAYLOAD_MODE_INCREMENTING =3D 1, + TPG_PAYLOAD_MODE_ALTERNATING_55_AA =3D 2, + TPG_PAYLOAD_MODE_RANDOM =3D 5, + TPG_PAYLOAD_MODE_USER_SPECIFIED =3D 6, + TPG_PAYLOAD_MODE_COLOR_BARS =3D 9, + TPG_PAYLOAD_MODE_NUM_SUPPORTED_GEN1 =3D 9, +}; + +struct tpg_testgen_config { + enum tpg_testgen_mode mode; + const char * const*modes; + u8 nmodes; +}; + +struct tpg_format_info { + u32 code; + u8 data_type; + u8 encode_format; + u8 bpp; +}; + +struct tpg_formats { + unsigned int nformats; + const struct tpg_format_info *formats; +}; + +struct tpg_device; + +struct tpg_hw_ops { + int (*configure_stream)(struct tpg_device *tpg, u8 enable); + + int (*configure_testgen_pattern)(struct tpg_device *tpg, s32 val); + + u32 (*hw_version)(struct tpg_device *tpg); + + int (*reset)(struct tpg_device *tpg); + + void (*subdev_init)(struct tpg_device *tpg); +}; + +struct tpg_subdev_resources { + u8 lane_cnt; + u8 vc_cnt; + const struct tpg_formats *formats; + const struct tpg_hw_ops *hw_ops; +}; + +struct tpg_device { + struct camss *camss; + u8 id; + struct v4l2_subdev subdev; + struct media_pad pads[MSM_TPG_PADS_NUM]; + void __iomem *base; + struct camss_clock *clock; + int nclocks; + struct tpg_testgen_config testgen; + struct v4l2_mbus_framefmt fmt[MSM_TPG_PADS_NUM]; + struct v4l2_ctrl_handler ctrls; + struct v4l2_ctrl *testgen_mode; + const struct tpg_subdev_resources *res; + const struct tpg_format *formats; + unsigned int nformats; + u32 hw_version; +}; + +struct camss_subdev_resources; + +const struct tpg_format_info *tpg_get_fmt_entry(struct tpg_device *tpg, + const struct tpg_format_info *formats, + unsigned int nformats, + u32 code); + +int msm_tpg_subdev_init(struct camss *camss, + struct tpg_device *tpg, + const struct camss_subdev_resources *res, u8 id); + +int msm_tpg_register_entity(struct tpg_device *tpg, + struct v4l2_device *v4l2_dev); + +void msm_tpg_unregister_entity(struct tpg_device *tpg); + +extern const char * const testgen_payload_modes[]; + +extern const struct tpg_formats tpg_formats_gen1; + +extern const struct tpg_hw_ops tpg_ops_gen1; + +#endif /* QC_MSM_CAMSS_TPG_H */ diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/plat= form/qcom/camss/camss.h index 9d9a62640e25dce0e8d45af9df01bbfd64b9bb4b..a892a87bed8bde8919200d6eac2= b7a5338763c0e 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -21,6 +21,7 @@ #include "camss-csid.h" #include "camss-csiphy.h" #include "camss-ispif.h" +#include "camss-tpg.h" #include "camss-vfe.h" #include "camss-format.h" =20 @@ -52,6 +53,7 @@ struct camss_subdev_resources { char *interrupt[CAMSS_RES_MAX]; union { struct csiphy_subdev_resources csiphy; + struct tpg_subdev_resources tpg; struct csid_subdev_resources csid; struct vfe_subdev_resources vfe; }; @@ -104,6 +106,7 @@ struct camss_resources { enum camss_version version; const char *pd_name; const struct camss_subdev_resources *csiphy_res; + const struct camss_subdev_resources *tpg_res; const struct camss_subdev_resources *csid_res; const struct camss_subdev_resources *ispif_res; const struct camss_subdev_resources *vfe_res; @@ -111,6 +114,7 @@ struct camss_resources { const struct resources_icc *icc_res; const unsigned int icc_path_num; const unsigned int csiphy_num; + const unsigned int tpg_num; const unsigned int csid_num; const unsigned int vfe_num; }; @@ -121,6 +125,7 @@ struct camss { struct media_device media_dev; struct device *dev; struct csiphy_device *csiphy; + struct tpg_device *tpg; struct csid_device *csid; struct ispif_device *ispif; struct vfe_device *vfe; --=20 2.34.1