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Thu, 25 Dec 2025 13:03:26 -0800 (PST) From: Alex Tran Date: Thu, 25 Dec 2025 13:03:08 -0800 Subject: [PATCH v3 2/2] media: dt-bindings: ti,omap3isp: Convert to DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251225-dt-bindings-et8ek8-omap3isp-v3-2-b027e0db69a5@gmail.com> References: <20251225-dt-bindings-et8ek8-omap3isp-v3-0-b027e0db69a5@gmail.com> In-Reply-To: <20251225-dt-bindings-et8ek8-omap3isp-v3-0-b027e0db69a5@gmail.com> To: Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Pavel Machek , Sakari Ailus , Laurent Pinchart Cc: Pavel Machek , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alex Tran X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8393; i=alex.t.tran@gmail.com; h=from:subject:message-id; bh=QTYAYLX9cyK63LJsZQA3buVLpKA8Ar82kX/gmIYypc0=; b=owEBbQKS/ZANAwAKAXT5fTREJs3IAcsmYgBpTaaa8PSmG7RBzDHXs+N700GMb0MDuOFGF970g 6WVB1TwcoyJAjMEAAEKAB0WIQQAohViG04SVxUVrcd0+X00RCbNyAUCaU2mmgAKCRB0+X00RCbN yMshEACQ//FJbbkjvlHaEBuDt6+MWP0iCPsS5MsdrgA7V4T1a3brX43Tg5T56hAOnyPm4K8LyNl Ak6hQu1U0ZB3imHXlOBIDOQqZxk/TqCP3VY1uJNeui9WUXXc08T9sYyHh9Z2F53cQxC8qugslFs 70cvVnkdZCnIkiy1P9E6qBndkeIayQIq14MwMni1ijg6CmIdN5w5C2iHTlZileRGISQSFjXXvXe D6vqV5ge8/zK3+8PJHJsmI8Kj0a+pl9A6oSspupnfST0KkuQs/kSUUhK9mYGJKHFoIQonem3Hjz xPYQzzcH1Puc0PcbQnY8VoteG2g0vHrF3E7yOFGA9A8hPv2Scf+UhugNBPT07iJK/ieesGFrtbo gdfgEZFH55jlCK7ZseFtbh7ObrkIJaWNqadaAm1KHxr3candVkneEgxi1kiMl90emKb5jkFYNo0 VU3cuXgTe9+d5ctXumHnlm5nt0ehR8Nw5d/pT2RLQbqWrHFhWU2/xNg0pjY5KMk57cxyKrGwewo AQPiss6khuQCzJH19wteEP+hPMCBEBtwQ6CCkLbaiiBalVwPAHtNGk9NcTggNgQYC26kbnKCKpD koIShEsvOAL/DKSZIndmh3lismqkxMlycxaiO2aR3dUwVAgoczvHKiPUoUbj8fuC9BAQXE8OzCa 36nBicogvSQ0Aaw== X-Developer-Key: i=alex.t.tran@gmail.com; a=openpgp; fpr=00A215621B4E12571515ADC774F97D344426CDC8 Convert binding for ti,omap3isp from TXT to YAML format. Signed-off-by: Alex Tran Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/media/ti,omap3isp.txt | 71 -------- .../devicetree/bindings/media/ti,omap3isp.yaml | 189 +++++++++++++++++= ++++ 2 files changed, 189 insertions(+), 71 deletions(-) diff --git a/Documentation/devicetree/bindings/media/ti,omap3isp.txt b/Docu= mentation/devicetree/bindings/media/ti,omap3isp.txt deleted file mode 100644 index ac23de8556412c52710f46c3ea015d2976c96dad..000000000000000000000000000= 0000000000000 --- a/Documentation/devicetree/bindings/media/ti,omap3isp.txt +++ /dev/null @@ -1,71 +0,0 @@ -OMAP 3 ISP Device Tree bindings -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D - -The DT definitions can be found in include/dt-bindings/media/omap3-isp.h. - -Required properties -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - -compatible : must contain "ti,omap3-isp" - -reg : the two registers sets (physical address and length) for the - ISP. The first set contains the core ISP registers up to - the end of the SBL block. The second set contains the - CSI PHYs and receivers registers. -interrupts : the ISP interrupt specifier -iommus : phandle and IOMMU specifier for the IOMMU that serves the ISP -syscon : the phandle and register offset to the Complex I/O or CSI-PHY - register -ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430) - 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630) -#clock-cells : Must be 1 --- the ISP provides two external clocks, - cam_xclka and cam_xclkb, at indices 0 and 1, - respectively. Please find more information on common - clock bindings in ../clock/clock-bindings.txt. - -Port nodes (optional) ---------------------- - -More documentation on these bindings is available in -video-interfaces.txt in the same directory. - -reg : The interface: - 0 - parallel (CCDC) - 1 - CSIPHY1 -- CSI2C / CCP2B on 3630; - CSI1 -- CSIb on 3430 - 2 - CSIPHY2 -- CSI2A / CCP2B on 3630; - CSI2 -- CSIa on 3430 - -Optional properties -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - -vdd-csiphy1-supply : voltage supply of the CSI-2 PHY 1 -vdd-csiphy2-supply : voltage supply of the CSI-2 PHY 2 - -Endpoint nodes --------------- - -lane-polarities : lane polarity (required on CSI-2) - 0 -- not inverted; 1 -- inverted -data-lanes : an array of data lanes from 1 to 3. The length can - be either 1 or 2. (required on CSI-2) -clock-lanes : the clock lane (from 1 to 3). (required on CSI-2) - - -Example -=3D=3D=3D=3D=3D=3D=3D - - isp@480bc000 { - compatible =3D "ti,omap3-isp"; - reg =3D <0x480bc000 0x12fc - 0x480bd800 0x0600>; - interrupts =3D <24>; - iommus =3D <&mmu_isp>; - syscon =3D <&scm_conf 0x2f0>; - ti,phy-type =3D ; - #clock-cells =3D <1>; - ports { - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; diff --git a/Documentation/devicetree/bindings/media/ti,omap3isp.yaml b/Doc= umentation/devicetree/bindings/media/ti,omap3isp.yaml new file mode 100644 index 0000000000000000000000000000000000000000..7155fd3db505ec577b03df537f4= dfa92ce784094 --- /dev/null +++ b/Documentation/devicetree/bindings/media/ti,omap3isp.yaml @@ -0,0 +1,189 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/ti,omap3isp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments OMAP 3 Image Signal Processor (ISP) + +maintainers: + - Laurent Pinchart + - Sakari Ailus + +description: + The OMAP 3 ISP is an image signal processor present in OMAP 3 SoCs. + +properties: + compatible: + const: ti,omap3-isp + + reg: + items: + - description: Core ISP registers up to the end of the SBL block + - description: CSI PHYs and receivers registers + + interrupts: + maxItems: 1 + + iommus: + maxItems: 1 + + syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to System Control Module + - description: register offset to Complex I/O or CSI-PHY register + description: + Phandle and register offset to the Complex I/O or CSI-PHY register + + ti,phy-type: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + 0 - OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. OMAP 3430) + 1 - OMAP3ISP_PHY_TYPE_CSIPHY (e.g. OMAP 3630) + + '#clock-cells': + const: 1 + description: + The ISP provides two external clocks, cam_xclka and cam_xclkb, + at indices 0 and 1 respectively. + + vdd-csiphy1-supply: + description: Voltage supply of the CSI-2 PHY 1 + + vdd-csiphy2-supply: + description: Voltage supply of the CSI-2 PHY 2 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Parallel (CCDC) interface + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: | + CSIPHY1 interface: + OMAP 3630: CSI2C / CCP2B + OMAP 3430: CSI1 (CSIb) + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + lane-polarities: + minItems: 2 + maxItems: 3 + + data-lanes: + minItems: 1 + maxItems: 2 + items: + minimum: 1 + maximum: 3 + + clock-lanes: + minimum: 1 + maximum: 3 + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: | + CSIPHY2 interface: + OMAP 3630: CSI2A / CCP2B + OMAP 3430: CSI2 (CSIa) + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + lane-polarities: + minItems: 2 + maxItems: 3 + + data-lanes: + minItems: 1 + maxItems: 2 + items: + minimum: 1 + maximum: 3 + + clock-lanes: + minimum: 1 + maximum: 3 + +required: + - compatible + - reg + - interrupts + - iommus + - syscon + - ti,phy-type + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + isp@480bc000 { + compatible =3D "ti,omap3-isp"; + reg =3D <0x480bc000 0x12fc>, + <0x480bd800 0x0600>; + interrupts =3D <24>; + iommus =3D <&mmu_isp>; + syscon =3D <&scm_conf 0x2f0>; + ti,phy-type =3D ; + #clock-cells =3D <1>; + vdd-csiphy1-supply =3D <&vaux2>; + vdd-csiphy2-supply =3D <&vaux2>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + parallel_ep: endpoint { + remote-endpoint =3D <¶llel>; + }; + }; + + port@1 { + reg =3D <1>; + csi1_ep: endpoint { + remote-endpoint =3D <&smia_1>; + clock-lanes =3D <1>; + data-lanes =3D <2>; + lane-polarities =3D <0 0>; + }; + }; + + port@2 { + reg =3D <2>; + csi2a_ep: endpoint { + remote-endpoint =3D <&smia_2>; + clock-lanes =3D <2>; + data-lanes =3D <1 3>; + lane-polarities =3D <1 1 1>; + }; + }; + }; + }; --=20 2.51.0