From nobody Tue Feb 10 14:32:11 2026 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 665A62DE70D; Wed, 24 Dec 2025 16:13:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766592788; cv=none; b=SD3e8YJYJwVtoNo55iDlZMTPw1Kv6IIJymnTgvFEcXxFWGX2bOXdhfR+06V/oG5Wu9aQr4ODz2tAE6tW2W7yoXPPfXB5j27LAOlWE8t+97HqSHEM2v3EGyrauh7wgqGRHBbF1fJfkQjFav+pB3IQcFZmKP4fDChOOitV3vHmA9s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766592788; c=relaxed/simple; bh=gazS/1qlDqhGht0zSyU5/vmxqKB8XNpSEOkkI0uRa4A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kXyhn4VnGEKo8Ao63zrpUb5bpAA0FzEWjciWLpGLd3vpZprq7E9hGKZBmJzePkJRX2byAnYNRJsoNrQKkfX1IECapCzShyI3y5qCebklHF9xk4w69zhYcceDBQTtWwHrbjxlZzmsvYTqVZnBQSXv7fQwqTw49h1W6Ai6vTuuouQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.100.54]) by APP-05 (Coremail) with SMTP id zQCowAA3yw7WEExpgGPNAQ--.14041S6; Thu, 25 Dec 2025 00:12:18 +0800 (CST) From: Icenowy Zheng To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini , Guo Ren , Fu Wei , Philipp Zabel , Heiko Stuebner , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Michal Wilczynski Cc: Han Gao , Yao Zi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Icenowy Zheng , Krzysztof Kozlowski Subject: [PATCH v4 4/9] dt-bindings: display/bridge: add binding for TH1520 HDMI controller Date: Thu, 25 Dec 2025 00:12:00 +0800 Message-ID: <20251224161205.1132149-5-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251224161205.1132149-1-zhengxingda@iscas.ac.cn> References: <20251224161205.1132149-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowAA3yw7WEExpgGPNAQ--.14041S6 X-Coremail-Antispam: 1UD129KBjvJXoWxuF1rJF17Xr1ftFyrtw4fZrb_yoW5Kw4Upa 1fGa1kJFykJF17ua1xJr1IkrZYqrZ5AFnYgr17Ww1jy3y5WFy2qrZIkrn8XFyrJF4xZay3 ZFZ8Xr1fKa1av3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmv14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26r4j6F4UM28EF7xvwVC2z280aVCY1x0267AKxVW8Jr0_ Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6x IIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_ Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8c xan2IY04v7MxkF7I0En4kS14v26r4a6rW5MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCj c4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4 CE17CEb7AF67AKxVW8ZVWrXwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1x MIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8Jr0_Cr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJV WUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4UJVWxJrUv cSsGvfC2KfnxnUUI43ZEXa7sRRjg43UUUUU== X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" From: Icenowy Zheng T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller paired with DesignWare HDMI PHY, with an extra clock gate for HDMI pixel clock and two reset controls. Add a device tree binding to it. Signed-off-by: Icenowy Zheng Signed-off-by: Icenowy Zheng Reviewed-by: Krzysztof Kozlowski --- No changes in v3, v4. Changes in v2: - Re-aligned multi-line clocks/resets in example. - Added Krzysztof's R-b. P.S. Should the mail addresss of Krzysztof be changed? I got notice email that says he's no longer working for Linaro. .../display/bridge/thead,th1520-dw-hdmi.yaml | 120 ++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/thead,= th1520-dw-hdmi.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/thead,th1520-= dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/thead,th152= 0-dw-hdmi.yaml new file mode 100644 index 0000000000000..68fff885ce15b --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi= .yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/thead,th1520-dw-hdmi.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-Head TH1520 DesignWare HDMI TX Encoder + +maintainers: + - Icenowy Zheng + +description: + The HDMI transmitter is a Synopsys DesignWare HDMI TX controller + paired with a DesignWare HDMI Gen2 TX PHY. + +allOf: + - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml# + +properties: + compatible: + enum: + - thead,th1520-dw-hdmi + + reg-io-width: + const: 4 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: iahb + - const: isfr + - const: cec + - const: pix + + resets: + items: + - description: Main reset + - description: Configuration APB reset + + reset-names: + items: + - const: main + - const: apb + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input port connected to DC8200 DPU "DP" output + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: HDMI output port + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - reg-io-width + - clocks + - clock-names + - resets + - reset-names + - interrupts + - ports + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + hdmi@ffef540000 { + compatible =3D "thead,th1520-dw-hdmi"; + reg =3D <0xff 0xef540000 0x0 0x40000>; + reg-io-width =3D <4>; + interrupts =3D <111 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk_vo CLK_HDMI_PCLK>, + <&clk_vo CLK_HDMI_SFR>, + <&clk_vo CLK_HDMI_CEC>, + <&clk_vo CLK_HDMI_PIXCLK>; + clock-names =3D "iahb", "isfr", "cec", "pix"; + resets =3D <&rst_vo TH1520_RESET_ID_HDMI>, + <&rst_vo TH1520_RESET_ID_HDMI_APB>; + reset-names =3D "main", "apb"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + + hdmi_in: endpoint { + remote-endpoint =3D <&dpu_out_dp1>; + }; + }; + + port@1 { + reg =3D <1>; + + hdmi_out_conn: endpoint { + remote-endpoint =3D <&hdmi_conn_in>; + }; + }; + }; + }; + }; --=20 2.52.0