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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Dec 2025 13:32:05.2688 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cc161d93-a5a9-4411-56bd-08de42f0d43f X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.194];Helo=[lewvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR10MB7564 Content-Type: text/plain; charset="utf-8" Update the AM65x DSS bindings to support AM62L which has a single video port. Add conditional constraints for AM62L. Signed-off-by: Swamil Jain --- .../bindings/display/ti/ti,am65x-dss.yaml | 95 +++++++++++++++---- 1 file changed, 76 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml= b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 38fcee91211e..ce39690df4e5 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -36,34 +36,50 @@ properties: reg: description: Addresses to each DSS memory region described in the SoC's TRM. - items: - - description: common DSS register area - - description: VIDL1 light video plane - - description: VID video plane - - description: OVR1 overlay manager for vp1 - - description: OVR2 overlay manager for vp2 - - description: VP1 video port 1 - - description: VP2 video port 2 - - description: common1 DSS register area + oneOf: + - items: + - description: common DSS register area + - description: VIDL1 light video plane + - description: VID video plane + - description: OVR1 overlay manager for vp1 + - description: OVR2 overlay manager for vp2 + - description: VP1 video port 1 + - description: VP2 video port 2 + - description: common1 DSS register area + - items: + - description: common DSS register area + - description: VIDL1 light video plane + - description: OVR1 overlay manager for vp1 + - description: VP1 video port 1 + - description: common1 DSS register area =20 reg-names: - items: - - const: common - - const: vidl1 - - const: vid - - const: ovr1 - - const: ovr2 - - const: vp1 - - const: vp2 - - const: common1 + oneOf: + - items: + - const: common + - const: vidl1 + - const: vid + - const: ovr1 + - const: ovr2 + - const: vp1 + - const: vp2 + - const: common1 + - items: + - const: common + - const: vidl1 + - const: ovr1 + - const: vp1 + - const: common1 =20 clocks: + minItems: 2 items: - description: fck DSS functional clock - description: vp1 Video Port 1 pixel clock - description: vp2 Video Port 2 pixel clock =20 clock-names: + minItems: 2 items: - const: fck - const: vp1 @@ -84,7 +100,8 @@ properties: maxItems: 1 description: phandle to the associated power domain =20 - dma-coherent: true + dma-coherent: + type: boolean =20 ports: $ref: /schemas/graph.yaml#/properties/ports @@ -195,6 +212,46 @@ allOf: port@0: properties: endpoint@1: false + - if: + properties: + compatible: + contains: + const: ti,am62l-dss + then: + properties: + clock-names: + maxItems: 2 + clocks: + maxItems: 2 + reg: + maxItems: 5 + + - if: + properties: + compatible: + contains: + const: ti,am62l-dss + then: + properties: + reg-names: + items: + - const: common + - const: vidl1 + - const: ovr1 + - const: vp1 + - const: common1 + else: + properties: + reg-names: + items: + - const: common + - const: vidl1 + - const: vid + - const: ovr1 + - const: ovr2 + - const: vp1 + - const: vp2 + - const: common1 =20 required: - compatible