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This makes it incompatible with any of the earlier platforms and therefore requires a dedicated compatible. So document it. Acked-by: Rob Herring (Arm) Signed-off-by: Abel Vesa Signed-off-by: Abel Vesa --- Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Docu= mentation/devicetree/bindings/phy/qcom,edp-phy.yaml index bfc4d75f50ff..4a1daae3d8d4 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -18,6 +18,7 @@ properties: compatible: oneOf: - enum: + - qcom,glymur-dp-phy - qcom,sa8775p-edp-phy - qcom,sc7280-edp-phy - qcom,sc8180x-edp-phy @@ -72,6 +73,7 @@ allOf: properties: compatible: enum: + - qcom,glymur-dp-phy - qcom,x1e80100-dp-phy then: properties: --=20 2.48.1 From nobody Sat Feb 7 06:55:25 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8369E32548E for ; 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This hasn't been an issue so far on currently supported platforms, because the init sequence never spanned beyond DP_PHY_AUX_CFG9. However, on the new upcoming Glymur platform, these are updated along with the rest of the init sequence. So update the size of the array holding the config to 13. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa Signed-off-by: Abel Vesa --- drivers/phy/qualcomm/phy-qcom-edp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index 06a08c9ea0f7..f98fe83de42e 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -32,7 +32,7 @@ #define DP_PHY_PD_CTL 0x001c #define DP_PHY_MODE 0x0020 =20 -#define DP_AUX_CFG_SIZE 10 +#define DP_AUX_CFG_SIZE 13 #define DP_PHY_AUX_CFG(n) (0x24 + (0x04 * (n))) =20 #define DP_PHY_AUX_INTERRUPT_MASK 0x0058 --=20 2.48.1 From nobody Sat Feb 7 06:55:25 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9918F329E73 for ; Wed, 24 Dec 2025 11:11:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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So in order to be able to differentiate between them, add these ones with DP prefix. Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa Signed-off-by: Abel Vesa --- .../phy/qualcomm/phy-qcom-qmp-qserdes-dp-com-v8.h | 52 ++++++++++++++++++= ++++ 1 file changed, 52 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-dp-com-v8.h b/driver= s/phy/qualcomm/phy-qcom-qmp-qserdes-dp-com-v8.h new file mode 100644 index 000000000000..93edabb830af --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-dp-com-v8.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2025 Linaro Ltd. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_DP_COM_V8_H_ +#define QCOM_PHY_QMP_QSERDES_DP_COM_V8_H_ + +/* Only for DP QMP V8 PHY - QSERDES COM registers */ +#define DP_QSERDES_V8_COM_HSCLK_SEL_1 0x03c +#define DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x058 +#define DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x05c +#define DP_QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0 0x060 +#define DP_QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0 0x064 +#define DP_QSERDES_V8_COM_CP_CTRL_MODE0 0x070 +#define DP_QSERDES_V8_COM_PLL_RCTRL_MODE0 0x074 +#define DP_QSERDES_V8_COM_PLL_CCTRL_MODE0 0x078 +#define DP_QSERDES_V8_COM_CORECLK_DIV_MODE0 0x07c +#define DP_QSERDES_V8_COM_LOCK_CMP1_MODE0 0x080 +#define DP_QSERDES_V8_COM_LOCK_CMP2_MODE0 0x084 +#define DP_QSERDES_V8_COM_DEC_START_MODE0 0x088 +#define DP_QSERDES_V8_COM_DIV_FRAC_START1_MODE0 0x090 +#define DP_QSERDES_V8_COM_DIV_FRAC_START2_MODE0 0x094 +#define DP_QSERDES_V8_COM_DIV_FRAC_START3_MODE0 0x098 +#define DP_QSERDES_V8_COM_INTEGLOOP_GAIN0_MODE0 0x0a0 +#define DP_QSERDES_V8_COM_VCO_TUNE1_MODE0 0x0a8 +#define DP_QSERDES_V8_COM_INTEGLOOP_GAIN1_MODE0 0x0a4 +#define DP_QSERDES_V8_COM_VCO_TUNE2_MODE0 0x0ac +#define DP_QSERDES_V8_COM_BG_TIMER 0x0bc +#define DP_QSERDES_V8_COM_SSC_EN_CENTER 0x0c0 +#define DP_QSERDES_V8_COM_SSC_ADJ_PER1 0x0c4 +#define DP_QSERDES_V8_COM_SSC_PER1 0x0cc +#define DP_QSERDES_V8_COM_SSC_PER2 0x0d0 +#define DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN 0x0dc +#define DP_QSERDES_V8_COM_CLK_ENABLE1 0x0e0 +#define DP_QSERDES_V8_COM_SYS_CLK_CTRL 0x0e4 +#define DP_QSERDES_V8_COM_SYSCLK_BUF_ENABLE 0x0e8 +#define DP_QSERDES_V8_COM_PLL_IVCO 0x0f4 +#define DP_QSERDES_V8_COM_SYSCLK_EN_SEL 0x110 +#define DP_QSERDES_V8_COM_RESETSM_CNTRL 0x118 +#define DP_QSERDES_V8_COM_LOCK_CMP_EN 0x120 +#define DP_QSERDES_V8_COM_VCO_TUNE_CTRL 0x13c +#define DP_QSERDES_V8_COM_VCO_TUNE_MAP 0x140 +#define DP_QSERDES_V8_COM_CLK_SELECT 0x164 +#define DP_QSERDES_V8_COM_CORE_CLK_EN 0x170 +#define DP_QSERDES_V8_COM_CMN_CONFIG_1 0x174 +#define DP_QSERDES_V8_COM_SVS_MODE_CLK_SEL 0x180 +#define DP_QSERDES_V8_COM_CLK_FWD_CONFIG_1 0x2f4 +#define DP_QSERDES_V8_COM_CMN_STATUS 0x314 +#define DP_QSERDES_V8_COM_C_READY_STATUS 0x33c + +#endif --=20 2.48.1 From nobody Sat Feb 7 06:55:25 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F991325721 for ; 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So rework the driver to support this new version and add the platform specific configuration data. While at it, add the rest of the AUX_CFG reset values for the v4 and v5 platforms, which makes the handling of the platforms specific array cleaner, as they are single sized now. Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa --- drivers/phy/qualcomm/phy-qcom-edp.c | 227 ++++++++++++++++++++++++++++++++= ++-- 1 file changed, 219 insertions(+), 8 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index f98fe83de42e..13feab99feec 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -26,6 +26,8 @@ #include "phy-qcom-qmp-qserdes-com-v4.h" #include "phy-qcom-qmp-qserdes-com-v6.h" =20 +#include "phy-qcom-qmp-qserdes-dp-com-v8.h" + /* EDP_PHY registers */ #define DP_PHY_CFG 0x0010 #define DP_PHY_CFG_1 0x0014 @@ -76,6 +78,7 @@ struct phy_ver_ops { int (*com_power_on)(const struct qcom_edp *edp); int (*com_resetsm_cntrl)(const struct qcom_edp *edp); int (*com_bias_en_clkbuflr)(const struct qcom_edp *edp); + int (*com_clk_fwd_cfg)(const struct qcom_edp *edp); int (*com_configure_pll)(const struct qcom_edp *edp); int (*com_configure_ssc)(const struct qcom_edp *edp); }; @@ -83,6 +86,7 @@ struct phy_ver_ops { struct qcom_edp_phy_cfg { bool is_edp; const u8 *aux_cfg; + const u8 *vco_div_cfg; const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg; const struct phy_ver_ops *ver_ops; }; @@ -181,8 +185,12 @@ static const struct qcom_edp_swing_pre_emph_cfg edp_ph= y_swing_pre_emph_cfg =3D { .pre_emphasis_hbr3_hbr2 =3D &edp_pre_emp_hbr2_hbr3, }; =20 -static const u8 edp_phy_aux_cfg_v4[10] =3D { - 0x00, 0x13, 0x24, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03 +static const u8 edp_phy_aux_cfg_v4[DP_AUX_CFG_SIZE] =3D { + 0x00, 0x13, 0x24, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03, 0x02, 0x02, 0= x00, +}; + +static const u8 edp_phy_vco_div_cfg_v4[4] =3D { + 0x01, 0x01, 0x02, 0x00, }; =20 static const u8 edp_pre_emp_hbr_rbr_v5[4][4] =3D { @@ -206,8 +214,16 @@ static const struct qcom_edp_swing_pre_emph_cfg edp_ph= y_swing_pre_emph_cfg_v5 =3D .pre_emphasis_hbr3_hbr2 =3D &edp_pre_emp_hbr2_hbr3_v5, }; =20 -static const u8 edp_phy_aux_cfg_v5[10] =3D { - 0x00, 0x13, 0xa4, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03 +static const u8 edp_phy_aux_cfg_v5[DP_AUX_CFG_SIZE] =3D { + 0x00, 0x13, 0xa4, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03, 0x02, 0x02, 0= x00, +}; + +static const u8 edp_phy_aux_cfg_v8[DP_AUX_CFG_SIZE] =3D { + 0x00, 0x00, 0xa0, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03, 0x02, 0x02, 0= x04, +}; + +static const u8 edp_phy_vco_div_cfg_v8[4] =3D { + 0x00, 0x00, 0x02, 0x01, }; =20 static int qcom_edp_phy_init(struct phy *phy) @@ -226,6 +242,10 @@ static int qcom_edp_phy_init(struct phy *phy) =20 memcpy(aux_cfg, edp->cfg->aux_cfg, sizeof(aux_cfg)); =20 + ret =3D edp->cfg->ver_ops->com_clk_fwd_cfg(edp); + if (ret) + return ret; + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, edp->edp + DP_PHY_PD_CTL); @@ -345,22 +365,22 @@ static int qcom_edp_set_vco_div(const struct qcom_edp= *edp, unsigned long *pixel =20 switch (dp_opts->link_rate) { case 1620: - vco_div =3D 0x1; + vco_div =3D edp->cfg->vco_div_cfg[0]; *pixel_freq =3D 1620000000UL / 2; break; =20 case 2700: - vco_div =3D 0x1; + vco_div =3D edp->cfg->vco_div_cfg[1]; *pixel_freq =3D 2700000000UL / 2; break; =20 case 5400: - vco_div =3D 0x2; + vco_div =3D edp->cfg->vco_div_cfg[2]; *pixel_freq =3D 5400000000UL / 4; break; =20 case 8100: - vco_div =3D 0x0; + vco_div =3D edp->cfg->vco_div_cfg[3]; *pixel_freq =3D 8100000000UL / 6; break; =20 @@ -398,6 +418,11 @@ static int qcom_edp_phy_com_resetsm_cntrl_v4(const str= uct qcom_edp *edp) val, val & BIT(0), 500, 10000); } =20 +static int qcom_edp_com_clk_fwd_cfg_v4(const struct qcom_edp *edp) +{ + return 0; +} + static int qcom_edp_com_bias_en_clkbuflr_v4(const struct qcom_edp *edp) { /* Turn on BIAS current for PHY/PLL */ @@ -530,6 +555,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 =3D= { .com_power_on =3D qcom_edp_phy_power_on_v4, .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v4, .com_bias_en_clkbuflr =3D qcom_edp_com_bias_en_clkbuflr_v4, + .com_clk_fwd_cfg =3D qcom_edp_com_clk_fwd_cfg_v4, .com_configure_pll =3D qcom_edp_com_configure_pll_v4, .com_configure_ssc =3D qcom_edp_com_configure_ssc_v4, }; @@ -537,17 +563,20 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 = =3D { static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg =3D { .is_edp =3D false, .aux_cfg =3D edp_phy_aux_cfg_v5, + .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v5, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, + .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, + .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; @@ -555,6 +584,7 @@ static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cf= g =3D { static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg =3D { .is_edp =3D true, .aux_cfg =3D edp_phy_aux_cfg_v4, + .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; @@ -734,10 +764,190 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v6 = =3D { =20 static struct qcom_edp_phy_cfg x1e80100_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, + .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v6, }; =20 +static int qcom_edp_com_configure_ssc_v8(const struct qcom_edp *edp) +{ + const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; + u32 step1; + u32 step2; + + switch (dp_opts->link_rate) { + case 1620: + case 2700: + case 8100: + step1 =3D 0x5b; + step2 =3D 0x02; + break; + + case 5400: + step1 =3D 0x5b; + step2 =3D 0x02; + break; + + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + + writel(0x01, edp->pll + DP_QSERDES_V8_COM_SSC_EN_CENTER); + writel(0x00, edp->pll + DP_QSERDES_V8_COM_SSC_ADJ_PER1); + writel(0x6b, edp->pll + DP_QSERDES_V8_COM_SSC_PER1); + writel(0x02, edp->pll + DP_QSERDES_V8_COM_SSC_PER2); + writel(step1, edp->pll + DP_QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0); + writel(step2, edp->pll + DP_QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0); + + return 0; +} + +static int qcom_edp_com_configure_pll_v8(const struct qcom_edp *edp) +{ + const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; + u32 div_frac_start2_mode0; + u32 div_frac_start3_mode0; + u32 dec_start_mode0; + u32 lock_cmp1_mode0; + u32 lock_cmp2_mode0; + u32 code1_mode0; + u32 code2_mode0; + u32 hsclk_sel; + + switch (dp_opts->link_rate) { + case 1620: + hsclk_sel =3D 0x5; + dec_start_mode0 =3D 0x34; + div_frac_start2_mode0 =3D 0xc0; + div_frac_start3_mode0 =3D 0x0b; + lock_cmp1_mode0 =3D 0x37; + lock_cmp2_mode0 =3D 0x04; + code1_mode0 =3D 0x71; + code2_mode0 =3D 0x0c; + break; + + case 2700: + hsclk_sel =3D 0x3; + dec_start_mode0 =3D 0x34; + div_frac_start2_mode0 =3D 0xc0; + div_frac_start3_mode0 =3D 0x0b; + lock_cmp1_mode0 =3D 0x07; + lock_cmp2_mode0 =3D 0x07; + code1_mode0 =3D 0x71; + code2_mode0 =3D 0x0c; + break; + + case 5400: + case 8100: + hsclk_sel =3D 0x2; + dec_start_mode0 =3D 0x4f; + div_frac_start2_mode0 =3D 0xa0; + div_frac_start3_mode0 =3D 0x01; + lock_cmp1_mode0 =3D 0x18; + lock_cmp2_mode0 =3D 0x15; + code1_mode0 =3D 0x14; + code2_mode0 =3D 0x25; + break; + + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + + writel(0x01, edp->pll + DP_QSERDES_V8_COM_SVS_MODE_CLK_SEL); + writel(0x3b, edp->pll + DP_QSERDES_V8_COM_SYSCLK_EN_SEL); + writel(0x02, edp->pll + DP_QSERDES_V8_COM_SYS_CLK_CTRL); + writel(0x0c, edp->pll + DP_QSERDES_V8_COM_CLK_ENABLE1); + writel(0x06, edp->pll + DP_QSERDES_V8_COM_SYSCLK_BUF_ENABLE); + writel(0x30, edp->pll + DP_QSERDES_V8_COM_CLK_SELECT); + writel(hsclk_sel, edp->pll + DP_QSERDES_V8_COM_HSCLK_SEL_1); + writel(0x07, edp->pll + DP_QSERDES_V8_COM_PLL_IVCO); + writel(0x00, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP_EN); + writel(0x36, edp->pll + DP_QSERDES_V8_COM_PLL_CCTRL_MODE0); + writel(0x16, edp->pll + DP_QSERDES_V8_COM_PLL_RCTRL_MODE0); + writel(0x06, edp->pll + DP_QSERDES_V8_COM_CP_CTRL_MODE0); + writel(dec_start_mode0, edp->pll + DP_QSERDES_V8_COM_DEC_START_MODE0); + writel(0x00, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START1_MODE0); + writel(div_frac_start2_mode0, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START= 2_MODE0); + writel(div_frac_start3_mode0, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START= 3_MODE0); + writel(0x96, edp->pll + DP_QSERDES_V8_COM_CMN_CONFIG_1); + writel(0x3f, edp->pll + DP_QSERDES_V8_COM_INTEGLOOP_GAIN0_MODE0); + writel(0x00, edp->pll + DP_QSERDES_V8_COM_INTEGLOOP_GAIN1_MODE0); + writel(0x00, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE_MAP); + writel(lock_cmp1_mode0, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP1_MODE0); + writel(lock_cmp2_mode0, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP2_MODE0); + + writel(0x0a, edp->pll + DP_QSERDES_V8_COM_BG_TIMER); + writel(0x0a, edp->pll + DP_QSERDES_V8_COM_CORECLK_DIV_MODE0); + writel(0x00, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE_CTRL); + writel(0x1f, edp->pll + DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN); + writel(0x00, edp->pll + DP_QSERDES_V8_COM_CORE_CLK_EN); + writel(0xa0, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE1_MODE0); + writel(0x01, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE2_MODE0); + + writel(code1_mode0, edp->pll + DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MOD= E0); + writel(code2_mode0, edp->pll + DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MOD= E0); + + return 0; +} + + +static int qcom_edp_phy_com_resetsm_cntrl_v8(const struct qcom_edp *edp) +{ + u32 val; + + writel(0x20, edp->pll + DP_QSERDES_V8_COM_RESETSM_CNTRL); + + return readl_poll_timeout(edp->pll + DP_QSERDES_V8_COM_C_READY_STATUS, + val, val & BIT(0), 500, 10000); +} + +static int qcom_edp_com_clk_fwd_cfg_v8(const struct qcom_edp *edp) +{ + writel(0x3f, edp->pll + DP_QSERDES_V8_COM_CLK_FWD_CONFIG_1); + + return 0; +} + +static int qcom_edp_com_bias_en_clkbuflr_v8(const struct qcom_edp *edp) +{ + /* Turn on BIAS current for PHY/PLL */ + writel(0x1f, edp->pll + DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN); + + return 0; +} + +static int qcom_edp_phy_power_on_v8(const struct qcom_edp *edp) +{ + u32 val; + + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, + edp->edp + DP_PHY_PD_CTL); + writel(0xfc, edp->edp + DP_PHY_MODE); + + return readl_poll_timeout(edp->pll + DP_QSERDES_V8_COM_CMN_STATUS, + val, val & BIT(7), 5, 200); +} + +static const struct phy_ver_ops qcom_edp_phy_ops_v8 =3D { + .com_power_on =3D qcom_edp_phy_power_on_v8, + .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v8, + .com_bias_en_clkbuflr =3D qcom_edp_com_bias_en_clkbuflr_v8, + .com_clk_fwd_cfg =3D qcom_edp_com_clk_fwd_cfg_v8, + .com_configure_pll =3D qcom_edp_com_configure_pll_v8, + .com_configure_ssc =3D qcom_edp_com_configure_ssc_v8, +}; + +static struct qcom_edp_phy_cfg glymur_phy_cfg =3D { + .aux_cfg =3D edp_phy_aux_cfg_v8, + .vco_div_cfg =3D edp_phy_vco_div_cfg_v8, + .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v5, + .ver_ops =3D &qcom_edp_phy_ops_v8, +}; + static int qcom_edp_phy_power_on(struct phy *phy) { const struct qcom_edp *edp =3D phy_get_drvdata(phy); @@ -1133,6 +1343,7 @@ static int qcom_edp_phy_probe(struct platform_device = *pdev) } =20 static const struct of_device_id qcom_edp_phy_match_table[] =3D { + { .compatible =3D "qcom,glymur-dp-phy", .data =3D &glymur_phy_cfg, }, { .compatible =3D "qcom,sa8775p-edp-phy", .data =3D &sa8775p_dp_phy_cfg, = }, { .compatible =3D "qcom,sc7280-edp-phy", .data =3D &sc7280_dp_phy_cfg, }, { .compatible =3D "qcom,sc8180x-edp-phy", .data =3D &sc7280_dp_phy_cfg, }, --=20 2.48.1