From nobody Tue Feb 10 06:58:20 2026 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43FD1239E65; Wed, 24 Dec 2025 03:11:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766545919; cv=none; b=X5gc36y47V6XpXkWyBNlpVaH4QUa4wye54RIaNwm2ETI8LL1S1A/kcC+Bl734CmeX91C5ERm9cXB4gbEo+WEHkV39pLfsDzE4cT2yjlN797HEMhNd6ceepwnEjsS2Ur/lLTLJT328nNr3mTUT57d8UOoWChOoh06UBVhVRaxciM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766545919; c=relaxed/simple; bh=WwXeANpA9YYaTJ6gJICQ2qIW4t/9tLVyD85CjocgArQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=j+gUKhahOny+xd4T1eBhHNqiwitRsGGQpNimmS8OVtwN29RtjiDb7GUO/ckiQZ4ZN2Y12zsTRUpW9sBIsFf7y/3RlxXWMC4hl5FZFhXD3axgeFFWmrhUEzeCWNibT2KM0cVClOb4F2zz65dSPTyoNEh5/46qxwxSSU4833ciTgw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from [127.0.0.2] (unknown [114.241.82.59]) by APP-05 (Coremail) with SMTP id zQCowADHXBDPWUtpQzS6AQ--.32153S7; Wed, 24 Dec 2025 11:11:12 +0800 (CST) From: Vivian Wang Date: Wed, 24 Dec 2025 11:10:53 +0800 Subject: [PATCH RFC net-next 5/5] net: ionic: Set msi_addr_mask to IONIC_ADDR_LEN-bit everywhere Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251224-pci-msi-addr-mask-v1-5-05a6fcb4b4c0@iscas.ac.cn> References: <20251224-pci-msi-addr-mask-v1-0-05a6fcb4b4c0@iscas.ac.cn> In-Reply-To: <20251224-pci-msi-addr-mask-v1-0-05a6fcb4b4c0@iscas.ac.cn> To: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , David Airlie , Simona Vetter , Brett Creeley , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bjorn Helgaas , Jaroslav Kysela , Takashi Iwai Cc: Han Gao , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, netdev@vger.kernel.org, linux-pci@vger.kernel.org, linux-sound@vger.kernel.org, Vivian Wang X-Mailer: b4 0.14.3 X-CM-TRANSID: zQCowADHXBDPWUtpQzS6AQ--.32153S7 X-Coremail-Antispam: 1UD129KBjvJXoW7tF4kXFWruF1rGF13GF15urg_yoW8WF1Dpa 98Ga4Iqr4rXryUGa1vyw4kZF98AayFkry5Wrn3Z3sa93sxtFy8tF17tF9xJ34UXrW8ua1S qFyjkw15XFn8Za7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmq14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE 3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2I x0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8 JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2 ka0xkIwI1lc7CjxVAaw2AFwI0_GFv_Wryl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Y z7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zV AF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1l IxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r 1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIY CTnIWIevJa73UjIFyTuYvjTRNdb1DUUUU X-CM-SenderInfo: pzdqw2pxlnt03j6l2u1dvotugofq/ The code was originally written using no_64bit_msi, which restricts the device to 32-bit MSI addresses. Since msi_addr_mask is introduced, use DMA_BIT_MASK(IONIC_ADDR_LEN) instead of DMA_BIT_MASK(32) here for msi_addr_mask, describing the restriction more precisely and allowing these devices to work on platforms with MSI doorbell address above 32-bit space, as long as it is within the hardware's addressable space. Also remove #ifdef CONFIG_PPC64 wrapped around it, since this is a hardware restriction and not a platform one. Signed-off-by: Vivian Wang --- RFC because net-next is closed pensando maintainers: I don't know if this is the actual restriction, and do not have any Pensando device to test this. Please help with checking this. Thanks. --- drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/= net/ethernet/pensando/ionic/ionic_bus_pci.c index 0671deae9a28..16133537c535 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c +++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c @@ -329,10 +329,8 @@ static int ionic_probe(struct pci_dev *pdev, const str= uct pci_device_id *ent) goto err_out; } =20 -#ifdef CONFIG_PPC64 /* Ensure MSI/MSI-X interrupts lie within addressable physical memory */ - pdev->msi_addr_mask =3D DMA_BIT_MASK(32); -#endif + pdev->msi_addr_mask =3D DMA_BIT_MASK(IONIC_ADDR_LEN); =20 err =3D ionic_setup_one(ionic); if (err) --=20 2.51.2