From nobody Mon Feb 9 19:08:57 2026 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 421E61EB5F8; Wed, 24 Dec 2025 03:11:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766545920; cv=none; b=pZ7H/g0qAtuRp8yZfoN17UtUdgmH5/nIU9m+2H8xZyepXrU1DSN7NBMyGVRceeUzBl4CK9gwHO8DcLkViZxDxGPhR08yv4gXOsvZb7Qw+jPF3F3+MpBhmno4jK514YLLQp2wdJeySGhEE9i2QtuUHRs4YEYlwm3C4/6qEzZKxoI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766545920; c=relaxed/simple; bh=0wKZOu3lF9zOV14ugyFXxa+Qz/FG4KrIvzxt8fO3Y3I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RX+6ofZA5/IEUQDmrz4hHf+VTN9lP77NvIv6dFonfEUJSzIIRVllQsXptLU9GmoicTxLrS6RepRQ6fbEPhff/IBOL9a2EGfDl0jiXwHWngiuw6pONRgFU82I6rdjjTmkzARH4LujMM4prkp9w4oY9Cf2krmmsydohjH+2sRe1Mg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from [127.0.0.2] (unknown [114.241.82.59]) by APP-05 (Coremail) with SMTP id zQCowADHXBDPWUtpQzS6AQ--.32153S3; Wed, 24 Dec 2025 11:11:12 +0800 (CST) From: Vivian Wang Date: Wed, 24 Dec 2025 11:10:49 +0800 Subject: [PATCH 1/5] PCI/MSI: Conservatively generalize no_64bit_msi into msi_addr_mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251224-pci-msi-addr-mask-v1-1-05a6fcb4b4c0@iscas.ac.cn> References: <20251224-pci-msi-addr-mask-v1-0-05a6fcb4b4c0@iscas.ac.cn> In-Reply-To: <20251224-pci-msi-addr-mask-v1-0-05a6fcb4b4c0@iscas.ac.cn> To: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , David Airlie , Simona Vetter , Brett Creeley , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bjorn Helgaas , Jaroslav Kysela , Takashi Iwai Cc: Han Gao , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, netdev@vger.kernel.org, linux-pci@vger.kernel.org, linux-sound@vger.kernel.org, Vivian Wang X-Mailer: b4 0.14.3 X-CM-TRANSID: zQCowADHXBDPWUtpQzS6AQ--.32153S3 X-Coremail-Antispam: 1UD129KBjvJXoWxtF1rArWkZFyUJFWxKF15Arb_yoW3Gw4rpa yDCFWfKrWrK34UJayqy3WUZF13Xan093yfWrWUK3sa93ZIvFyUXFn7try3Jwn7XrsrCF1a qFyUKw4UWFnxX3JanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmY14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2 xKxwCY1x0262kKe7AKxVW8ZVWrXwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWU JVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67 kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY 6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42 IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIev Ja73UjIFyTuYvjTRMfOzDUUUU X-CM-SenderInfo: pzdqw2pxlnt03j6l2u1dvotugofq/ Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but implement less than 64 address bits. This breaks on platforms where such a device is assigned an MSI address higher than what's reachable. Currently, we deal with this with a single no_64bit_msi flag, and (notably on powerpc) use 32-bit MSI address for these devices. However, on some platforms the MSI doorbell address is above 32-bit but within device ability. As a first step, conservatively generalize the single-bit flag no_64bit_msi into msi_addr_mask. (The name msi_addr_mask is chosen to avoid confusion with msi_mask.) The translation is essentially: - no_64bit_msi =3D 1 -> msi_addr_mask =3D DMA_BIT_MASK(32) - no_64bit_msi =3D 0 -> msi_addr_mask =3D DMA_BIT_MASK(64) - if (no_64bit_msi) -> if (msi_addr_mask < DMA_BIT_MASK(64)) Since no values other than DMA_BIT_MASK(32) and DMA_BIT_MASK(64) is used, no functional change is intended. Future patches that make use of intermediate values of msi_addr_mask will follow, allowing devices that cannot use full 64-bit addresses for MSI to work on platforms with MSI doorbell above 32-bit address space. Signed-off-by: Vivian Wang --- checkpatch complains about the comment include/linux/pci.h, which I have formatted similarly with other comments in the vicinity. --- arch/powerpc/platforms/powernv/pci-ioda.c | 2 +- arch/powerpc/platforms/pseries/msi.c | 4 ++-- drivers/gpu/drm/radeon/radeon_irq_kms.c | 2 +- drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c | 2 +- drivers/pci/msi/msi.c | 2 +- drivers/pci/msi/pcidev_msi.c | 2 +- drivers/pci/probe.c | 7 +++++++ include/linux/pci.h | 8 +++++++- sound/hda/controllers/intel.c | 2 +- 9 files changed, 22 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platf= orms/powernv/pci-ioda.c index b0c1d9d16fb5..1c78fdfb7b03 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -1666,7 +1666,7 @@ static int __pnv_pci_ioda_msi_setup(struct pnv_phb *p= hb, struct pci_dev *dev, return -ENXIO; =20 /* Force 32-bit MSI on some broken devices */ - if (dev->no_64bit_msi) + if (dev->msi_addr_mask < DMA_BIT_MASK(64)) is_64 =3D 0; =20 /* Assign XIVE to PE */ diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/= pseries/msi.c index a82aaa786e9e..7473c7ca1db0 100644 --- a/arch/powerpc/platforms/pseries/msi.c +++ b/arch/powerpc/platforms/pseries/msi.c @@ -383,7 +383,7 @@ static int rtas_prepare_msi_irqs(struct pci_dev *pdev, = int nvec_in, int type, */ again: if (type =3D=3D PCI_CAP_ID_MSI) { - if (pdev->no_64bit_msi) { + if (pdev->msi_addr_mask < DMA_BIT_MASK(64)) { rc =3D rtas_change_msi(pdn, RTAS_CHANGE_32MSI_FN, nvec); if (rc < 0) { /* @@ -409,7 +409,7 @@ static int rtas_prepare_msi_irqs(struct pci_dev *pdev, = int nvec_in, int type, if (use_32bit_msi_hack && rc > 0) rtas_hack_32bit_msi_gen2(pdev); } else { - if (pdev->no_64bit_msi) + if (pdev->msi_addr_mask < DMA_BIT_MASK(64)) rc =3D rtas_change_msi(pdn, RTAS_CHANGE_32MSIX_FN, nvec); else rc =3D rtas_change_msi(pdn, RTAS_CHANGE_MSIX_FN, nvec); diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/rade= on/radeon_irq_kms.c index 9961251b44ba..d550554a6f3f 100644 --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c +++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c @@ -252,7 +252,7 @@ static bool radeon_msi_ok(struct radeon_device *rdev) */ if (rdev->family < CHIP_BONAIRE) { dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n"); - rdev->pdev->no_64bit_msi =3D 1; + rdev->pdev->msi_addr_mask =3D DMA_BIT_MASK(32); } =20 /* force MSI on */ diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/= net/ethernet/pensando/ionic/ionic_bus_pci.c index 70d86c5f52fb..0671deae9a28 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c +++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c @@ -331,7 +331,7 @@ static int ionic_probe(struct pci_dev *pdev, const stru= ct pci_device_id *ent) =20 #ifdef CONFIG_PPC64 /* Ensure MSI/MSI-X interrupts lie within addressable physical memory */ - pdev->no_64bit_msi =3D 1; + pdev->msi_addr_mask =3D DMA_BIT_MASK(32); #endif =20 err =3D ionic_setup_one(ionic); diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c index 34d664139f48..48f5f03d1479 100644 --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -322,7 +322,7 @@ static int msi_verify_entries(struct pci_dev *dev) { struct msi_desc *entry; =20 - if (!dev->no_64bit_msi) + if (dev->msi_addr_mask =3D=3D DMA_BIT_MASK(64)) return 0; =20 msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) { diff --git a/drivers/pci/msi/pcidev_msi.c b/drivers/pci/msi/pcidev_msi.c index 5520aff53b56..0b0346813092 100644 --- a/drivers/pci/msi/pcidev_msi.c +++ b/drivers/pci/msi/pcidev_msi.c @@ -24,7 +24,7 @@ void pci_msi_init(struct pci_dev *dev) } =20 if (!(ctrl & PCI_MSI_FLAGS_64BIT)) - dev->no_64bit_msi =3D 1; + dev->msi_addr_mask =3D DMA_BIT_MASK(32); } =20 void pci_msix_init(struct pci_dev *dev) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 41183aed8f5d..a2bff57176a3 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2047,6 +2047,13 @@ int pci_setup_device(struct pci_dev *dev) */ dev->dma_mask =3D 0xffffffff; =20 + /* + * Assume 64-bit addresses for MSI initially. Will be changed to 32-bit + * if MSI (rather than MSI-X) capability does not have + * PCI_MSI_FLAGS_64BIT. Can also be overridden by driver. + */ + dev->msi_addr_mask =3D DMA_BIT_MASK(64); + dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); diff --git a/include/linux/pci.h b/include/linux/pci.h index 864775651c6f..0fe32fef0331 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -377,6 +377,13 @@ struct pci_dev { 0xffffffff. You only need to change this if your device has broken DMA or supports 64-bit transfers. */ + u64 msi_addr_mask; /* Mask of the bits of bus address for + MSI that this device implements. + Normally set based on device + capabilities. You only need to + change this if your device claims + to support 64-bit MSI but implements + fewer than 64 address bits. */ =20 struct device_dma_parameters dma_parms; =20 @@ -441,7 +448,6 @@ struct pci_dev { =20 unsigned int is_busmaster:1; /* Is busmaster */ unsigned int no_msi:1; /* May not use MSI */ - unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ unsigned int block_cfg_access:1; /* Config space access blocked */ unsigned int broken_parity_status:1; /* Generates false positive parity */ unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c index 1e8e3d61291a..c9542ebdf7e2 100644 --- a/sound/hda/controllers/intel.c +++ b/sound/hda/controllers/intel.c @@ -1905,7 +1905,7 @@ static int azx_first_init(struct azx *chip) =20 if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { dev_dbg(card->dev, "Disabling 64bit MSI\n"); - pci->no_64bit_msi =3D true; + pci->msi_addr_mask =3D DMA_BIT_MASK(32); } =20 pci_set_master(pci); --=20 2.51.2 From nobody Mon Feb 9 19:08:57 2026 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDEF3239567; Wed, 24 Dec 2025 03:11:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766545919; cv=none; b=i3qQrXQ3aj/z8FmGO5+ndzkGeMny+aK3glaSHtr88s175MDq2hQuNndz9f71FOCOx/mn4L+0ELSaEz26WAwJcGQkdGyw1UVUIemQmcGc61K7PfiNBoNYc/MLVJzVv4CB+Pg2r0i3yYx1wvaXvaLjj7MbAaBgsBSDMuUpWNtyACo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766545919; c=relaxed/simple; bh=+phS86qLr1KOrIv1QFkRvEDvad88uZDH9wf8fLxXmUs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UuHbvR+wvatPqtMKttrEgclRdWYYtu8b331TH2yj5nHcw1vqcup+cuRKGlw4NgAi9nMfo2AUPjWG215NuRi3lIVzcCHIjjnQxPSqpUlhyT7nKPJDB/dW1csAqg6OM79N5kDwlVTSMJyI4eNqD72n/FRipJydvJ7aaTNTgD9Bu8I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from [127.0.0.2] (unknown [114.241.82.59]) by APP-05 (Coremail) with SMTP id zQCowADHXBDPWUtpQzS6AQ--.32153S4; Wed, 24 Dec 2025 11:11:12 +0800 (CST) From: Vivian Wang Date: Wed, 24 Dec 2025 11:10:50 +0800 Subject: [PATCH 2/5] PCI/MSI: Check msi_addr_mask in msi_verify_entries() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251224-pci-msi-addr-mask-v1-2-05a6fcb4b4c0@iscas.ac.cn> References: <20251224-pci-msi-addr-mask-v1-0-05a6fcb4b4c0@iscas.ac.cn> In-Reply-To: <20251224-pci-msi-addr-mask-v1-0-05a6fcb4b4c0@iscas.ac.cn> To: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , David Airlie , Simona Vetter , Brett Creeley , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bjorn Helgaas , Jaroslav Kysela , Takashi Iwai Cc: Han Gao , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, netdev@vger.kernel.org, linux-pci@vger.kernel.org, linux-sound@vger.kernel.org, Vivian Wang X-Mailer: b4 0.14.3 X-CM-TRANSID: zQCowADHXBDPWUtpQzS6AQ--.32153S4 X-Coremail-Antispam: 1UD129KBjvJXoW7uFy5JryfGw1kur43trWUurg_yoW8GrW8pF WqgayDAr4Fkw15JFsxXw10qF15ZFZ0qa4fGrW8G34Y9FsIv3W2yrnxKa47ta43XFy8Gw15 ZFyYyw4UWFs0yFJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmY14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2 xKxwCY1x0262kKe7AKxVW8ZVWrXwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWU JVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67 kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY 6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42 IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIev Ja73UjIFyTuYvjTRNiSHDUUUU X-CM-SenderInfo: pzdqw2pxlnt03j6l2u1dvotugofq/ Instead of a 32-bit/64-bit dichotomy, check the MSI address against msi_addr_mask. This allows platforms with MSI doorbell above 32-bit address space to work with devices without full 64-bit MSI address support, as long as the doorbell is within addressable range of MSI of the device. Signed-off-by: Vivian Wang --- drivers/pci/msi/msi.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c index 48f5f03d1479..2ecbcd6c436a 100644 --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -321,14 +321,17 @@ static int msi_setup_msi_desc(struct pci_dev *dev, in= t nvec, static int msi_verify_entries(struct pci_dev *dev) { struct msi_desc *entry; + u64 address; =20 if (dev->msi_addr_mask =3D=3D DMA_BIT_MASK(64)) return 0; =20 msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) { - if (entry->msg.address_hi) { - pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only = supports 32 bits\n", - entry->msg.address_hi, entry->msg.address_lo); + address =3D (u64)entry->msg.address_hi << 32 | + entry->msg.address_lo; + if (address & ~dev->msi_addr_mask) { + pci_err(dev, "arch assigned 64-bit MSI address %llx above device MSI ad= dress mask %llx\n", + address, dev->msi_addr_mask); break; } } --=20 2.51.2 From nobody Mon Feb 9 19:08:57 2026 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CFF922A813; Wed, 24 Dec 2025 03:11:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766545918; cv=none; b=EioBI5Ad4mWDzZNkY81AcJk+grNx0FVdkg8EXVoNLet7MUdTSGalwVjj1AOqACPGhZLyleTaUE1pVXEuqRyT6iOa5BKs/rRXSmnjDtELjYJnlzN5/uE1VKQUqu4qcJjpgvQm1Qr+Dpd5fNpS+GKFQTfL6087RtMorDjkg8Puo48= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766545918; c=relaxed/simple; bh=22WFEpVhx6O5d9AfQJ0a+wyuclxh8J0/RzaBW+QazLs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=idVbUrXzbuN6EueJ4SHccTjVW/rY/SClbB2EwqV6Jk3oLX8QvifFqmLbgvCY0hAaVYrKNhAnOAVexvEq/YeYoyX2kaApDecl3gkWzaMosAxazPSKVnfDFZ7NqFgx09IhcUmVZ6la+FkA+vHcW9lw1UWVacSWJMVPyEYqk3Ycszk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from [127.0.0.2] (unknown [114.241.82.59]) by APP-05 (Coremail) with SMTP id zQCowADHXBDPWUtpQzS6AQ--.32153S5; Wed, 24 Dec 2025 11:11:12 +0800 (CST) From: Vivian Wang Date: Wed, 24 Dec 2025 11:10:51 +0800 Subject: [PATCH 3/5] drm/radeon: Raise msi_addr_mask to 40 bits for pre-Bonaire Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251224-pci-msi-addr-mask-v1-3-05a6fcb4b4c0@iscas.ac.cn> References: <20251224-pci-msi-addr-mask-v1-0-05a6fcb4b4c0@iscas.ac.cn> In-Reply-To: <20251224-pci-msi-addr-mask-v1-0-05a6fcb4b4c0@iscas.ac.cn> To: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , David Airlie , Simona Vetter , Brett Creeley , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bjorn Helgaas , Jaroslav Kysela , Takashi Iwai Cc: Han Gao , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, netdev@vger.kernel.org, linux-pci@vger.kernel.org, linux-sound@vger.kernel.org, Vivian Wang X-Mailer: b4 0.14.3 X-CM-TRANSID: zQCowADHXBDPWUtpQzS6AQ--.32153S5 X-Coremail-Antispam: 1UD129KBjvJXoW7Wr1xWFW7JryDKr1UWrW7Jwb_yoW8JF1kpa 98Ca9xKrZIy34jka9rCa9rZF15Aa18KayrGrZrG3y3Ww1YyFyj9FZIvw17Jw1kXr1vgr4j vFy8Ga1rZF109FJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmI14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JrWl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJw A2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0x kIwI1lc7CjxVAaw2AFwI0_GFv_Wryl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_ Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1V AY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAI cVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMI IF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnI WIevJa73UjIFyTuYvjTRM6wCDUUUU X-CM-SenderInfo: pzdqw2pxlnt03j6l2u1dvotugofq/ The code was originally written using no_64bit_msi, which restricts the device to 32-bit MSI addresses. Since msi_addr_mask is introduced, use DMA_BIT_MASK(40) instead of DMA_BIT_MASK(32) here for msi_addr_mask, describing the restriction more precisely and allowing these devices to work on platforms with MSI doorbell address above 32-bit space, as long as it is within the hardware restriction of 40-bit space. Signed-off-by: Vivian Wang --- drivers/gpu/drm/radeon/radeon_irq_kms.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/rade= on/radeon_irq_kms.c index d550554a6f3f..ea519d43348b 100644 --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c +++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c @@ -251,8 +251,8 @@ static bool radeon_msi_ok(struct radeon_device *rdev) * IBM POWER servers, so we limit them */ if (rdev->family < CHIP_BONAIRE) { - dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n"); - rdev->pdev->msi_addr_mask =3D DMA_BIT_MASK(32); + dev_info(rdev->dev, "radeon: MSI limited to 40-bit\n"); + rdev->pdev->msi_addr_mask =3D DMA_BIT_MASK(40); } =20 /* force MSI on */ --=20 2.51.2 From nobody Mon Feb 9 19:08:57 2026 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A80D3235BE2; Wed, 24 Dec 2025 03:11:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766545919; cv=none; b=BEWQYqxg0k8vJURGPX/97wrzlnpog4t6yHQAXH3VoVaPWwysCsqT3djuAwFFXtf1yXOp2a9KG+9gM7G+YFtQpjE4iVqa2e2HFekj8k7eYoQdDxZiP/QGxdIr/Cw048SE+fS/wlmi3KydoRZiyPl56JwfgJHezPHGEDbiYNdfmtU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766545919; c=relaxed/simple; bh=GQKNg/ZNRV9PLitS2rcJTmU+JtRLIKr5Yw4LQ7lI4FU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EhXHgO9Quu0kxXplLdxiFLTFRK/B+QR+uJUOxL85/WK60QodQQz/XBsQZfIW0O/Vbnj8H/lBsLhQk/dSPkuJn4PPbxxkw3xW85dvWpLwpGhpexTz+B3iBQrz3YXkH1d66A10dM7wPEdcgNMLUVChx9shDUZOTb56tMud9gI6eF8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from [127.0.0.2] (unknown [114.241.82.59]) by APP-05 (Coremail) with SMTP id zQCowADHXBDPWUtpQzS6AQ--.32153S6; Wed, 24 Dec 2025 11:11:12 +0800 (CST) From: Vivian Wang Date: Wed, 24 Dec 2025 11:10:52 +0800 Subject: [PATCH 4/5] ALSA: hda/intel: Raise msi_addr_mask to dma_bits Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251224-pci-msi-addr-mask-v1-4-05a6fcb4b4c0@iscas.ac.cn> References: <20251224-pci-msi-addr-mask-v1-0-05a6fcb4b4c0@iscas.ac.cn> In-Reply-To: <20251224-pci-msi-addr-mask-v1-0-05a6fcb4b4c0@iscas.ac.cn> To: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , David Airlie , Simona Vetter , Brett Creeley , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bjorn Helgaas , Jaroslav Kysela , Takashi Iwai Cc: Han Gao , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, netdev@vger.kernel.org, linux-pci@vger.kernel.org, linux-sound@vger.kernel.org, Vivian Wang X-Mailer: b4 0.14.3 X-CM-TRANSID: zQCowADHXBDPWUtpQzS6AQ--.32153S6 X-Coremail-Antispam: 1UD129KBjvJXoW7tF4kGw13tw4DtFWDKFyrXrb_yoW8Ar45pw 4UGayftF1jqFyrJa1kKa1DZF13CFZYkwn8GrWrK34fCa4Yyr10gF9Fkr1xJa4xGF4vgw1Y vrWjv3W8WF45ZaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmq14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE 3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2I x0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8 JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2 ka0xkIwI1lc7CjxVAaw2AFwI0_GFv_Wryl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Y z7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zV AF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4l IxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r 1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIY CTnIWIevJa73UjIFyTuYvjTRNdb1DUUUU X-CM-SenderInfo: pzdqw2pxlnt03j6l2u1dvotugofq/ The code was originally written using no_64bit_msi, which restricts the device to 32-bit MSI addresses. Since msi_addr_mask is introduced, use DMA_BIT_MASK(dma_bits) instead of DMA_BIT_MASK(32) here for msi_addr_mask, describing the restriction more precisely and allowing these devices to work on platforms with MSI doorbell address above 32-bit space, as long as it is within the hardware's addressable space. Signed-off-by: Vivian Wang --- hda/intel maintainers: I don't know if this is the correct restriction. Please help with checking. Thanks. --- sound/hda/controllers/intel.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c index c9542ebdf7e2..a44de2306a2b 100644 --- a/sound/hda/controllers/intel.c +++ b/sound/hda/controllers/intel.c @@ -1903,11 +1903,6 @@ static int azx_first_init(struct azx *chip) chip->gts_present =3D true; #endif =20 - if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { - dev_dbg(card->dev, "Disabling 64bit MSI\n"); - pci->msi_addr_mask =3D DMA_BIT_MASK(32); - } - pci_set_master(pci); =20 gcap =3D azx_readw(chip, GCAP); @@ -1958,6 +1953,11 @@ static int azx_first_init(struct azx *chip) dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); dma_set_max_seg_size(&pci->dev, UINT_MAX); =20 + if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { + dev_dbg(card->dev, "Restricting MSI to %u-bit\n", dma_bits); + pci->msi_addr_mask =3D DMA_BIT_MASK(dma_bits); + } + /* read number of streams from GCAP register instead of using * hardcoded value */ --=20 2.51.2 From nobody Mon Feb 9 19:08:57 2026 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43FD1239E65; Wed, 24 Dec 2025 03:11:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766545919; cv=none; b=X5gc36y47V6XpXkWyBNlpVaH4QUa4wye54RIaNwm2ETI8LL1S1A/kcC+Bl734CmeX91C5ERm9cXB4gbEo+WEHkV39pLfsDzE4cT2yjlN797HEMhNd6ceepwnEjsS2Ur/lLTLJT328nNr3mTUT57d8UOoWChOoh06UBVhVRaxciM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766545919; c=relaxed/simple; bh=WwXeANpA9YYaTJ6gJICQ2qIW4t/9tLVyD85CjocgArQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=j+gUKhahOny+xd4T1eBhHNqiwitRsGGQpNimmS8OVtwN29RtjiDb7GUO/ckiQZ4ZN2Y12zsTRUpW9sBIsFf7y/3RlxXWMC4hl5FZFhXD3axgeFFWmrhUEzeCWNibT2KM0cVClOb4F2zz65dSPTyoNEh5/46qxwxSSU4833ciTgw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from [127.0.0.2] (unknown [114.241.82.59]) by APP-05 (Coremail) with SMTP id zQCowADHXBDPWUtpQzS6AQ--.32153S7; Wed, 24 Dec 2025 11:11:12 +0800 (CST) From: Vivian Wang Date: Wed, 24 Dec 2025 11:10:53 +0800 Subject: [PATCH RFC net-next 5/5] net: ionic: Set msi_addr_mask to IONIC_ADDR_LEN-bit everywhere Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251224-pci-msi-addr-mask-v1-5-05a6fcb4b4c0@iscas.ac.cn> References: <20251224-pci-msi-addr-mask-v1-0-05a6fcb4b4c0@iscas.ac.cn> In-Reply-To: <20251224-pci-msi-addr-mask-v1-0-05a6fcb4b4c0@iscas.ac.cn> To: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , David Airlie , Simona Vetter , Brett Creeley , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bjorn Helgaas , Jaroslav Kysela , Takashi Iwai Cc: Han Gao , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, netdev@vger.kernel.org, linux-pci@vger.kernel.org, linux-sound@vger.kernel.org, Vivian Wang X-Mailer: b4 0.14.3 X-CM-TRANSID: zQCowADHXBDPWUtpQzS6AQ--.32153S7 X-Coremail-Antispam: 1UD129KBjvJXoW7tF4kXFWruF1rGF13GF15urg_yoW8WF1Dpa 98Ga4Iqr4rXryUGa1vyw4kZF98AayFkry5Wrn3Z3sa93sxtFy8tF17tF9xJ34UXrW8ua1S qFyjkw15XFn8Za7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmq14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE 3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2I x0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8 JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2 ka0xkIwI1lc7CjxVAaw2AFwI0_GFv_Wryl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Y z7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zV AF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1l IxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r 1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIY CTnIWIevJa73UjIFyTuYvjTRNdb1DUUUU X-CM-SenderInfo: pzdqw2pxlnt03j6l2u1dvotugofq/ The code was originally written using no_64bit_msi, which restricts the device to 32-bit MSI addresses. Since msi_addr_mask is introduced, use DMA_BIT_MASK(IONIC_ADDR_LEN) instead of DMA_BIT_MASK(32) here for msi_addr_mask, describing the restriction more precisely and allowing these devices to work on platforms with MSI doorbell address above 32-bit space, as long as it is within the hardware's addressable space. Also remove #ifdef CONFIG_PPC64 wrapped around it, since this is a hardware restriction and not a platform one. Signed-off-by: Vivian Wang --- RFC because net-next is closed pensando maintainers: I don't know if this is the actual restriction, and do not have any Pensando device to test this. Please help with checking this. Thanks. --- drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/= net/ethernet/pensando/ionic/ionic_bus_pci.c index 0671deae9a28..16133537c535 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c +++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c @@ -329,10 +329,8 @@ static int ionic_probe(struct pci_dev *pdev, const str= uct pci_device_id *ent) goto err_out; } =20 -#ifdef CONFIG_PPC64 /* Ensure MSI/MSI-X interrupts lie within addressable physical memory */ - pdev->msi_addr_mask =3D DMA_BIT_MASK(32); -#endif + pdev->msi_addr_mask =3D DMA_BIT_MASK(IONIC_ADDR_LEN); =20 err =3D ionic_setup_one(ionic); if (err) --=20 2.51.2