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[2001:1c00:c32:7800:5bfa:a036:83f0:f9ec]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8037f0b12dsm1750304066b.48.2025.12.24.04.31.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Dec 2025 04:31:16 -0800 (PST) From: Hans de Goede Date: Wed, 24 Dec 2025 13:31:12 +0100 Subject: [PATCH v4 03/15] media: mt9m114: Use aptina-PLL helper to get PLL values Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251224-mt9m114-atomisp-v4-3-60b25da7a1bc@oss.qualcomm.com> References: <20251224-mt9m114-atomisp-v4-0-60b25da7a1bc@oss.qualcomm.com> In-Reply-To: <20251224-mt9m114-atomisp-v4-0-60b25da7a1bc@oss.qualcomm.com> To: Laurent Pinchart , Mauro Carvalho Chehab , Sakari Ailus Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Laurent Pinchart , Hans de Goede X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI0MDEwOSBTYWx0ZWRfX310IDDPjw+Rq 56nOc7tlZ5Hbp81M9yvSN9Y/iQy3p/+eXRtNZTnltOZ33sHzt1+u9XIx+ypTt7JbZLnIWKzGZiN k8ubJX2mCX88RuOvqo2E7B69EziYHVtgViw3VOSxMHeGxcm7Rie03H5p9booPboI4o93CSJwwTl 9i3JThdTzfsVLwkRmS0juUJmRZLAs1p2WT//g71u6lxgnq071VeJ7DnUpd1Nmf9yMnQtcUM5sT0 ZvbuaZqVbnioqNYOsP8ZVDX69yiL/Y4WA6dw0ZXuBhkGBsFs35SKFBo5wYrplqsJK5BN3gMUwgN FxDXNed1WZhtK2ZFUiKuSs0musBiN+3ZBM+FQXnpBpS2AlNfIqNlSvG8PvJ1Z5h1DLC7a04YrTP 9+fZu5AI4nUAM5BfIHkPGSWJINKaRacvurHxyW3Titmm7uArb3uJH5SWW5hINETGt5dD3+RnM0l YyPNDseqqyUQuw3kyJQ== X-Proofpoint-ORIG-GUID: OWyEcLqFN89k9vXuo9A-Y7red6szh3y_ X-Authority-Analysis: v=2.4 cv=WegBqkhX c=1 sm=1 tr=0 ts=694bdd16 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=P1BnusSwAAAA:8 a=EUspDBNiAAAA:8 a=HeJOk8pXgLY-FChRk_YA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 a=D0XLA9XvdZm18NrgonBM:22 X-Proofpoint-GUID: OWyEcLqFN89k9vXuo9A-Y7red6szh3y_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-24_03,2025-12-22_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 bulkscore=0 adultscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512240109 Before this change the driver used hardcoded PLL m, n and p values to achieve a 48MHz pixclock when used with an external clock with a frequency of 24 MHz. Use aptina_pll_calculate() to allow the driver to work with different external clock frequencies. The m, n, and p values will be unchanged with a 24 MHz extclk and this has also been tested with a 19.2 MHz clock where m gets increased from 32 to 40. Suggested-by: Laurent Pinchart Signed-off-by: Hans de Goede Reviewed-by: Laurent Pinchart --- Changes in v4: - After re-reading the docs out_clock_max should be 384MHz and P1 should always be 8, adjust the pll-limits accordingly and drop the comment about the out_clock_max from the documentation not working Changes in v3: - Document that using 768Mhz for out_clock_max does not work Changes in v2: - Add select VIDEO_APTINA_PLL to Kconfig - Use correct aptina_pll_limits --- drivers/media/i2c/Kconfig | 1 + drivers/media/i2c/mt9m114.c | 50 +++++++++++++++++++++++++++++++----------= ---- 2 files changed, 36 insertions(+), 15 deletions(-) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 4b4db8c4f49657e19018535927eb41f7ad2a4f80..befea5952191184536ad7d7e5c8= 1f567826d8aa7 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -305,6 +305,7 @@ config VIDEO_MT9M111 config VIDEO_MT9M114 tristate "onsemi MT9M114 sensor support" select V4L2_CCI_I2C + select VIDEO_APTINA_PLL help This is a Video4Linux2 sensor-level driver for the onsemi MT9M114 camera. diff --git a/drivers/media/i2c/mt9m114.c b/drivers/media/i2c/mt9m114.c index 51ebbe7ae996950a58f8fee30029e0a060feaf3f..d1635f49ee047ca696f6053f6c1= 7e30d736ab795 100644 --- a/drivers/media/i2c/mt9m114.c +++ b/drivers/media/i2c/mt9m114.c @@ -32,6 +32,8 @@ #include #include =20 +#include "aptina-pll.h" + /* Sysctl registers */ #define MT9M114_CHIP_ID CCI_REG16(0x0000) #define MT9M114_COMMAND_REGISTER CCI_REG16(0x0080) @@ -267,9 +269,9 @@ #define MT9M114_CAM_SYSCTL_PLL_ENABLE_VALUE BIT(0) #define MT9M114_CAM_SYSCTL_PLL_DISABLE_VALUE 0x00 #define MT9M114_CAM_SYSCTL_PLL_DIVIDER_M_N CCI_REG16(0xc980) -#define MT9M114_CAM_SYSCTL_PLL_DIVIDER_VALUE(m, n) (((n) << 8) | (m)) +#define MT9M114_CAM_SYSCTL_PLL_DIVIDER_VALUE(m, n) ((((n) - 1) << 8) | (m= )) #define MT9M114_CAM_SYSCTL_PLL_DIVIDER_P CCI_REG16(0xc982) -#define MT9M114_CAM_SYSCTL_PLL_DIVIDER_P_VALUE(p) ((p) << 8) +#define MT9M114_CAM_SYSCTL_PLL_DIVIDER_P_VALUE(p) (((p) - 1) << 8) #define MT9M114_CAM_PORT_OUTPUT_CONTROL CCI_REG16(0xc984) #define MT9M114_CAM_PORT_PORT_SELECT_PARALLEL (0 << 0) #define MT9M114_CAM_PORT_PORT_SELECT_MIPI (1 << 0) @@ -330,7 +332,7 @@ * minimum values that have been seen in register lists are 303 and 38, use * them. * - * Set the default to achieve 1280x960 at 30fps. + * Set the default to achieve 1280x960 at 30fps with a 48 MHz pixclock. */ #define MT9M114_MIN_HBLANK 303 #define MT9M114_MIN_VBLANK 38 @@ -340,6 +342,8 @@ #define MT9M114_DEF_FRAME_RATE 30 #define MT9M114_MAX_FRAME_RATE 120 =20 +#define MT9M114_DEF_PIXCLOCK 48000000 + #define MT9M114_PIXEL_ARRAY_WIDTH 1296U #define MT9M114_PIXEL_ARRAY_HEIGHT 976U =20 @@ -384,11 +388,7 @@ struct mt9m114 { struct v4l2_fwnode_endpoint bus_cfg; bool bypass_pll; =20 - struct { - unsigned int m; - unsigned int n; - unsigned int p; - } pll; + struct aptina_pll pll; =20 unsigned int pixrate; bool streaming; @@ -758,7 +758,7 @@ static int mt9m114_initialize(struct mt9m114 *sensor) sensor->pll.n), &ret); cci_write(sensor->regmap, MT9M114_CAM_SYSCTL_PLL_DIVIDER_P, - MT9M114_CAM_SYSCTL_PLL_DIVIDER_P_VALUE(sensor->pll.p), + MT9M114_CAM_SYSCTL_PLL_DIVIDER_P_VALUE(sensor->pll.p1), &ret); } =20 @@ -2283,12 +2283,25 @@ static int mt9m114_verify_link_frequency(struct mt9= m114 *sensor, =20 static int mt9m114_clk_init(struct mt9m114 *sensor) { + static const struct aptina_pll_limits limits =3D { + .ext_clock_min =3D 6000000, + .ext_clock_max =3D 54000000, + /* int_clock_* limits are not documented taken from mt9p031.c */ + .int_clock_min =3D 2000000, + .int_clock_max =3D 13500000, + /* out_clock_min is not documented, taken from mt9p031.c */ + .out_clock_min =3D 180000000, + .out_clock_max =3D 384000000, + .pix_clock_max =3D 48000000, + .n_min =3D 1, + .n_max =3D 64, + .m_min =3D 16, + .m_max =3D 192, + .p1_min =3D 8, + .p1_max =3D 8, + }; unsigned int pixrate; - - /* Hardcode the PLL multiplier and dividers to default settings. */ - sensor->pll.m =3D 32; - sensor->pll.n =3D 1; - sensor->pll.p =3D 7; + int ret; =20 /* * Calculate the pixel rate and link frequency. The CSI-2 bus is clocked @@ -2308,8 +2321,15 @@ static int mt9m114_clk_init(struct mt9m114 *sensor) } =20 /* Check if the PLL configuration fits the configured link frequency. */ + sensor->pll.ext_clock =3D clk_get_rate(sensor->clk); + sensor->pll.pix_clock =3D MT9M114_DEF_PIXCLOCK; + + ret =3D aptina_pll_calculate(&sensor->client->dev, &limits, &sensor->pll); + if (ret) + return ret; + pixrate =3D clk_get_rate(sensor->clk) * sensor->pll.m - / ((sensor->pll.n + 1) * (sensor->pll.p + 1)); + / (sensor->pll.n * sensor->pll.p1); if (mt9m114_verify_link_frequency(sensor, pixrate) =3D=3D 0) { sensor->pixrate =3D pixrate; sensor->bypass_pll =3D false; --=20 2.52.0