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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-59a1861f2e6sm5071562e87.69.2025.12.24.07.42.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Dec 2025 07:42:33 -0800 (PST) From: Dmitry Baryshkov Date: Wed, 24 Dec 2025 17:42:30 +0200 Subject: [PATCH v3 1/3] drm/msm/dpu: drop intr_start from DPU 3.x catalog files Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251224-mdp5-drop-dpu3-v3-1-fd7bb8546c30@oss.qualcomm.com> References: <20251224-mdp5-drop-dpu3-v3-0-fd7bb8546c30@oss.qualcomm.com> In-Reply-To: <20251224-mdp5-drop-dpu3-v3-0-fd7bb8546c30@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Alexey Minnekhanov , David Airlie , Simona Vetter , Alexey Minnekhanov Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3891; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=KGT0ib6f0S9x+W7J89kuc0HaNX2OlP5UrNenSreVEj4=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpTAnnziVXM9tBiur/oDhZRvJxxsxCPopAEmiGt 2MEGkk86pqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaUwJ5wAKCRCLPIo+Aiko 1d7bCACvxx6Jb0d3zC1nbjim5Ae8mQk1udJasKB08xZ0ijR08IxUFrmLeIaiubgxLVhcG4Kbnpv c22USuQpHqJHXMIXwmCfvDGpoQcGZSahvx1JIamkDA6Zx3hYZZrcJ3CWZbOeSwKEUWspVqO+QjD VKM2MF+2TKvxiC1/Ve0S3nQ62khUCnvzqvO5piQGtqiDZzEaxlffUTFSw8YZIxRzFlRE3uqCxGx KCNkZ3frm9K24UnpsnxOdN30Ca84DElh+CkljqsprUZw76UokPej3azZhkycGl5mht7YlvFeyUE KI5hck0RZ5iIzl6vKN/3mqYOjXjhuP14CmCpm+pj8svbxE49 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: -OobslQbj7BPEtqJsCY4wTfdz1AZALh2 X-Proofpoint-ORIG-GUID: -OobslQbj7BPEtqJsCY4wTfdz1AZALh2 X-Authority-Analysis: v=2.4 cv=QutTHFyd c=1 sm=1 tr=0 ts=694c09eb cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=-wdOMmJq3JXEukoY-DMA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI0MDEzOCBTYWx0ZWRfX0ErDB1Ndj8xO NuOjLEgQqIfeitXs9YlksoB8p261FQdcMKwP6TnRPteRSaby1q7IlGYDl1pbzpqZjy8WiF3eSDR WNQwySagsI30vi/Jgz6q3MQW5oOEaOzUxtvNhlX6Myq0hhdbmSLmKhMmgepZs8psuQnue6fbeEV 0gcFNq8X9avLqW1xIbkViLlGWd0yzKPWbH0SGprNTn1S/74BLD2a8G0KWnBwLuhOVUhFvvPmD62 IRakVzMG6SsKD6liREep+s/xUPVyypY817bTH9Suu+/6WAtAje95bBuT9NbcMN2Bdma5GZKYpAG Xn66Q/EMQeQfWup+3M49ydhmnVJWAzsg75S1ydZ55zuIzWf+XfBxYNSZUgclJLMvLEPOIyBxcSf /BHi/ByGuOcRROAdCQ3m9aX6gK62DAA8UXUox3EMr5y/s1T7S+xDY4ZVlVZswW9eSuxSpt8JSui hMQv7fAymBjqonQgBsw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-24_04,2025-12-22_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 bulkscore=0 impostorscore=0 spamscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512240138 DPU 3.x don't have separate intr_start interrupt, drop it from catalog files. Fixes: 94391a14fc27 ("drm/msm/dpu1: Add MSM8998 to hw catalog") Fixes: 7204df5e7e68 ("drm/msm/dpu: add support for SDM660 and SDM630 platfo= rms") Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 5 ----- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 5 ----- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 5 ----- 3 files changed, 15 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index f91220496082..b1b03d8b30fa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -42,24 +42,19 @@ static const struct dpu_ctl_cfg msm8998_ctl[] =3D { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x94, .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x1200, .len =3D 0x94, - .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x1400, .len =3D 0x94, .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x1600, .len =3D 0x94, - .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x1800, .len =3D 0x94, - .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h index 8f9a097147c0..64df4e80ea43 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h @@ -37,24 +37,19 @@ static const struct dpu_ctl_cfg sdm660_ctl[] =3D { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x94, .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x1200, .len =3D 0x94, - .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x1400, .len =3D 0x94, .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x1600, .len =3D 0x94, - .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x1800, .len =3D 0x94, - .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h index 0ad18bd273ff..b409af899918 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h @@ -36,24 +36,19 @@ static const struct dpu_ctl_cfg sdm630_ctl[] =3D { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x94, .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x1200, .len =3D 0x94, - .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x1400, .len =3D 0x94, .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x1600, .len =3D 0x94, - .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x1800, .len =3D 0x94, - .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, }; 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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-59a1861f2e6sm5071562e87.69.2025.12.24.07.42.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Dec 2025 07:42:34 -0800 (PST) From: Dmitry Baryshkov Date: Wed, 24 Dec 2025 17:42:31 +0200 Subject: [PATCH v3 2/3] drm/msm/dpu: fix CMD panels on DPU 1.x - 3.x Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251224-mdp5-drop-dpu3-v3-2-fd7bb8546c30@oss.qualcomm.com> References: <20251224-mdp5-drop-dpu3-v3-0-fd7bb8546c30@oss.qualcomm.com> In-Reply-To: <20251224-mdp5-drop-dpu3-v3-0-fd7bb8546c30@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Alexey Minnekhanov , David Airlie , Simona Vetter , Alexey Minnekhanov Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1402; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=/MJ75vhsI5cjj4o92iPu5gq8x/vgx9is2mnNAWB6edk=; b=kA0DAAoBizyKPgIpKNUByyZiAGlMCeehXSUbi4oIEysRtaTYV82kp6fPSKz0qxAudd3ZbyiHs IkBMwQAAQoAHRYhBExwhJVcsmNW8LiVf4s8ij4CKSjVBQJpTAnnAAoJEIs8ij4CKSjVpYUIAINc jhZ0GS07jX+JaZ6RIjwLf4EnHghhkF8Ljv25l2LrEhuGSLdFXOZJA5AizKoC6B5zSZITozzTGXF swym0Mwgf9NJGZn1cQniwIIocKxjfa4fwdPa4I3+1Si3afkSX20b/C8BSSOGXYVIM0tLGPJpJjg UIUVBnHgvOZpWYzJn84o6pmBJEh2TI4jui7i4GnyUAQadF6NPOZazfaPcw01PK9VmHofFFI1KQF 6ROzVGBiz88+cQSZgRHZZfCJYyxpSyBz07i7pnziU6lMZoI6AttT6Ah1MyyHyaZEPbocKIHJTy8 XsDFIEKuZSeqqeT06SrV+7vlyj493Xf+KrLRxFg= X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: xB4NFT72ytJYItsmQ5XzGIB_yZrzR-de X-Proofpoint-GUID: xB4NFT72ytJYItsmQ5XzGIB_yZrzR-de X-Authority-Analysis: v=2.4 cv=aOf9aL9m c=1 sm=1 tr=0 ts=694c09ec cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=Gbw9aFdXAAAA:8 a=EUspDBNiAAAA:8 a=3DtPeeBlMjcqd2FmxTYA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 a=9vIz8raoGPyDa4jBFAYH:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI0MDEzOCBTYWx0ZWRfXyOObmhn0ISKM qc7SWnrpPBN9yfYIfgsqF2KGlEkPM5PORdj3fsrmHiKOd+jXYY+iRN8+FfegLCguVJqOb5E1yec 9/jzDlryd4hBw2lqaAWXYbmvFwpEjuLQ37KVTECxXj/Nn1wICRhxitq+3RjaDWyWosHu5S9G5s5 8gkT8aAf156BqyWzcq4s/6NSKpTzwmE5GQiaDWzo9aEg2EXpfpYBQetNaJTXL7QKWsrptgK4bJV MVRLDLTj0bzxE/u7UlsX14c7u5fmcVElDjaAz8lcjEkfKOmxtrf8hGLO2XyOK3Uqewbu7jFBKa0 nfGDnCJtlooz3Yfq2Ra2ot87jr7wzadkuiPage/ozAy2jXP9NndD26xVCztToA1OZMDudN7WXOl JQ/ngyWN6oAxvxsXFaZKlSJzSE1ZGCfEg/gKmfHjMZA0Hat4sxiPA3z9Uonsk72qxKYvc1/JqGw 0y2zv4Es/l8QMl+x9KA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-24_04,2025-12-22_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 suspectscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512240138 DPU units before 4.x don't have a separate CTL_START IRQ to mark the begin of the data transfer. In such a case, wait for the frame transfer to complete rather than trying to wait for the CTL_START interrupt (and obviously hitting the timeout). Fixes: 050770cbbd26 ("drm/msm/dpu: Fix timeout issues on command mode panel= s") Reported-by: Alexey Minnekhanov Closes: https://lore.kernel.org/r/8e1d33ff-d902-4ae9-9162-e00d17a5e6d1@post= marketos.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers= /gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 0ec6d67c7c70..4faed35f146b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -681,7 +681,8 @@ static int dpu_encoder_phys_cmd_wait_for_commit_done( if (!dpu_encoder_phys_cmd_is_master(phys_enc)) return 0; =20 - if (phys_enc->hw_ctl->ops.is_started(phys_enc->hw_ctl)) + if (!phys_enc->irq[INTR_IDX_CTL_START] || + phys_enc->hw_ctl->ops.is_started(phys_enc->hw_ctl)) return dpu_encoder_phys_cmd_wait_for_tx_complete(phys_enc); =20 return _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc); 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Support for them in the DPU driver is mature enough, so it's no longer sensible to keep them enabled in the MDP5 driver. Not to mention that MSM8998 never used an MDP5 compatible string. Drop support for the MDP5 3.x genration inside the MDP5 driver and migrate those to the DPU driver only. Note: this will break if one uses the DT generated before v6.3 as they had only the generic, "qcom,mdp5" compatible string for SDM630 and SDM660. However granted that we had two LTS releases inbetween I don't think it is an issue. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 314 ---------------------------= ---- drivers/gpu/drm/msm/msm_drv.c | 16 +- 2 files changed, 13 insertions(+), 317 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm= /disp/mdp5/mdp5_cfg.c index df464f7c05bf..69fef034d0df 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c @@ -1097,310 +1097,6 @@ static const struct mdp5_cfg_hw msm8937_config =3D { .max_clk =3D 320000000, }; =20 -static const struct mdp5_cfg_hw msm8998_config =3D { - .name =3D "msm8998", - .mdp =3D { - .count =3D 1, - .caps =3D MDP_CAP_DSC | - MDP_CAP_CDM | - MDP_CAP_SRC_SPLIT | - 0, - }, - .ctl =3D { - .count =3D 5, - .base =3D { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, - .flush_hw_mask =3D 0xf7ffffff, - }, - .pipe_vig =3D { - .count =3D 4, - .base =3D { 0x04000, 0x06000, 0x08000, 0x0a000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SCALE | - MDP_PIPE_CAP_CSC | - MDP_PIPE_CAP_DECIMATION | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_rgb =3D { - .count =3D 4, - .base =3D { 0x14000, 0x16000, 0x18000, 0x1a000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SCALE | - MDP_PIPE_CAP_DECIMATION | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_dma =3D { - .count =3D 2, /* driver supports max of 2 currently */ - .base =3D { 0x24000, 0x26000, 0x28000, 0x2a000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_cursor =3D { - .count =3D 2, - .base =3D { 0x34000, 0x36000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SW_PIX_EXT | - MDP_PIPE_CAP_CURSOR | - 0, - }, - - .lm =3D { - .count =3D 6, - .base =3D { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 }, - .instances =3D { - { .id =3D 0, .pp =3D 0, .dspp =3D 0, - .caps =3D MDP_LM_CAP_DISPLAY | - MDP_LM_CAP_PAIR, }, - { .id =3D 1, .pp =3D 1, .dspp =3D 1, - .caps =3D MDP_LM_CAP_DISPLAY, }, - { .id =3D 2, .pp =3D 2, .dspp =3D -1, - .caps =3D MDP_LM_CAP_DISPLAY | - MDP_LM_CAP_PAIR, }, - { .id =3D 3, .pp =3D -1, .dspp =3D -1, - .caps =3D MDP_LM_CAP_WB, }, - { .id =3D 4, .pp =3D -1, .dspp =3D -1, - .caps =3D MDP_LM_CAP_WB, }, - { .id =3D 5, .pp =3D 3, .dspp =3D -1, - .caps =3D MDP_LM_CAP_DISPLAY, }, - }, - .nb_stages =3D 8, - .max_width =3D 2560, - .max_height =3D 0xFFFF, - }, - .dspp =3D { - .count =3D 2, - .base =3D { 0x54000, 0x56000 }, - }, - .ad =3D { - .count =3D 3, - .base =3D { 0x78000, 0x78800, 0x79000 }, - }, - .pp =3D { - .count =3D 4, - .base =3D { 0x70000, 0x70800, 0x71000, 0x71800 }, - }, - .cdm =3D { - .count =3D 1, - .base =3D { 0x79200 }, - }, - .dsc =3D { - .count =3D 2, - .base =3D { 0x80000, 0x80400 }, - }, - .intf =3D { - .base =3D { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 }, - .connect =3D { - [0] =3D INTF_eDP, - [1] =3D INTF_DSI, - [2] =3D INTF_DSI, - [3] =3D INTF_HDMI, - }, - }, - .max_clk =3D 412500000, -}; - -static const struct mdp5_cfg_hw sdm630_config =3D { - .name =3D "sdm630", - .mdp =3D { - .count =3D 1, - .caps =3D MDP_CAP_CDM | - MDP_CAP_SRC_SPLIT | - 0, - }, - .ctl =3D { - .count =3D 5, - .base =3D { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, - .flush_hw_mask =3D 0xf4ffffff, - }, - .pipe_vig =3D { - .count =3D 1, - .base =3D { 0x04000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SCALE | - MDP_PIPE_CAP_CSC | - MDP_PIPE_CAP_DECIMATION | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_rgb =3D { - .count =3D 4, - .base =3D { 0x14000, 0x16000, 0x18000, 0x1a000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SCALE | - MDP_PIPE_CAP_DECIMATION | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_dma =3D { - .count =3D 2, /* driver supports max of 2 currently */ - .base =3D { 0x24000, 0x26000, 0x28000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_cursor =3D { - .count =3D 1, - .base =3D { 0x34000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SW_PIX_EXT | - MDP_PIPE_CAP_CURSOR | - 0, - }, - - .lm =3D { - .count =3D 2, - .base =3D { 0x44000, 0x46000 }, - .instances =3D { - { .id =3D 0, .pp =3D 0, .dspp =3D 0, - .caps =3D MDP_LM_CAP_DISPLAY | - MDP_LM_CAP_PAIR, }, - { .id =3D 1, .pp =3D 1, .dspp =3D -1, - .caps =3D MDP_LM_CAP_WB, }, - }, - .nb_stages =3D 8, - .max_width =3D 2048, - .max_height =3D 0xFFFF, - }, - .dspp =3D { - .count =3D 1, - .base =3D { 0x54000 }, - }, - .ad =3D { - .count =3D 2, - .base =3D { 0x78000, 0x78800 }, - }, - .pp =3D { - .count =3D 3, - .base =3D { 0x70000, 0x71000, 0x72000 }, - }, - .cdm =3D { - .count =3D 1, - .base =3D { 0x79200 }, - }, - .intf =3D { - .base =3D { 0x6a000, 0x6a800 }, - .connect =3D { - [0] =3D INTF_DISABLED, - [1] =3D INTF_DSI, - }, - }, - .max_clk =3D 412500000, -}; - -static const struct mdp5_cfg_hw sdm660_config =3D { - .name =3D "sdm660", - .mdp =3D { - .count =3D 1, - .caps =3D MDP_CAP_DSC | - MDP_CAP_CDM | - MDP_CAP_SRC_SPLIT | - 0, - }, - .ctl =3D { - .count =3D 5, - .base =3D { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, - .flush_hw_mask =3D 0xf4ffffff, - }, - .pipe_vig =3D { - .count =3D 2, - .base =3D { 0x04000, 0x6000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SCALE | - MDP_PIPE_CAP_CSC | - MDP_PIPE_CAP_DECIMATION | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_rgb =3D { - .count =3D 4, - .base =3D { 0x14000, 0x16000, 0x18000, 0x1a000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SCALE | - MDP_PIPE_CAP_DECIMATION | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_dma =3D { - .count =3D 2, /* driver supports max of 2 currently */ - .base =3D { 0x24000, 0x26000, 0x28000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_cursor =3D { - .count =3D 1, - .base =3D { 0x34000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SW_PIX_EXT | - MDP_PIPE_CAP_CURSOR | - 0, - }, - - .lm =3D { - .count =3D 4, - .base =3D { 0x44000, 0x45000, 0x46000, 0x49000 }, - .instances =3D { - { .id =3D 0, .pp =3D 0, .dspp =3D 0, - .caps =3D MDP_LM_CAP_DISPLAY | - MDP_LM_CAP_PAIR, }, - { .id =3D 1, .pp =3D 1, .dspp =3D 1, - .caps =3D MDP_LM_CAP_DISPLAY, }, - { .id =3D 2, .pp =3D 2, .dspp =3D -1, - .caps =3D MDP_LM_CAP_DISPLAY | - MDP_LM_CAP_PAIR, }, - { .id =3D 3, .pp =3D 3, .dspp =3D -1, - .caps =3D MDP_LM_CAP_WB, }, - }, - .nb_stages =3D 8, - .max_width =3D 2560, - .max_height =3D 0xFFFF, - }, - .dspp =3D { - .count =3D 2, - .base =3D { 0x54000, 0x56000 }, - }, - .ad =3D { - .count =3D 2, - .base =3D { 0x78000, 0x78800 }, - }, - .pp =3D { - .count =3D 5, - .base =3D { 0x70000, 0x70800, 0x71000, 0x71800, 0x72000 }, - }, - .cdm =3D { - .count =3D 1, - .base =3D { 0x79200 }, - }, - .dsc =3D { - .count =3D 2, - .base =3D { 0x80000, 0x80400 }, - }, - .intf =3D { - .base =3D { 0x6a000, 0x6a800, 0x6b000, 0x6b800 }, - .connect =3D { - [0] =3D INTF_DISABLED, - [1] =3D INTF_DSI, - [2] =3D INTF_DSI, - [3] =3D INTF_HDMI, - }, - }, - .max_clk =3D 412500000, -}; - static const struct mdp5_cfg_handler cfg_handlers_v1[] =3D { { .revision =3D 0, .config =3D { .hw =3D &msm8x74v1_config } }, { .revision =3D 1, .config =3D { .hw =3D &msm8x26_config } }, @@ -1416,12 +1112,6 @@ static const struct mdp5_cfg_handler cfg_handlers_v1= [] =3D { { .revision =3D 16, .config =3D { .hw =3D &msm8x53_config } }, }; =20 -static const struct mdp5_cfg_handler cfg_handlers_v3[] =3D { - { .revision =3D 0, .config =3D { .hw =3D &msm8998_config } }, - { .revision =3D 2, .config =3D { .hw =3D &sdm660_config } }, - { .revision =3D 3, .config =3D { .hw =3D &sdm630_config } }, -}; - const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *= cfg_handler) { return cfg_handler->config.hw; @@ -1455,10 +1145,6 @@ struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_k= ms *mdp5_kms, cfg_handlers =3D cfg_handlers_v1; num_handlers =3D ARRAY_SIZE(cfg_handlers_v1); break; - case 3: - cfg_handlers =3D cfg_handlers_v3; - num_handlers =3D ARRAY_SIZE(cfg_handlers_v3); - break; default: DRM_DEV_ERROR(dev->dev, "unexpected MDP major version: v%d.%d\n", major, minor); diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 7e977fec4100..abee7149a9e8 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -960,23 +960,33 @@ static bool prefer_mdp5 =3D true; MODULE_PARM_DESC(prefer_mdp5, "Select whether MDP5 or DPU driver should be= preferred"); module_param(prefer_mdp5, bool, 0444); =20 +/* list all platforms that have been migrated from mdp5 to dpu driver */ +static const char *const msm_mdp5_dpu_migrated[] =3D { + /* there never was qcom,msm8998-mdp5 */ + "qcom,sdm630-mdp5", + "qcom,sdm660-mdp5", + NULL +}; + /* list all platforms supported by both mdp5 and dpu drivers */ static const char *const msm_mdp5_dpu_migration[] =3D { "qcom,msm8917-mdp5", "qcom,msm8937-mdp5", "qcom,msm8953-mdp5", "qcom,msm8996-mdp5", - "qcom,sdm630-mdp5", - "qcom,sdm660-mdp5", NULL, }; =20 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver) { - /* If it is not an MDP5 device, do not try MDP5 driver */ + /* If it is not an MDP5 device, use DPU */ if (!of_device_is_compatible(dev->of_node, "qcom,mdp5")) return dpu_driver; =20 + /* If it is no longer supported by MDP5, use DPU */ + if (of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migrated)) + return dpu_driver; + /* If it is not in the migration list, use MDP5 */ if (!of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migration)) return !dpu_driver; --=20 2.47.3