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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-59a18618cf9sm5115105e87.57.2025.12.24.07.33.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Dec 2025 07:33:52 -0800 (PST) From: Dmitry Baryshkov Date: Wed, 24 Dec 2025 17:33:49 +0200 Subject: [PATCH v4 1/2] drm/msm/dpu: Set vsync source irrespective of mdp top support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251224-intf-fix-wd-v4-1-07a0926fafd2@oss.qualcomm.com> References: <20251224-intf-fix-wd-v4-0-07a0926fafd2@oss.qualcomm.com> In-Reply-To: <20251224-intf-fix-wd-v4-0-07a0926fafd2@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Teguh Sobirin Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2330; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=cYm0vhLoKqA2PBsfl+wS9rx0q7aHEWOFtDsgpCz+I9Q=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpTAferAB2TUEQ1WhDBlHehg6VFbE6pjSp/CfWP 7fjPuiPKdaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaUwH3gAKCRCLPIo+Aiko 1TKIB/9gCUDK2YB7407yFykOcDkHJk8KsO426K6fmECYOOTiCiVMsnp7zAT3st9H4z8ckEoiFtX PEz868HYa/toZJo0B3hKpw3FeSRV+qtvbzfQ3POlOG3cwtaBtOu2y5uVfHbnqzRL9xWNJQJYstK i1Dqhjv9u5H4nGBkad2tyeJ0X4HLvg8AnSYEAkDx7eBhvEDb7FmNvVZbZvEjvYIE8pfZxT5hKbe aOXla86xAepBu4NTqQHzorXof82UpmN/pVnDS4Fl3Yzv9zxEKobXAMkmKwd/MPwo8WvzXQLNHXB 67FFtXGPzrY0jlK4v3klbH4IJsdKL+nsUvSubIgqGu/YoLSx X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: oRuWQrblPmgC-hr7bzhiFDPo_d5MukTs X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI0MDEzNyBTYWx0ZWRfXwFp/fyhwHyc/ 1woSxY1g+Pln9VqlxFFw5LYQT1W3Yu7eohx1DGkPQpUPBZ5VfmqBtx0y4VgMi+/Yo6twVRhCKdo S93lpTIkzYfWQgpmGrjX3Wm70dgDuhfD75w8uBBVuen0HiS6V8MKtbHSwmW66KGV4P0AATDpm6a 7pBn1T16E0CuTR5RcpRh7IU3IcnW4aXrE1dGqxAn+PmDRvQignFQh0jlTWcjKCDL5rjQCaoA67E 8pOCP+3HA3e43+lOeLAIjPfcsGUB/TgzVRmBssIAXSmx1tWYUFQstLUOoLErfMMwxbHofTTZevy bC+ZgY9R/f3dj90iOQGbEABQY35zkUDy7YM0GjOxiuKTZf5HRJLQd7sgUMG4wtGYZ++2oA74lkv oxSGcTeQATu/xXUoNDyyGAszRnONnTkMx4Qu2FEa/XS2V/5zAVi1nry2J2pcxtRoaWt6RrKiYay yTo4OaM9K3HA3UZAUXQ== X-Authority-Analysis: v=2.4 cv=HqV72kTS c=1 sm=1 tr=0 ts=694c07e2 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=3fIW1a8P77-jr8MUMFIA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-ORIG-GUID: oRuWQrblPmgC-hr7bzhiFDPo_d5MukTs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-24_04,2025-12-22_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 suspectscore=0 malwarescore=0 bulkscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512240137 From: Teguh Sobirin Since DPU 5.x the vsync source TE setup is split between MDP TOP and INTF blocks. Currently all code to setup vsync_source is only exectued if MDP TOP implements the setup_vsync_source() callback. However on DPU >=3D 8.x this callback is not implemented, making DPU driver skip all vsync setup. Move the INTF part out of this condition, letting DPU driver to setup TE vsync selection on all new DPU devices. Signed-off-by: Teguh Sobirin Fixes: 2f69e5458447 ("drm/msm/dpu: skip watchdog timer programming through = TOP on >=3D SM8450") [DB: restored top->ops.setup_vsync_source call] Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index d1cfe81a3373..0482b2bb5a9e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -774,6 +774,9 @@ static void _dpu_encoder_update_vsync_source(struct dpu= _encoder_virt *dpu_enc, return; } =20 + /* Set vsync source irrespective of mdp top support */ + vsync_cfg.vsync_source =3D disp_info->vsync_source; + if (hw_mdptop->ops.setup_vsync_source) { for (i =3D 0; i < dpu_enc->num_phys_encs; i++) vsync_cfg.ppnumber[i] =3D dpu_enc->hw_pp[i]->idx; @@ -781,17 +784,15 @@ static void _dpu_encoder_update_vsync_source(struct d= pu_encoder_virt *dpu_enc, vsync_cfg.pp_count =3D dpu_enc->num_phys_encs; vsync_cfg.frame_rate =3D drm_mode_vrefresh(&dpu_enc->base.crtc->state->a= djusted_mode); =20 - vsync_cfg.vsync_source =3D disp_info->vsync_source; - hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); + } =20 - for (i =3D 0; i < dpu_enc->num_phys_encs; i++) { - phys_enc =3D dpu_enc->phys_encs[i]; + for (i =3D 0; i < dpu_enc->num_phys_encs; i++) { + phys_enc =3D dpu_enc->phys_encs[i]; =20 - if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel) - phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf, - vsync_cfg.vsync_source); - } + if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel) + phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf, + vsync_cfg.vsync_source); } } =20 --=20 2.47.3