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[88.207.15.53]) by smtp.googlemail.com with ESMTPSA id 41be03b00d2f7-c1e7cbfa619sm12567549a12.36.2025.12.23.12.21.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Dec 2025 12:21:52 -0800 (PST) From: Robert Marko To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, herbert@gondor.apana.org.au, davem@davemloft.net, vkoul@kernel.org, andi.shyti@kernel.org, lee@kernel.org, andrew+netdev@lunn.ch, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, linusw@kernel.org, Steen.Hegelund@microchip.com, daniel.machon@microchip.com, UNGLinuxDriver@microchip.com, olivia@selenic.com, radu_nicolae.pirea@upb.ro, richard.genoud@bootlin.com, gregkh@linuxfoundation.org, jirislaby@kernel.org, broonie@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, lars.povlsen@microchip.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, linux-clk@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko Subject: [PATCH v3 15/15] arm64: dts: microchip: add EV23X71A board Date: Tue, 23 Dec 2025 21:16:26 +0100 Message-ID: <20251223201921.1332786-16-robert.marko@sartura.hr> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251223201921.1332786-1-robert.marko@sartura.hr> References: <20251223201921.1332786-1-robert.marko@sartura.hr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Microchip EV23X71A is an LAN9696 based evaluation board. Signed-off-by: Robert Marko --- Changes in v2: * Split from SoC DTSI commit * Apply DTS coding style * Enclose array in i2c-mux * Alphanumericaly sort nodes * Change management port mode to RGMII-ID=20 arch/arm64/boot/dts/microchip/Makefile | 1 + .../boot/dts/microchip/lan9696-ev23x71a.dts | 757 ++++++++++++++++++ 2 files changed, 758 insertions(+) create mode 100644 arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts diff --git a/arch/arm64/boot/dts/microchip/Makefile b/arch/arm64/boot/dts/m= icrochip/Makefile index c6e0313eea0f..09d16fc1ce9a 100644 --- a/arch/arm64/boot/dts/microchip/Makefile +++ b/arch/arm64/boot/dts/microchip/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_LAN969X) +=3D lan9696-ev23x71a.dtb dtb-$(CONFIG_ARCH_SPARX5) +=3D sparx5_pcb125.dtb dtb-$(CONFIG_ARCH_SPARX5) +=3D sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb dtb-$(CONFIG_ARCH_SPARX5) +=3D sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb diff --git a/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts b/arch/arm6= 4/boot/dts/microchip/lan9696-ev23x71a.dts new file mode 100644 index 000000000000..435df455b078 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts @@ -0,0 +1,757 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; + +#include +#include +#include "lan9691.dtsi" + +/ { + model =3D "Microchip EV23X71A"; + compatible =3D "microchip,ev23x71a", "microchip,lan9696", "microchip,lan9= 691"; + + aliases { + serial0 =3D &usart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + gpio-restart { + compatible =3D "gpio-restart"; + gpios =3D <&gpio 60 GPIO_ACTIVE_LOW>; + open-source; + priority =3D <200>; + }; + + i2c-mux { + compatible =3D "i2c-mux-gpio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-parent =3D <&i2c3>; + idle-state =3D <0x8>; + mux-gpios =3D <&sgpio_out 0 1 GPIO_ACTIVE_HIGH>, + <&sgpio_out 0 2 GPIO_ACTIVE_HIGH>, + <&sgpio_out 0 3 GPIO_ACTIVE_HIGH>; + settle-time-us =3D <100>; + + i2c_sfp0: i2c@0 { + reg =3D <0x0>; + }; + + i2c_sfp1: i2c@1 { + reg =3D <0x1>; + }; + + i2c_sfp2: i2c@2 { + reg =3D <0x2>; + }; + + i2c_sfp3: i2c@3 { + reg =3D <0x3>; + }; + + i2c_poe: i2c@7 { + reg =3D <0x7>; + }; + }; + + leds { + compatible =3D "gpio-leds"; + + led-status { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&gpio 61 GPIO_ACTIVE_LOW>; + }; + + led-sfp1-green { + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <0>; + gpios =3D <&sgpio_out 6 0 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + + led-sfp1-yellow { + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <0>; + gpios =3D <&sgpio_out 6 1 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + + led-sfp2-green { + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <1>; + gpios =3D <&sgpio_out 7 0 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + + led-sfp2-yellow { + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <1>; + gpios =3D <&sgpio_out 7 1 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + + led-sfp3-green { + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <2>; + gpios =3D <&sgpio_out 8 0 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + + led-sfp3-yellow { + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <2>; + gpios =3D <&sgpio_out 8 1 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + + led-sfp4-green { + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <3>; + gpios =3D <&sgpio_out 9 0 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + + led-sfp4-yellow { + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <3>; + gpios =3D <&sgpio_out 9 1 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + }; + + mux-controller { + compatible =3D "gpio-mux"; + #mux-control-cells =3D <0>; + mux-gpios =3D <&sgpio_out 1 2 GPIO_ACTIVE_LOW>, + <&sgpio_out 1 3 GPIO_ACTIVE_LOW>; + }; + + sfp0: sfp0 { + compatible =3D "sff,sfp"; + i2c-bus =3D <&i2c_sfp0>; + tx-disable-gpios =3D <&sgpio_out 6 2 GPIO_ACTIVE_HIGH>; + los-gpios =3D <&sgpio_in 6 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios =3D <&sgpio_in 6 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios =3D <&sgpio_in 6 2 GPIO_ACTIVE_HIGH>; + }; + + sfp1: sfp1 { + compatible =3D "sff,sfp"; + i2c-bus =3D <&i2c_sfp1>; + tx-disable-gpios =3D <&sgpio_out 7 2 GPIO_ACTIVE_HIGH>; + los-gpios =3D <&sgpio_in 7 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios =3D <&sgpio_in 7 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios =3D <&sgpio_in 7 2 GPIO_ACTIVE_HIGH>; + }; + + sfp2: sfp2 { + compatible =3D "sff,sfp"; + i2c-bus =3D <&i2c_sfp2>; + tx-disable-gpios =3D <&sgpio_out 8 2 GPIO_ACTIVE_HIGH>; + los-gpios =3D <&sgpio_in 8 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios =3D <&sgpio_in 8 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios =3D <&sgpio_in 8 2 GPIO_ACTIVE_HIGH>; + }; + + sfp3: sfp3 { + compatible =3D "sff,sfp"; + i2c-bus =3D <&i2c_sfp3>; + tx-disable-gpios =3D <&sgpio_out 9 2 GPIO_ACTIVE_HIGH>; + los-gpios =3D <&sgpio_in 9 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios =3D <&sgpio_in 9 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios =3D <&sgpio_in 9 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio { + emmc_sd_pins: emmc-sd-pins { + /* eMMC_SD - CMD, CLK, D0, D1, D2, D3, D4, D5, D6, D7, RSTN */ + pins =3D "GPIO_14", "GPIO_15", "GPIO_16", "GPIO_17", + "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_21", + "GPIO_22", "GPIO_23", "GPIO_24"; + function =3D "emmc_sd"; + }; + + fan_pins: fan-pins { + pins =3D "GPIO_25", "GPIO_26"; + function =3D "fan"; + }; + + fc0_pins: fc0-pins { + pins =3D "GPIO_3", "GPIO_4"; + function =3D "fc"; + }; + + fc2_pins: fc2-pins { + pins =3D "GPIO_64", "GPIO_65", "GPIO_66"; + function =3D "fc"; + }; + + fc3_pins: fc3-pins { + pins =3D "GPIO_55", "GPIO_56"; + function =3D "fc"; + }; + + mdio_pins: mdio-pins { + pins =3D "GPIO_9", "GPIO_10"; + function =3D "miim"; + }; + + mdio_irq_pins: mdio-irq-pins { + pins =3D "GPIO_11"; + function =3D "miim_irq"; + }; + + sgpio_pins: sgpio-pins { + /* SCK, D0, D1, LD */ + pins =3D "GPIO_5", "GPIO_6", "GPIO_7", "GPIO_8"; + function =3D "sgpio_a"; + }; + + usb_ulpi_pins: usb-ulpi-pins { + pins =3D "GPIO_30", "GPIO_31", "GPIO_32", "GPIO_33", + "GPIO_34", "GPIO_35", "GPIO_36", "GPIO_37", + "GPIO_38", "GPIO_39", "GPIO_40", "GPIO_41"; + function =3D "usb_ulpi"; + }; + + usb_rst_pins: usb-rst-pins { + pins =3D "GPIO_12"; + function =3D "usb2phy_rst"; + }; + + usb_over_pins: usb-over-pins { + pins =3D "GPIO_13"; + function =3D "usb_over_detect"; + }; + + usb_power_pins: usb-power-pins { + pins =3D "GPIO_1"; + function =3D "usb_power"; + }; + + ptp_out_pins: ptp-out-pins { + pins =3D "GPIO_58"; + function =3D "ptpsync_4"; + }; + + ptp_ext_pins: ptp-ext-pins { + pins =3D "GPIO_59"; + function =3D "ptpsync_5"; + }; +}; + +&flx0 { + atmel,flexcom-mode =3D ; + status =3D "okay"; +}; + +&flx2 { + atmel,flexcom-mode =3D ; + status =3D "okay"; +}; + +&flx3 { + atmel,flexcom-mode =3D ; + status =3D "okay"; +}; + +&i2c3 { + pinctrl-0 =3D <&fc3_pins>; + pinctrl-names =3D "default"; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns =3D <35>; + i2c-sda-hold-time-ns =3D <1500>; + status =3D "okay"; +}; + +&mdio0 { + pinctrl-0 =3D <&mdio_pins>, <&mdio_irq_pins>; + pinctrl-names =3D "default"; + reset-gpios =3D <&gpio 62 GPIO_ACTIVE_LOW>; + status =3D "okay"; + + phy3: phy@3 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <3>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy4: phy@4 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <4>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy5: phy@5 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <5>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy6: phy@6 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <6>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy7: phy@7 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <7>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy8: phy@8 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <8>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy9: phy@9 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <9>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy10: phy@10 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <10>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy11: phy@11 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <11>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy12: phy@12 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <12>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy13: phy@13 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <13>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy14: phy@14 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <14>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy15: phy@15 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <15>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy16: phy@16 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <16>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy17: phy@17 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <17>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy18: phy@18 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <18>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy19: phy@19 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <19>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy20: phy@20 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <20>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy21: phy@21 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <21>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy22: phy@22 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <22>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy23: phy@23 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <23>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy24: phy@24 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <24>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy25: phy@25 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <25>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy26: phy@26 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <26>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy27: phy@27 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <27>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; +}; + +&serdes { + status =3D "okay"; +}; + +&sgpio { + pinctrl-0 =3D <&sgpio_pins>; + pinctrl-names =3D "default"; + microchip,sgpio-port-ranges =3D <0 1>, <6 9>; + status =3D "okay"; + + gpio@0 { + ngpios =3D <128>; + }; + gpio@1 { + ngpios =3D <128>; + }; +}; + +&spi2 { + pinctrl-0 =3D <&fc2_pins>; + pinctrl-names =3D "default"; + cs-gpios =3D <&gpio 63 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&switch { + pinctrl-0 =3D <&ptp_out_pins>, <&ptp_ext_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port0: port@0 { + reg =3D <0>; + phy-handle =3D <&phy4>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 0>; + microchip,bandwidth =3D <1000>; + }; + + port1: port@1 { + reg =3D <1>; + phy-handle =3D <&phy5>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 0>; + microchip,bandwidth =3D <1000>; + }; + + port2: port@2 { + reg =3D <2>; + phy-handle =3D <&phy6>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 0>; + microchip,bandwidth =3D <1000>; + }; + + port3: port@3 { + reg =3D <3>; + phy-handle =3D <&phy7>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 0>; + microchip,bandwidth =3D <1000>; + }; + + port4: port@4 { + reg =3D <4>; + phy-handle =3D <&phy8>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 1>; + microchip,bandwidth =3D <1000>; + }; + + port5: port@5 { + reg =3D <5>; + phy-handle =3D <&phy9>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 1>; + microchip,bandwidth =3D <1000>; + }; + + port6: port@6 { + reg =3D <6>; + phy-handle =3D <&phy10>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 1>; + microchip,bandwidth =3D <1000>; + }; + + port7: port@7 { + reg =3D <7>; + phy-handle =3D <&phy11>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 1>; + microchip,bandwidth =3D <1000>; + }; + + port8: port@8 { + reg =3D <8>; + phy-handle =3D <&phy12>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 2>; + microchip,bandwidth =3D <1000>; + }; + + port9: port@9 { + reg =3D <9>; + phy-handle =3D <&phy13>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 2>; + microchip,bandwidth =3D <1000>; + }; + + port10: port@10 { + reg =3D <10>; + phy-handle =3D <&phy14>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 2>; + microchip,bandwidth =3D <1000>; + }; + + port11: port@11 { + reg =3D <11>; + phy-handle =3D <&phy15>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 2>; + microchip,bandwidth =3D <1000>; + }; + + port12: port@12 { + reg =3D <12>; + phy-handle =3D <&phy16>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 3>; + microchip,bandwidth =3D <1000>; + }; + + port13: port@13 { + reg =3D <13>; + phy-handle =3D <&phy17>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 3>; + microchip,bandwidth =3D <1000>; + }; + + port14: port@14 { + reg =3D <14>; + phy-handle =3D <&phy18>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 3>; + microchip,bandwidth =3D <1000>; + }; + + port15: port@15 { + reg =3D <15>; + phy-handle =3D <&phy19>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 3>; + microchip,bandwidth =3D <1000>; + }; + + port16: port@16 { + reg =3D <16>; + phy-handle =3D <&phy20>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 4>; + microchip,bandwidth =3D <1000>; + }; + + port17: port@17 { + reg =3D <17>; + phy-handle =3D <&phy21>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 4>; + microchip,bandwidth =3D <1000>; + }; + + port18: port@18 { + reg =3D <18>; + phy-handle =3D <&phy22>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 4>; + microchip,bandwidth =3D <1000>; + }; + + port19: port@19 { + reg =3D <19>; + phy-handle =3D <&phy23>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 4>; + microchip,bandwidth =3D <1000>; + }; + + port20: port@20 { + reg =3D <20>; + phy-handle =3D <&phy24>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 5>; + microchip,bandwidth =3D <1000>; + }; + + port21: port@21 { + reg =3D <21>; + phy-handle =3D <&phy25>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 5>; + microchip,bandwidth =3D <1000>; + }; + + port22: port@22 { + reg =3D <22>; + phy-handle =3D <&phy26>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 5>; + microchip,bandwidth =3D <1000>; + }; + + port23: port@23 { + reg =3D <23>; + phy-handle =3D <&phy27>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 5>; + microchip,bandwidth =3D <1000>; + }; + + port24: port@24 { + reg =3D <24>; + phys =3D <&serdes 6>; + phy-mode =3D "10gbase-r"; + sfp =3D <&sfp0>; + managed =3D "in-band-status"; + microchip,bandwidth =3D <10000>; + microchip,sd-sgpio =3D <24>; + }; + + port25: port@25 { + reg =3D <25>; + phys =3D <&serdes 7>; + phy-mode =3D "10gbase-r"; + sfp =3D <&sfp1>; + managed =3D "in-band-status"; + microchip,bandwidth =3D <10000>; + microchip,sd-sgpio =3D <28>; + }; + + port26: port@26 { + reg =3D <26>; + phys =3D <&serdes 8>; + phy-mode =3D "10gbase-r"; + sfp =3D <&sfp2>; + managed =3D "in-band-status"; + microchip,bandwidth =3D <10000>; + microchip,sd-sgpio =3D <32>; + }; + + port27: port@27 { + reg =3D <27>; + phys =3D <&serdes 9>; + phy-mode =3D "10gbase-r"; + sfp =3D <&sfp3>; + managed =3D "in-band-status"; + microchip,bandwidth =3D <10000>; + microchip,sd-sgpio =3D <36>; + }; + + port29: port@29 { + reg =3D <29>; + phys =3D <&serdes 11>; + phy-handle =3D <&phy3>; + phy-mode =3D "rgmii-id"; + microchip,bandwidth =3D <1000>; + }; + }; +}; + +&tmon { + pinctrl-0 =3D <&fan_pins>; + pinctrl-names =3D "default"; +}; + +&usart0 { + pinctrl-0 =3D <&fc0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&usb { + pinctrl-0 =3D <&usb_ulpi_pins>, <&usb_rst_pins>, <&usb_over_pins>, <&usb_= power_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; --=20 2.52.0