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([2a02:2f04:620a:8300:4258:c40f:5faf:7af5]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47d192e88f5sm237921025e9.0.2025.12.23.05.50.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Dec 2025 05:50:51 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, biju.das.jz@bp.renesas.com, fabrizio.castro.jz@renesas.com, geert+renesas@glider.be, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH v6 8/8] dmaengine: sh: rz-dmac: Add device_{pause,resume}() callbacks Date: Tue, 23 Dec 2025 15:49:52 +0200 Message-ID: <20251223134952.460284-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251223134952.460284-1-claudiu.beznea.uj@bp.renesas.com> References: <20251223134952.460284-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add support for device_{pause, resume}() callbacks. These are required by the RZ/G2L SCIFA driver. Signed-off-by: Claudiu Beznea --- Changes in v6: - set CHCTRL_SETSUS for pause and CHCTRL_CLRSUS for resume - dropped read-modify-update approach for CHCTRL updates as the HW returns zero when reading CHCTRL - moved the read_poll_timeout_atomic() under spin lock to ensure avoid any races b/w pause and resume functionalities Changes in v5: - used suspend capability of the controller to pause/resume the transfers drivers/dma/sh/rz-dmac.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 44f0f72cbcf1..377bdd5c9425 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -135,10 +135,12 @@ struct rz_dmac { #define CHANNEL_8_15_COMMON_BASE 0x0700 =20 #define CHSTAT_ER BIT(4) +#define CHSTAT_SUS BIT(3) #define CHSTAT_EN BIT(0) =20 #define CHCTRL_CLRINTMSK BIT(17) #define CHCTRL_CLRSUS BIT(9) +#define CHCTRL_SETSUS BIT(8) #define CHCTRL_CLRTC BIT(6) #define CHCTRL_CLREND BIT(5) #define CHCTRL_CLRRQ BIT(4) @@ -827,6 +829,38 @@ static enum dma_status rz_dmac_tx_status(struct dma_ch= an *chan, return status; } =20 +static int rz_dmac_device_pause(struct dma_chan *chan) +{ + struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); + u32 val; + int ret; + + scoped_guard(spinlock_irqsave, &channel->vc.lock) { + rz_dmac_ch_writel(channel, CHCTRL_SETSUS, CHCTRL, 1); + ret =3D read_poll_timeout_atomic(rz_dmac_ch_readl, val, + (val & CHSTAT_SUS), 1, 1024, + false, channel, CHSTAT, 1); + } + + return ret; +} + +static int rz_dmac_device_resume(struct dma_chan *chan) +{ + struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); + u32 val; + int ret; + + scoped_guard(spinlock_irqsave, &channel->vc.lock) { + rz_dmac_ch_writel(channel, CHCTRL_CLRSUS, CHCTRL, 1); + ret =3D read_poll_timeout_atomic(rz_dmac_ch_readl, val, + !(val & CHSTAT_SUS), 1, 1024, + false, channel, CHSTAT, 1); + } + + return ret; +} + /* * -----------------------------------------------------------------------= ------ * IRQ handling @@ -1165,6 +1199,8 @@ static int rz_dmac_probe(struct platform_device *pdev) engine->device_terminate_all =3D rz_dmac_terminate_all; engine->device_issue_pending =3D rz_dmac_issue_pending; engine->device_synchronize =3D rz_dmac_device_synchronize; + engine->device_pause =3D rz_dmac_device_pause; + engine->device_resume =3D rz_dmac_device_resume; =20 engine->copy_align =3D DMAENGINE_ALIGN_1_BYTE; dma_set_max_seg_size(engine->dev, U32_MAX); --=20 2.43.0