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([2a02:2f04:620a:8300:4258:c40f:5faf:7af5]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47d192e88f5sm237921025e9.0.2025.12.23.05.50.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Dec 2025 05:50:43 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, biju.das.jz@bp.renesas.com, fabrizio.castro.jz@renesas.com, geert+renesas@glider.be, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH v6 3/8] dmaengine: sh: rz-dmac: Drop read of CHCTRL register Date: Tue, 23 Dec 2025 15:49:47 +0200 Message-ID: <20251223134952.460284-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251223134952.460284-1-claudiu.beznea.uj@bp.renesas.com> References: <20251223134952.460284-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The CHCTRL register has 11 bits that can be updated by software. The documentation for all these bits states the following: - A read operation results in 0 being read - Writing zero does not affect the operation All bits in the CHCTRL register accessible by software are set and clear bits. The documentation for the CLREND bit of CHCTRL states: Setting this bit to 1 can clear the END bit of the CHSTAT_n/nS register. Also, the DMA transfer end interrupt is cleared. An attempt to read this bit results in 0 being read. 1: Clears the END bit. 0: Does not affect the operation. Since writing zero to any bit in this register does not affect controller operation and reads always return zero, there is no need to perform read-modify-write accesses to set the CLREND bit. Drop the read of the CHCTRL register. Also, since setting the CLREND bit does not interact with other functionalities exposed through this register and only clears the END interrupt, there is no need to lock around this operation. Add a comment to document this. Signed-off-by: Claudiu Beznea --- Changes in v6: - none, this patch is new drivers/dma/sh/rz-dmac.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 818d1ef6f0bf..43a772e4478c 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -698,7 +698,7 @@ static void rz_dmac_irq_handle_channel(struct rz_dmac_c= han *channel) { struct dma_chan *chan =3D &channel->vc.chan; struct rz_dmac *dmac =3D to_rz_dmac(chan->device); - u32 chstat, chctrl; + u32 chstat; =20 chstat =3D rz_dmac_ch_readl(channel, CHSTAT, 1); if (chstat & CHSTAT_ER) { @@ -710,8 +710,11 @@ static void rz_dmac_irq_handle_channel(struct rz_dmac_= chan *channel) goto done; } =20 - chctrl =3D rz_dmac_ch_readl(channel, CHCTRL, 1); - rz_dmac_ch_writel(channel, chctrl | CHCTRL_CLREND, CHCTRL, 1); + /* + * No need to lock. This just clears the END interrupt. Writing + * zeros to CHCTRL is just ignored by HW. + */ + rz_dmac_ch_writel(channel, CHCTRL_CLREND, CHCTRL, 1); done: return; } --=20 2.43.0