From nobody Sat Feb 7 05:01:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 644721531C8; Tue, 23 Dec 2025 12:47:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766494068; cv=none; b=B/6NXyn4yB7nKkososT5VQx1AbYBbW8KXj+GWVfBI0oUofuBsXKxCJwmYkLq1beBFUQdP3Gie89bt7sH62GME1eH36JLiHjZQ0EM9hgckoU4sEW9OJW3a9ViUmd2w64A8XJ4Cf5AhRpeDZVrM4dzCx4wH4YFWDPhjR6lodiYtj0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766494068; c=relaxed/simple; bh=2MjDtfXLypEJRTDTl8IzvcRwXY4LSxBOkoiWuhZLK/c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=p0vtCqJi/eFoEoQ7FMr0FwSln6EyuveKIPeeOhQGghJbb0EBzkTxpS9HrYHQw5+ETZjTBFJrKYAYAyNKkLde3ahoI7RRkYXL2tjZMja68z7FrlUKyxwvyPMC4vzEYk7hn8EFnWROONEh8Y6cCVlO0K2f+V2WQCygXdgEuF8u9iU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=u/xMO7Nw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="u/xMO7Nw" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1E2EDC116C6; Tue, 23 Dec 2025 12:47:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1766494066; bh=2MjDtfXLypEJRTDTl8IzvcRwXY4LSxBOkoiWuhZLK/c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=u/xMO7Nw3t3IKgf7oRNo8bj7RH9qndcM/dAQAGbmZiPkooJ0K4tsMdl+JnfF1FmoU px3VoHsX5JNFtyIcOvePmF15TGIUSD90DN9EQ0sdmmq345AS69CX+KI7FEz6FEpG3q zNIDJKg9jWU7X/ArBmIuFsB1wZs6wNeA7R5p1p7ykjTaKei7TLSNn/b4iR8wb3W/wj fqc6ImWdPssVqoUjrok/PQ88iquzXfa/AERl89HenBCD7OVvAWG44AUOQIOel+BsEW AmV5Hspqhp3BgCCdpmE/mQikQwBQALq2sq4FSS5ccQ0uZt64MsBiJyWJZjcwWoyT2j D8g5SnmSMLvJA== From: Michael Walle To: Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Andrew Davis , Santosh Shilimkar , Michael Turquette , Stephen Boyd , Kevin Hilman , Randolph Sapp Cc: linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Michael Walle , Conor Dooley Subject: [PATCH v2 1/4] dt-bindings: gpu: img: Add AM62P SoC specific compatible Date: Tue, 23 Dec 2025 13:47:13 +0100 Message-ID: <20251223124729.2482877-2-mwalle@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251223124729.2482877-1-mwalle@kernel.org> References: <20251223124729.2482877-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The AM62P and the J722S features the same BXS-4 GPU as the J721S2. Add a new SoC specific compatible. Signed-off-by: Michael Walle Acked-by: Conor Dooley Reviewed-by: Matt Coster --- Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b= /Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 86ef68985317..a1f54dbae3f3 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -40,6 +40,7 @@ properties: - const: img,img-rogue - items: - enum: + - ti,am62p-gpu - ti,j721s2-gpu - const: img,img-bxs-4-64 - const: img,img-rogue @@ -100,6 +101,7 @@ allOf: contains: enum: - ti,am62-gpu + - ti,am62p-gpu - ti,j721s2-gpu then: properties: --=20 2.47.3 From nobody Sat Feb 7 05:01:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8AC5A1531C8; Tue, 23 Dec 2025 12:47:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766494072; cv=none; b=KwOu2foqgr1QNQD1ZQOZpaiP4wi3+hLjvYr5fYiU7L+5hqII4EkauALAoO1PFFVAzehozZfbnoQgGdFjvfkKzlWgvMaMTHuAfmkteOOdwqDqEfPmM3eYL1jokR6aifyvnCQIVhM5Bpsn57mzoxA8pblMpmeoTFeuOABYbRMJ0Rw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766494072; c=relaxed/simple; bh=jGxjXld3AbH/E5UJYH7bhKAG0w3LuU6IFlo/+lXXbyE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HExM/9C5oaSIPHGtwxTBQ7VoutbgR2/dMsxRYvunnMKIqZhJd4CzywxB5AxXv+6wXUk67s1Bt2JAt8u+FRyyP17COswXm4PGbKsBmaZWyEsDRiWuvB+YSskOYW7TA5R563hD471FoyMex45dKAykU3MepklTtFtSOadieAfZBIM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gXGBmVIJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gXGBmVIJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5616FC113D0; Tue, 23 Dec 2025 12:47:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1766494072; bh=jGxjXld3AbH/E5UJYH7bhKAG0w3LuU6IFlo/+lXXbyE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gXGBmVIJqJRkCum5iYNnqsEG2H0Wc1XPk6ECg093ArxZO7wPZ97xbuhNMuS1/finB RqaIel3Wh4AuUufa1fMGExYCHqqzuAqMjJq9eYEESh1IBMg9MQOFf08lj6BBFOHjqY EUWEL97hcYYLqpK/+q6gLOhGaNJjeRrOMUYqB8Kc4C7IPHuOaXqLijRFPRZB9Mp39g OeBoHAHsRMF//BwLTgi1YaqmwHdUhbZus0eV919cV/vYFuxWFmhGrpExeJu49Qoycb GsDPSX6Xl+eisCuUhTQUL3HUPYfaDmIJ8POccdzV+dYZOnPEz2BNWfW5rouqJsF5fc f4pNInq4ecxIg== From: Michael Walle To: Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Andrew Davis , Santosh Shilimkar , Michael Turquette , Stephen Boyd , Kevin Hilman , Randolph Sapp Cc: linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Michael Walle Subject: [PATCH v2 2/4] clk: keystone: don't cache clock rate Date: Tue, 23 Dec 2025 13:47:14 +0100 Message-ID: <20251223124729.2482877-3-mwalle@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251223124729.2482877-1-mwalle@kernel.org> References: <20251223124729.2482877-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The TISCI firmware will return 0 if the clock or consumer is not enabled although there is a stored value in the firmware. IOW a call to set rate will work but at get rate will always return 0 if the clock is disabled. The clk framework will try to cache the clock rate when it's requested by a consumer. If the clock or consumer is not enabled at that point, the cached value is 0, which is wrong. Thus, disable the cache altogether. Signed-off-by: Michael Walle Reviewed-by: Kevin Hilman Reviewed-by: Randolph Sapp Reviewed-by: Nishanth Menon --- drivers/clk/keystone/sci-clk.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c index 9d5071223f4c..0a1565fdbb3b 100644 --- a/drivers/clk/keystone/sci-clk.c +++ b/drivers/clk/keystone/sci-clk.c @@ -333,6 +333,14 @@ static int _sci_clk_build(struct sci_clk_provider *pro= vider, =20 init.ops =3D &sci_clk_ops; init.num_parents =3D sci_clk->num_parents; + + /* + * A clock rate query to the SCI firmware will return 0 if either the + * clock itself is disabled or the attached device/consumer is disabled. + * This makes it inherently unsuitable for the caching of the clk + * framework. + */ + init.flags =3D CLK_GET_RATE_NOCACHE; sci_clk->hw.init =3D &init; =20 ret =3D devm_clk_hw_register(provider->dev, &sci_clk->hw); --=20 2.47.3 From nobody Sat Feb 7 05:01:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C6EA1531C8; Tue, 23 Dec 2025 12:47:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766494077; cv=none; b=Y/eel5SOb5uF5n7zaWO6KE4QeCYiOVGRl4xnNzZVRsS9f+EGOoS/JqoAqhPlVxoRhMJsdBCe7VKvZARlFCc84SdY+XtnOVrB9QB35l9Ggq4He8pYI54W690IKZqQKIu8ARFzXfgzOHd5twG5Wkuo1PHxVvNHquHOpB6UhjphlHw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766494077; c=relaxed/simple; bh=WXvLUt0Z4RKCNcS99dOC/TE9RwivHFDhbm9iqtxU6lw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rfXCsThG1fbCtttHEMIjJAu6TjudJePIVADKOjPlFiOB/M/M7cdxt+p5YTQIbvVZytCzk1tIH9sV3Tdg/YfOYTFDzI8//6gqqwrrP4PxP1ds9bLJgl1sTojJKLHmjbbn5ZlNzwccdIQ7hPsYqAJQQwij3DugyQdBRmxO2WywxX8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oVkaDxA3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oVkaDxA3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 788F3C116C6; Tue, 23 Dec 2025 12:47:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1766494077; bh=WXvLUt0Z4RKCNcS99dOC/TE9RwivHFDhbm9iqtxU6lw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oVkaDxA3FQ+242CPw9Nk3qyl6ju3owT7uVtIWKZwdNSeXEe1CYIUzK3BXk7U9MjrK arUl9yXvURxfDeMoY6R/WsHSxOYqELoBj17bIGOXZeSGff2VY+2CTG113VuoHY7fym 0LIMDdgSvqGgwClsQuLb1ho//8eqrIx8j5lhMRRbUHYwfQSyuTySKvoNrQj9Sox85H NcdcUg+HUED3thRKNCHinPVr5USJNFMA2xTb5BNkvIlBOftbMxzTpX9L/lK6hFSWZk /A4gE99eQoL2W2a0HnZkhTo9db4WLu/U7MM1WaG1sasiE/9qFX1MGFS8DxM5oFUnFq rU0meQQEZrisg== From: Michael Walle To: Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Andrew Davis , Santosh Shilimkar , Michael Turquette , Stephen Boyd , Kevin Hilman , Randolph Sapp Cc: linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Michael Walle Subject: [PATCH v2 3/4] arm64: dts: ti: add GPU node Date: Tue, 23 Dec 2025 13:47:15 +0100 Message-ID: <20251223124729.2482877-4-mwalle@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251223124729.2482877-1-mwalle@kernel.org> References: <20251223124729.2482877-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The J722S features a BXS-4 GPU. Add the node for it. Signed-off-by: Michael Walle --- .../arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/= arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 3cf7c2b3ce2d..a55e5108e7b6 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -1110,6 +1110,17 @@ dphy0: phy@30110000 { status =3D "disabled"; }; =20 + gpu: gpu@fd80000 { + compatible =3D "ti,am62p-gpu", "img,img-bxs-4-64", "img,img-rogue"; + reg =3D <0x00 0x0fd80000 0x00 0x80000>; + clocks =3D <&k3_clks 237 3>; + clock-names =3D "core"; + interrupts =3D ; + power-domains =3D <&k3_pds 237 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + power-domain-names =3D "a", "b"; + }; + vpu: video-codec@30210000 { compatible =3D "ti,j721s2-wave521c", "cnm,wave521c"; reg =3D <0x00 0x30210000 0x00 0x10000>; --=20 2.47.3 From nobody Sat Feb 7 05:01:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9644232860B; Tue, 23 Dec 2025 12:48:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766494082; cv=none; b=OFDL1tE+igzdBK9I03tcZ4ExyBaIg4+UmHFUjkF+GozeUifmQEvVCNGX7srOGiLSn0rrgkho2RViNlbjvpb9nw3rOZUu6/+uceN+R5DAvgjpjpU99aqdMfQAr1Wly3889HgDyRl1tKqBSr8l2mM8pt9ouEwAO/rXRswybFQNeQc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766494082; c=relaxed/simple; bh=B3xjfPRKFS0qoDeFoIRFLfaayzMur0aXjaMmej6M+fY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tNdQpELdNqzleEMErPnuasdi+vbKQ2D7BI6MpDKrIr/ffv75xW44aemgi4r633vvoxIQp2PdHtasjEpuvmTolxMK0u+sc1VxgvZzw8ov0mhbd61Y/gI2OMroa2J63/WeDebAkiwneDENy37pt9qVWe3M5KFTovV4f4XJJRQe8l8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NbcY4pX7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NbcY4pX7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8B8E4C113D0; Tue, 23 Dec 2025 12:47:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1766494082; bh=B3xjfPRKFS0qoDeFoIRFLfaayzMur0aXjaMmej6M+fY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NbcY4pX7UDRBAH4ABtafnWNjBiGs15KK27AUjeMprV6VHlaJScb+kc0gkP4pq9L64 BnExPDBzCuUh4NNdaojK6q9d+2HvCjUKfhxmXNUCdPkP+/KI3dSk0KfB9ZpP4+xQPI 6+aBqjJh5BBnRhixRWoVMjer4IH+31iJXIta72hIW+FGgJdn/97wLG3cumHLXPvLtt nzugW7B58tBFoaO4W8iCsxOCpo8GKnunDulQoMUCuzjDlg+EdQgbHieFvJ4zT4VGPo FXcaVYmCJjWYzWcw4/vJbqqNiRYs3ZWm6gohw3+3z49F7IwWLQKvxpKRSCSsVDuRAg oi9eh0bpFPHnQ== From: Michael Walle To: Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Andrew Davis , Santosh Shilimkar , Michael Turquette , Stephen Boyd , Kevin Hilman , Randolph Sapp Cc: linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Michael Walle Subject: [PATCH v2 4/4] arm64: dts: ti: sa67: set the GPU clock to 800MHz Date: Tue, 23 Dec 2025 13:47:16 +0100 Message-ID: <20251223124729.2482877-5-mwalle@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251223124729.2482877-1-mwalle@kernel.org> References: <20251223124729.2482877-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The board is running with a core voltage of 0.85V and therefore we can clock the GPU at 800MHz. Signed-off-by: Michael Walle --- arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts b/arch/a= rm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts index 7169d934adac..0c7f3e10a150 100644 --- a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts +++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts @@ -292,6 +292,12 @@ &cpsw_port1 { status =3D "okay"; }; =20 +&gpu { + /* The VCORE is 0.85V, thus we can use a faster GPU clock. */ + assigned-clocks =3D <&k3_clks 237 3>; + assigned-clock-rates =3D <800000000>; +}; + &main_gpio0 { gpio-line-names =3D "", "", "", "", "", "", "", "SOC_SDIO_PWR_EN", "VSD_SEL", --=20 2.47.3