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Tue, 23 Dec 2025 04:14:33 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 08/11] cpufreq: CPPC: sync policy limits when updating min/max_perf Date: Tue, 23 Dec 2025 17:43:04 +0530 Message-ID: <20251223121307.711773-9-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251223121307.711773-1-sumitg@nvidia.com> References: <20251223121307.711773-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB75:EE_|DS0PR12MB8479:EE_ X-MS-Office365-Filtering-Correlation-Id: 767b4306-eac8-4113-db47-08de421ce251 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|7416014|82310400026|376014|921020; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Dec 2025 12:14:55.4786 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 767b4306-eac8-4113-db47-08de421ce251 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB75.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8479 Content-Type: text/plain; charset="utf-8" When min_perf or max_perf is updated via sysfs in autonomous mode, the policy frequency limits should also be updated to reflect the new performance bounds. Add @update_policy parameter to cppc_cpufreq_set_mperf_limit() to control whether policy constraints are synced with HW registers. The policy is updated only when autonomous selection is enabled to keep SW limits in sync with HW. This ensures that scaling_min_freq and scaling_max_freq values remain consistent with the actual min/max_perf register values when operating in autonomous mode. Signed-off-by: Sumit Gupta --- drivers/cpufreq/cppc_cpufreq.c | 35 ++++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 1f8825006940..0202c7b823e6 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -544,14 +544,20 @@ static void populate_efficiency_class(void) * cppc_cpufreq_set_mperf_limit - Set min/max performance limit * @policy: cpufreq policy * @val: performance value to set + * @update_policy: whether to update policy constraints * @is_min: true for min_perf, false for max_perf + * + * When @update_policy is true, updates cpufreq policy frequency limits. + * @update_policy is false during cpu_init when policy isn't fully set up. */ static int cppc_cpufreq_set_mperf_limit(struct cpufreq_policy *policy, u64= val, - bool is_min) + bool update_policy, bool is_min) { struct cppc_cpudata *cpu_data =3D policy->driver_data; struct cppc_perf_caps *caps =3D &cpu_data->perf_caps; unsigned int cpu =3D policy->cpu; + struct freq_qos_request *req; + unsigned int freq; u32 perf; int ret; =20 @@ -571,15 +577,26 @@ static int cppc_cpufreq_set_mperf_limit(struct cpufre= q_policy *policy, u64 val, else cpu_data->perf_ctrls.max_perf =3D perf; =20 + if (update_policy) { + freq =3D cppc_perf_to_khz(caps, perf); + req =3D is_min ? policy->min_freq_req : policy->max_freq_req; + + ret =3D freq_qos_update_request(req, freq); + if (ret < 0) { + pr_warn("Failed to update %s_freq constraint for CPU%d: %d\n", + is_min ? "min" : "max", cpu, ret); + return ret; + } + } + return 0; } =20 -#define cppc_cpufreq_set_min_perf(policy, val) \ - cppc_cpufreq_set_mperf_limit(policy, val, true) - -#define cppc_cpufreq_set_max_perf(policy, val) \ - cppc_cpufreq_set_mperf_limit(policy, val, false) +#define cppc_cpufreq_set_min_perf(policy, val, update_policy) \ + cppc_cpufreq_set_mperf_limit(policy, val, update_policy, true) =20 +#define cppc_cpufreq_set_max_perf(policy, val, update_policy) \ + cppc_cpufreq_set_mperf_limit(policy, val, update_policy, false) static struct cppc_cpudata *cppc_cpufreq_get_cpu_data(unsigned int cpu) { struct cppc_cpudata *cpu_data; @@ -988,7 +1005,8 @@ static ssize_t store_min_perf(struct cpufreq_policy *p= olicy, const char *buf, perf =3D cppc_khz_to_perf(&cpu_data->perf_caps, freq_khz); =20 guard(mutex)(&cppc_cpufreq_update_autosel_config_lock); - ret =3D cppc_cpufreq_set_min_perf(policy, perf); + ret =3D cppc_cpufreq_set_min_perf(policy, perf, + cpu_data->perf_ctrls.auto_sel); if (ret) return ret; =20 @@ -1045,7 +1063,8 @@ static ssize_t store_max_perf(struct cpufreq_policy *= policy, const char *buf, perf =3D cppc_khz_to_perf(&cpu_data->perf_caps, freq_khz); =20 guard(mutex)(&cppc_cpufreq_update_autosel_config_lock); - ret =3D cppc_cpufreq_set_max_perf(policy, perf); + ret =3D cppc_cpufreq_set_max_perf(policy, perf, + cpu_data->perf_ctrls.auto_sel); if (ret) return ret; =20 --=20 2.34.1