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Tue, 23 Dec 2025 04:14:59 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 10/11] cpufreq: CPPC: make scaling_min/max_freq read-only when auto_sel enabled Date: Tue, 23 Dec 2025 17:43:06 +0530 Message-ID: <20251223121307.711773-11-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251223121307.711773-1-sumitg@nvidia.com> References: <20251223121307.711773-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE36:EE_|MN0PR12MB5761:EE_ X-MS-Office365-Filtering-Correlation-Id: cf48e479-fd63-4c72-e46f-08de421cf057 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013|7416014|921020; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Dec 2025 12:15:19.0934 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf48e479-fd63-4c72-e46f-08de421cf057 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5761 Content-Type: text/plain; charset="utf-8" When autonomous selection (auto_sel) is enabled, the hardware controls performance within min_perf/max_perf register bounds making the scaling_min/max_freq effectively read-only. Enforce this by setting policy limits to min/max_perf bounds in cppc_verify_policy(). Users must use min_perf/max_perf sysfs interfaces to change performance limits in autonomous mode. Signed-off-by: Sumit Gupta --- drivers/cpufreq/cppc_cpufreq.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index b1f570d6de34..b3da263c18b0 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -305,7 +305,37 @@ static unsigned int cppc_cpufreq_fast_switch(struct cp= ufreq_policy *policy, =20 static int cppc_verify_policy(struct cpufreq_policy_data *policy) { - cpufreq_verify_within_cpu_limits(policy); + unsigned int min_freq =3D policy->cpuinfo.min_freq; + unsigned int max_freq =3D policy->cpuinfo.max_freq; + struct cpufreq_policy *cpu_policy; + struct cppc_cpudata *cpu_data; + struct cppc_perf_caps *caps; + + cpu_policy =3D cpufreq_cpu_get(policy->cpu); + if (!cpu_policy) + return -ENODEV; + + cpu_data =3D cpu_policy->driver_data; + caps =3D &cpu_data->perf_caps; + + if (cpu_data->perf_ctrls.auto_sel) { + u32 min_perf, max_perf; + + /* + * Set policy limits to HW min/max_perf bounds. In autonomous + * mode, scaling_min/max_freq is effectively read-only. + */ + min_perf =3D cpu_data->perf_ctrls.min_perf ?: + caps->lowest_nonlinear_perf; + max_perf =3D cpu_data->perf_ctrls.max_perf ?: caps->nominal_perf; + + policy->min =3D cppc_perf_to_khz(caps, min_perf); + policy->max =3D cppc_perf_to_khz(caps, max_perf); + } else { + cpufreq_verify_within_limits(policy, min_freq, max_freq); + } + + cpufreq_cpu_put(cpu_policy); return 0; } =20 --=20 2.34.1