From nobody Sat Feb 7 17:56:00 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012021.outbound.protection.outlook.com [52.101.43.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DE7E32ED4A; Tue, 23 Dec 2025 12:13:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.21 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492032; cv=fail; b=UD60H3dlYy940y3OOjdfd8SwL2AoK/ISagbtOZofkeNmROs7QXuSJa/ZzOlkWfoqyCZMbmZ2H4vnisk0IRhoPe2ygIG4YO++9Nkj5UaNzHmO6LftJm7PPXszawgTXx0bROQBsTfGhjDvGOuWWUoBNF/T0/k8YXnv6M64/M2uIok= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492032; c=relaxed/simple; bh=SRYgLFoCnfWZmQxsfBMu0k+wYxbr39i8aU/BugfCsy8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=i9M9mgFwWa8RXXsQ5tOEVq3gMR+ftznthclOKIFcT/yMRcvZmpkczMEx6xEKtw3ZgnROIhkPY+x+8TquhkVAlDd0H2qsLTfulwD1kL6hLyGXQAhNVDS37mPAdVh0cZli4145DreknEBE8k2h1vSQwkfrlp5trqkGKeEQ+2t3rDA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=G4RVMQmz; arc=fail smtp.client-ip=52.101.43.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="G4RVMQmz" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=FeOJ+oMlS1zKo62Gj1TTj7xvk5Ry9n3FyeVxzprJLm/Ty3uMsw9U9kCf7OerescJDB9j7nhgLpyS1/7upek7FHLoltpGS/vyOCo0f9zTCRnCYCnvNw01SfRyHmoiU6v5pgfvi085IE1Ii+XfNF2pcCWUtJWgZ9qIfhH5FEq1rZFH+gqG6pmgi5AGELaSqbT0Lrlb9DMDPBSgf17cGl2q8KKzgT1hOq9fWTngzM+7WjdEuK2hQi6hdO2HWBhlBHhNmh5QHbYepWVeTzxD9eap+jKIGh9vdRLXcow1BsSps9xR5PsAEU3OnUXxz1qbiCfiuag00MkGk+HXsv58g3Zcjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=bc4ivu+0y2mVMdduDtnz/2tNx0zq2Muw6kWpVOPPqss=; b=R9dZTYfZX2v6mvIveMybDF+SxtZeM5oX/Wi/e8UWcU3mXFpAztMLGnsdm8hRUZzID3IRe17hLo5yEB4U8gVa0zlSVYJZ4nilVb19euv+TlDWhiww7P4D3dAXDcgUtP0/pq1Pwi3m2b/cdzs5cbgdpB1A4fTdl9RWvcE0QpPJ12flolz/yTg8LjQ8ewlhGi1P7EsQbXLoXV4GwoOZYpng6DiftnlIhO+Jvqo9O1ku74KDiTPz7jWJOhXlJuGNOuoz6L4YbSrYsKkxj904WQmt8C6cryd3ZbQme/eIHLqtvKkVFEvdu5Hx1lxbawlHWQ7oMho+oO4sgJpPfrdQCT2PbQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bc4ivu+0y2mVMdduDtnz/2tNx0zq2Muw6kWpVOPPqss=; b=G4RVMQmzKXxdZ6N0bc01XDoozm0c0k7JfRJErCM/dtf8i/YhE27YXpC+2m9/Z2YSqaU3kel9K27dujZUC4fEXpY8Id0RoVpHwIdjLc4hmHsWmu1IRQE7SFZJL+n22zl27MsnLBW20KaGQICIwtWALqHZlvuQxIE1bF7O/Nw4VZpZNzBGYupF2COsaiOQtjGOQk/kl1BvxYxAhb2T74dU5h7oYF3asgQMvZV5f+TMnvxgr7Np1Ad+ChJSPPSrAVmqK4XZMC6v13Rc5NWhTK++WaMzTLw2DYQ2sxdOHRsDwVf30BPUio9qRAQN3/AHztH4eB9mn875EA/xsNNNmy8UJA== Received: from MN2PR16CA0063.namprd16.prod.outlook.com (2603:10b6:208:234::32) by IA1PR12MB8585.namprd12.prod.outlook.com (2603:10b6:208:451::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9434.11; Tue, 23 Dec 2025 12:13:47 +0000 Received: from BL6PEPF0001AB77.namprd02.prod.outlook.com (2603:10b6:208:234:cafe::f0) by MN2PR16CA0063.outlook.office365.com (2603:10b6:208:234::32) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9456.10 via Frontend Transport; Tue, 23 Dec 2025 12:13:45 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL6PEPF0001AB77.mail.protection.outlook.com (10.167.242.170) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9456.9 via Frontend Transport; Tue, 23 Dec 2025 12:13:46 +0000 Received: from rnnvmail205.nvidia.com (10.129.68.10) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:13:28 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:13:27 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 23 Dec 2025 04:13:20 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 01/11] cpufreq: CPPC: Add generic helpers for sysfs show/store Date: Tue, 23 Dec 2025 17:42:57 +0530 Message-ID: <20251223121307.711773-2-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251223121307.711773-1-sumitg@nvidia.com> References: <20251223121307.711773-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB77:EE_|IA1PR12MB8585:EE_ X-MS-Office365-Filtering-Correlation-Id: 8dbfc1da-fd6c-412e-699e-08de421cb91c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|1800799024|82310400026|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?GRFhkBwZkcvugumZgBPdsOnAI/k/DEZLCejbDfdmrt+o2ukJWmTIs8xIes/X?= =?us-ascii?Q?ub4OSQiJSr7VK+f6NrDKfIY1eQrXGfiUONiRPnt8m6fqcQDpsuBm1TmDt47V?= =?us-ascii?Q?je29sEzZz2pwMzanH35aiuzLze/1ZCUKS8vF17utkq19zoc/Jblm6szcGNm+?= =?us-ascii?Q?VRF6o0/k5hGPfIYmVagXIYerhmW+IDzeD126cM1b0PgWulRBckQraAfgpEBp?= =?us-ascii?Q?bg2QJy0nWZIYM/jPKDxI9x1wim3vfBvagvJDCk2/vZF3D9mmuNWkFrRywSfR?= =?us-ascii?Q?gC2lze74vGgyGQKN4Fj0bFgl6ZPtwW98efXqIcS2AjlOW/0Ou99guz8KGUmk?= =?us-ascii?Q?4Hqi9ET4TFY5EGffNB9IgZnE5dc3j0AAZ7hbAEgcwIJkXw99IY0cDF6FbWI5?= =?us-ascii?Q?4qqkNDvGu+snNMEIy5H3omoZsXvKEHcS7GDT6gVLafAPcULxU2QKjAYYyAcc?= =?us-ascii?Q?zypwmb5ry0usxi3Rwgal4N0Nl449KghI13Z/SXxTWDj0t46E334hwyQZwxTW?= =?us-ascii?Q?cKJ0rTMW/ZZQN7TD6769nEW32jxkiQBY4J0zJqo+qBpoZj+iiNnbUluQ/FM2?= =?us-ascii?Q?kti5w1JmMy75LxbS27MQuYkNzKxa/As8Yq4i34zlhanElnUKAgYBq8KjpCEW?= =?us-ascii?Q?iImMLJgzJQb7hxTLdlKQTedeXIEp6LObCyqiWbAbFW71EbxV6N2CD0dhQUKH?= =?us-ascii?Q?LwPHI1YOwkrmtMFPiqn+siCiCglfzhXbUYD39tOHaWZtYPhUf8LnCpnYKmCa?= =?us-ascii?Q?QSc21vYQ5X2t97yqbamqSdKKBrSvsOeG4zaco8laiI306/38g9EUe5+d88U1?= =?us-ascii?Q?wO2Audl5PPkIZimQKS6NC/Ljj0iyg7t4rZiTMpGTeipj/gyzicFct3OGDYam?= =?us-ascii?Q?InFpBmyhcYB61S1SNNBJdp8DCEm+hGycrgobAM0xFCOzRdKJUeM2ujHCeF/1?= =?us-ascii?Q?FBAjmAqBjkR/xjPwjIo3pHRBZh0umTa9pe3y0hUPY/aPd2OX5CsZTybkM8VR?= =?us-ascii?Q?5k7HZRMzX7GUdrz+cMveFYRVE6lqzShixG2gsKZ4S0n1qG0d4ezuboEEnFLW?= =?us-ascii?Q?kgugt8+e832bvkIzY8YkIQp7xrGWDoPmA8nwYjd5bWWAEJLmcW3Oo/g3dmvO?= =?us-ascii?Q?MfCLLnT3NT2OHwNkmHN0KPAKHyT/N7lqEgbeb0Sy9jhCfWcwcfTCN3Wja8zx?= =?us-ascii?Q?RGV5fBUzjo9KKdQYnT1ztzVYvk4bhPI975snCCdR1iqBtyBrHGnjB/qh/nlU?= =?us-ascii?Q?/p6/hmJHr+oXuKY0cyLcrqtJlObOiTM5ltgFFhaiDuCMVQABeeXKjcPopyNn?= =?us-ascii?Q?YqfoqeZ/LpM4fcY5jtwJSeDq5AqpqXe6UNjgrk1jtBM06Gi5XCjBIJdAinsZ?= =?us-ascii?Q?PdIKBvbz5fSKjJhCFvZwAxsUd5o7kizPMmOcIptpnnfTvuyvZA0vbnsVHV4L?= =?us-ascii?Q?FVxGgzR+1GaypgWnm636Gip/LppyPhyhxxfN5ZcI3S3o4eeUxc9BNar60yPv?= =?us-ascii?Q?xjGcmJ37+4KZFalwvJBIMevGSHeggO9xqVy+iAiaJrSotsljbCc852ZyPTg9?= =?us-ascii?Q?tHy23GLUuP0/HDYWq8HqAYPQ0tuCjdNTWFTZ/qPa?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(1800799024)(82310400026)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Dec 2025 12:13:46.3576 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8dbfc1da-fd6c-412e-699e-08de421cb91c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB77.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8585 Content-Type: text/plain; charset="utf-8" Add generic show/store helper functions for u64 sysfs attributes: - cppc_cpufreq_sysfs_show_u64() - cppc_cpufreq_sysfs_store_u64() Refactor auto_act_window and energy_performance_preference_val attributes to use these helpers, eliminating code duplication. No functional changes. Signed-off-by: Sumit Gupta --- drivers/cpufreq/cppc_cpufreq.c | 71 +++++++++++++++------------------- 1 file changed, 31 insertions(+), 40 deletions(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 9eac77c4f294..7c26ce554e29 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -831,72 +831,63 @@ static ssize_t store_auto_select(struct cpufreq_polic= y *policy, return count; } =20 -static ssize_t show_auto_act_window(struct cpufreq_policy *policy, char *b= uf) +static ssize_t cppc_cpufreq_sysfs_show_u64(unsigned int cpu, + int (*get_func)(int, u64 *), + char *buf) { u64 val; - int ret; - - ret =3D cppc_get_auto_act_window(policy->cpu, &val); + int ret =3D get_func((int)cpu, &val); =20 - /* show "" when this register is not supported by cpc */ if (ret =3D=3D -EOPNOTSUPP) return sysfs_emit(buf, "\n"); - if (ret) return ret; =20 return sysfs_emit(buf, "%llu\n", val); } =20 -static ssize_t store_auto_act_window(struct cpufreq_policy *policy, - const char *buf, size_t count) +static ssize_t cppc_cpufreq_sysfs_store_u64(unsigned int cpu, + int (*set_func)(int, u64), + const char *buf, size_t count) { - u64 usec; + u64 val; int ret; =20 - ret =3D kstrtou64(buf, 0, &usec); + ret =3D kstrtou64(buf, 0, &val); if (ret) return ret; =20 - ret =3D cppc_set_auto_act_window(policy->cpu, usec); - if (ret) - return ret; + ret =3D set_func((int)cpu, val); =20 - return count; + return ret ? ret : count; } =20 -static ssize_t show_energy_performance_preference_val(struct cpufreq_polic= y *policy, char *buf) +static ssize_t show_auto_act_window(struct cpufreq_policy *policy, char *b= uf) { - u64 val; - int ret; - - ret =3D cppc_get_epp_perf(policy->cpu, &val); - - /* show "" when this register is not supported by cpc */ - if (ret =3D=3D -EOPNOTSUPP) - return sysfs_emit(buf, "\n"); - - if (ret) - return ret; - - return sysfs_emit(buf, "%llu\n", val); + return cppc_cpufreq_sysfs_show_u64(policy->cpu, + cppc_get_auto_act_window, buf); } =20 -static ssize_t store_energy_performance_preference_val(struct cpufreq_poli= cy *policy, - const char *buf, size_t count) +static ssize_t store_auto_act_window(struct cpufreq_policy *policy, + const char *buf, size_t count) { - u64 val; - int ret; - - ret =3D kstrtou64(buf, 0, &val); - if (ret) - return ret; + return cppc_cpufreq_sysfs_store_u64(policy->cpu, + cppc_set_auto_act_window, + buf, count); +} =20 - ret =3D cppc_set_epp(policy->cpu, val); - if (ret) - return ret; +static ssize_t +show_energy_performance_preference_val(struct cpufreq_policy *policy, char= *buf) +{ + return cppc_cpufreq_sysfs_show_u64(policy->cpu, cppc_get_epp_perf, buf); +} =20 - return count; +static ssize_t +store_energy_performance_preference_val(struct cpufreq_policy *policy, + const char *buf, size_t count) +{ + return cppc_cpufreq_sysfs_store_u64(policy->cpu, cppc_set_epp, + buf, count); } =20 cpufreq_freq_attr_ro(freqdomain_cpus); --=20 2.34.1 From nobody Sat Feb 7 17:56:00 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013020.outbound.protection.outlook.com [40.107.201.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF387331A6E; Tue, 23 Dec 2025 12:13:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.201.20 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492039; cv=fail; b=awr49+ejGE5pSA+yhgMzYIcbRRm46Ko2orQuYz6jYBqKWFhQRKDKbNkFfQFrUg7ayNynNDBi5YnqA85ZSnQUVxjtZcMuY9NuvVeT/6UtotYyDI9xdoOJjY31+s43+DJ5KvtfCTEju2WQTwFLi3CgN8O0JPbILCL7ztW+Jtuofck= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492039; c=relaxed/simple; bh=oPmfzuzdJrvlTsNvYKRYEU2chcOcwtmhWaNmP/PsEBo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KPFtgGf96n6EQb9MtlvZLvZmMIFUHynF/d+szlrncN2w8h62R+kiHxUS8XePMzDhcx8D5chG6E2LkpPZxO6+ylQLkjqER8I40+dTqBEpTfAcmi+SqU79ldJNxtNlAn7RTe/5IsEVccYTVaF9lQFnFUnpTDmTF5OUMiSFhEG4wRM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=qgX07Q6v; arc=fail smtp.client-ip=40.107.201.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="qgX07Q6v" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=NszzYe9CYySmYCt2wQeVZp2E9vQeF1xDxijqLQU7OoTZw9xtjDlP7WteVuvA4LaPS9ElGNII5ruQpdLe7jDxmjdFbyX7Z63U0fzxzwOqUh+cOBrSpY9vSJrTRcf2o9V+GV92SVyQo5UfesIhEIQZHZNHw8HJsOeIoEkb9gk/Mlrqc2Bl1UUAL08I0jlRMZ45Go4h7o8iaSoVMyWeu210pBgBMg2qmDjeR6yTesSruP73KpaT0jAXAV5puNybIszEmtwlx03SFPj3NYAnm0dugiIWp7A39TvSIshkcpNmajAno6uRgigi94abwBXXAoJJ7eqgKLxaosEa6ZvDxxF+/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=OLcwldikhS91ww2sE9IaXldkzy8C8UXJNVDAavCmOS4=; b=GVGSPMF8Hb4khHe6CzDuQHnLh+G2pnAWlsuVLJZgIyDHxJmvnCpRWxrhRDK+Y5Wmbt9Vg+yKHL881KPtXYnpy81TeNoSnglyXFXFhRlXYxNFscIEyBw8ue998vvT0PJB+fC/c9FYqk2Vq0/jLfJIFxJXYa6HJoK/OXYhDFLnpjoGrFohNQQyjBaC1YkiN/+5JDA6XIw6dp/vIDBxpFxTmksAwuXuRxW0zXJNie5PJV7MNuRuT1+HKQIGDouS6ZpciEE9GKFG9mpMCrlAh/IQjIFD0G/eHAbEw5CbojkeEJ6IRiRCWDi4lDUOS8QSF5QKunpxzsAdNOdQ36XJ4MBZKg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OLcwldikhS91ww2sE9IaXldkzy8C8UXJNVDAavCmOS4=; b=qgX07Q6vR7nuclQgJPsZ0mjjFB9nCA/2LQzXr8580YghFr/pL/vxV2aaO2P54XGW9HIfk9TeIhmdGMguY0QaPsoMs+SZe/wA/YRYnHlV/QC9yPI+SjBbal3Vz5KgcsPS98GbOJISqvW2ljBGszHClLMmPAs6qKLV1a4kI3uce63gZEVo8m7Ji1AxhXSGVL8A9x9tABFCvut6ySyrDzubPu87Y1LQEjwsNk6Y56nB6xA8rVSbL9M0UIwUmNdpCUOpwqhPlmmK7HD+RgJFDS1hQTdmxfvPmZfehQ7iCQEr4jDcRXzjNGuyDEFqbD6W6MXd50cIUVrXW5dUpbFN4XdOJA== Received: from PH8PR02CA0040.namprd02.prod.outlook.com (2603:10b6:510:2da::17) by BL1PR12MB5779.namprd12.prod.outlook.com (2603:10b6:208:392::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9456.11; Tue, 23 Dec 2025 12:13:50 +0000 Received: from CY4PEPF0000EE30.namprd05.prod.outlook.com (2603:10b6:510:2da:cafe::a2) by PH8PR02CA0040.outlook.office365.com (2603:10b6:510:2da::17) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.11 via Frontend Transport; Tue, 23 Dec 2025 12:13:42 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE30.mail.protection.outlook.com (10.167.242.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9456.9 via Frontend Transport; Tue, 23 Dec 2025 12:13:49 +0000 Received: from rnnvmail205.nvidia.com (10.129.68.10) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:13:37 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:13:36 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 23 Dec 2025 04:13:29 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 02/11] ACPI: CPPC: Clean up cppc_perf_caps and cppc_perf_ctrls structs Date: Tue, 23 Dec 2025 17:42:58 +0530 Message-ID: <20251223121307.711773-3-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251223121307.711773-1-sumitg@nvidia.com> References: <20251223121307.711773-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE30:EE_|BL1PR12MB5779:EE_ X-MS-Office365-Filtering-Correlation-Id: 117eb132-48c0-49ba-1b0e-08de421cbac3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|1800799024|82310400026|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?l7l3KHNn3ZjsoIZw1hzRSaqYLI+BWxltnL40jUBllYir1cjT/uhZUGlqrDcg?= =?us-ascii?Q?ubL7Xg1Z8uz1VaiX+VNNWcs2s7TABiewj5tOnwrpHPE+12e1ZUCH0JyCWiKv?= =?us-ascii?Q?SEkZ1GJV5BWCYAkaOk4I81hnBPsgzrhv1pxgb2EScupclo2n0wyPA2Q0arww?= =?us-ascii?Q?rmnxNUAN/JNmuqX7M3rQSszsEHxo+SnZO/QTv60GAJDYek1sbU5LM7jjqqIG?= =?us-ascii?Q?WsRIbQVkV3CoLOZfd2D9cz+rbJRGhpHFTPDYh/ILjbo7RN/6mEc6aqVKyV73?= =?us-ascii?Q?vz0lCsSsPn/V/iF3SFUmxIFRHib/vxoA9ArG+/K28BUTneXxC+IHfN46kHXK?= =?us-ascii?Q?rtnoRVxo79s2dtZUAP7mvmFFnitt0Au+QK26z9y0YHE+ioVtzdNGLSuYXGap?= =?us-ascii?Q?F237YQCHTtxSQfo2IpmfHXu1qC0L8EWAHwgdUTBvpNOZ1zAnvc32hOGjN6uF?= =?us-ascii?Q?HSAwqHJV3+CrYAPpxYlKCRGYiPmAV1GdDtUmPWAyfdgJ6TmAVYN2GTkl14tB?= =?us-ascii?Q?qj98IJwHV+YB7fnZdfsk8X7tx0U3tf1EIoBfTUhaOH1Y1bIwksy30LFcN9d7?= =?us-ascii?Q?bKE1r5MVy0MbA8GdSVds9S6kvx/t2oAtB42uPe2aTZxuljeycoStv7N1JyJr?= =?us-ascii?Q?bS2RelwFIIRYoXICerqylw8JsBLdQzEyK1YUKXymGfg5aAulSAYSPimeUgcm?= =?us-ascii?Q?fjCezKSxUnRtHmGBF//ML822NiPpCtzaaSV7lBo2u/QQqNCru4B5rNONhbcp?= =?us-ascii?Q?cP1IHwFEh4ftj984Z8Plb6tlh2DRGAzrRKmv2pqeJDPPtOIxc2hx2omoDOD7?= =?us-ascii?Q?fAW+vA1qnPvlWP7t2IGrqWt5P3xhwypuLoQYOMl6i52YRX7G9F6nrFZx5cPx?= =?us-ascii?Q?NvEg5T5zaGkGfe1rxBwo4ggLU1svDxkL+nkxqzt/6vRqVTFPUCEbo+bEBo68?= =?us-ascii?Q?IuIll2zJbT+lBh1w5qA1OEGamosnsfvgsLwUSkqkhfcjU8kpnxjpcMB8PI55?= =?us-ascii?Q?WuzKfw3a8jeWZs61/GZInWIIJ5pda/oTbG/ENPL6yVK9YYcY5rTCS5+VtUTX?= =?us-ascii?Q?888pFEPzSiJ1yvfUpHcjEY5j8UFVzy8cy8/+4kA1YHHX0hN0xJF0+F6whzyy?= =?us-ascii?Q?InD9fTDDgou4GJ1OAeTXoTLr26/QBZbuj7czf9MdFe79dVDTq/IAAbI9XL2f?= =?us-ascii?Q?oLUfL5NlZZ6CdXhXW84V8DjIVlOhyP3Omk5HAVVt4HKEvrqqcHxZIJjeWYf2?= =?us-ascii?Q?dlSXYrE/dg0vDLbO6/TWqAWUFnBIWi4XfSaOHezxMmrf9YV5wDu01ykIYMm8?= =?us-ascii?Q?5JAYp3fjLL9xd9gVciYhvSZbWxGHf6he5k6yzOj2ZQIpUIhDZ5T3cXBqtbwh?= =?us-ascii?Q?S5CrljJ2X6S9f2GZW/sJ5bu+BTpQDiUIjdTrePCZA6aOVBzHTQf97TxzqkzV?= =?us-ascii?Q?mCFlY1vNnJaxbSdyL4xVqMRMd4P74nkGwL2wmxYpD2fvvYv56xddwacJMzr2?= =?us-ascii?Q?FlGp30AxDaW9HmeI5RDvr3P6tB9gTonqi/rKb2XRvvwluP4/2IoOGy3vxsiW?= =?us-ascii?Q?5StoByiFkDOK0D8jK+drdiDBSHnbdV437oCOk32J?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700013)(1800799024)(82310400026)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Dec 2025 12:13:49.1927 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 117eb132-48c0-49ba-1b0e-08de421cbac3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE30.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5779 Content-Type: text/plain; charset="utf-8" - Remove redundant energy_perf field from 'struct cppc_perf_caps' as the same is available in 'struct cppc_perf_ctrls' which is used. - Move the 'auto_sel' field from 'struct cppc_perf_caps' to 'struct cppc_perf_ctrls' as it represents a control register. Reviewed-by: Pierre Gondois --- include/acpi/cppc_acpi.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 13fa81504844..a090b010f5f1 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -119,8 +119,6 @@ struct cppc_perf_caps { u32 lowest_nonlinear_perf; u32 lowest_freq; u32 nominal_freq; - u32 energy_perf; - bool auto_sel; }; =20 struct cppc_perf_ctrls { @@ -128,6 +126,7 @@ struct cppc_perf_ctrls { u32 min_perf; u32 desired_perf; u32 energy_perf; + bool auto_sel; }; =20 struct cppc_perf_fb_ctrs { --=20 2.34.1 From nobody Sat Feb 7 17:56:00 2026 Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazon11010061.outbound.protection.outlook.com [52.101.61.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD193331A77; Tue, 23 Dec 2025 12:14:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.61.61 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492049; cv=fail; b=bSEk3Te64bZLsLaoT0rBvh7dqxMQJGnDg7CZmwocZcPCARy4f1BbzuE6iCNYzEt/cEeRYs00z4q/VWhgAv5BhPelGWQkWnvFPi7GH3IxO5yIzCyRlmB7Brv2CRw0Y1h9bC4ru4QHI5kJzGkRy9Riblo1ozgaXTL48tQT178UlgU= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492049; c=relaxed/simple; bh=eikuNNWZCmRL/5A/z+zcw2F0CuizEaJFL8vzA7A0pj8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cxFoWWpH+0HZA5RvJsG76aI1AMXA2VO+edmQguF+HrCFbI7QK98F/HquSL8reCrzH9Kb87cHmAsRjUa2lCNs7pGI8nJYQZ43iiIAjEmsPaTOwJqCdJBgZXV55cDgNJakgRhTWeXMxt54EZdrjmJQycsCVFF0PMEPNXYEqsLsY4U= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=W1XVCRmz; arc=fail smtp.client-ip=52.101.61.61 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="W1XVCRmz" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=NyV/fMg9EOXsvJ/F3EMw0x/rvWcTFinZxZ+Gvcig75iGXoPVkbWKKSlo7aX0o80U71SwdMBsHwDT5TKV1P7M+PUNbnCEFWfqQsFg+El8/k2jW0es+zIkwpHG54h74EOqK3MPNKpLXu30JeGGtxbMxauXxEEFTWfibwUi2c/q0nJBfzrMQgNDRnJTW4WcsrQiV6b7xCC6Ab8UMQUklLyi/RKkIqaEDg2eeo6QbcrNDxJtWo0kqubSBmqouYKKsTwdhMBX+GbRD7H9mwXFcg3WQUqIObOazEZjddwOQiCd97p3k6lyv/e81nsDoFvX+hQv7jCoFUnXHtJieQsOwEdWyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=kT//9ChpBu5xs99TSYBBq4OmHngQKlF95xpQI+Ke6MU=; b=CiwDVEJsI8wZpPEXKcR5fK3R1WBJxHxQlL31jHB86HpVEp7wy2ci2Pk7zTQIGDYRK4ZWCXo8zfWioqXfZivtYEqiPU8xTGgrZRGThePul5gHMItZL3eBuKZhvvJW3IroYFsbek/NucYTZwUGK/6fHWkqfZUinRExmOt/29H6LYOBF/U5m2Bc4h5KllOJ4lvs3CiJNQbHuZncpPMIqBSG3amPzJv66jgbr116JyXHs0a14RxPVa2QPXSr+xZTxdQtG5DTmTqzq/a+BE7rs//CRT2uTPTY13+BOA4XPU8d/1/pzrI9/pZEJZOml4hj7+6EJVJnjNAKGdCSgk0yHOwwMA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=kT//9ChpBu5xs99TSYBBq4OmHngQKlF95xpQI+Ke6MU=; b=W1XVCRmz/xJpQgkWfApMtqlEPgRq44Cb5Zqr8z9udjicNWoB+Jcfe6csjaxPFnMqNnrgzjRMXVL23TnXwjsD0YwOMPUU8+iM7mDDaRw1ycZCb8Xv5MToygDUt+HM+imPypkzq9qPM6KjMr1lr9QBuvVHMBpk33wl32L6Jsw5ySC7L9x7noTVgTEMvSs6WE7ytjr0UMD6TubqJOZZvCqGUesN8TuBDhLEyfwzmiAR19Q4O8uTVIWqsnWE1XHkkw88HEaSV9NivhBBI04pNtjjZFm+ziQcNPlpibsfXDbjmLmELUhSB4YK062zfib2xhFmWdJFeFr6RzHlzM4/yp6PtQ== Received: from DS7PR03CA0168.namprd03.prod.outlook.com (2603:10b6:5:3b2::23) by MW3PR12MB4476.namprd12.prod.outlook.com (2603:10b6:303:2d::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9456.11; Tue, 23 Dec 2025 12:14:02 +0000 Received: from CY4PEPF0000EE36.namprd05.prod.outlook.com (2603:10b6:5:3b2:cafe::2e) by DS7PR03CA0168.outlook.office365.com (2603:10b6:5:3b2::23) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.11 via Frontend Transport; Tue, 23 Dec 2025 12:14:01 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE36.mail.protection.outlook.com (10.167.242.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9456.9 via Frontend Transport; Tue, 23 Dec 2025 12:14:01 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:13:48 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:13:47 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 23 Dec 2025 04:13:40 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 03/11] ACPI: CPPC: Add cppc_get_perf() API to read performance controls Date: Tue, 23 Dec 2025 17:42:59 +0530 Message-ID: <20251223121307.711773-4-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251223121307.711773-1-sumitg@nvidia.com> References: <20251223121307.711773-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE36:EE_|MW3PR12MB4476:EE_ X-MS-Office365-Filtering-Correlation-Id: 446f90a2-1aaa-4164-7d3e-08de421cc21b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|1800799024|82310400026|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?oedexfdQrjndmFfR9HY3oIMhf/I6uu7qLbGNR7vKptAh4KGLuy1yOc69qYPM?= =?us-ascii?Q?II9Fo06WShqqR7Y8jUIv4jPn6sVrYablRk0hK8/3kpVPq8DEcgoCWVNSXu2W?= =?us-ascii?Q?zmu0qpkz8YMO/2lzSdPBwBP3yzNSM336mxU0zk6h5qBDBx/fOddzXcPoaiMt?= =?us-ascii?Q?RN4HUPXcXTlgNmRAEF5PXPENg3xsYdUbNscpVABmFMeeDA63uMW9iWG/s9jr?= =?us-ascii?Q?vrWrh2HNQgSQcOcf+vi73Clxyka0XKcjCwrZ6VU/UWQhkkl0GYjLjq6GA7lI?= =?us-ascii?Q?iIv/FT0wmlPPYHtr+ZLIj6nvHfb2L1dZpu4hMX+tX+pNOU1Uw8/DOvxFBFdj?= =?us-ascii?Q?gmYZuaKeVW2ApUZZU3insTJMiSbgruASinPoWhX/0LeAiUNCaJxlv42DE1Po?= =?us-ascii?Q?x4MxaaVSMzp/7eRteLq9N3HuIN5cXjxIAPm4Txe+z8n5/3Ilus1vFflkDHOL?= =?us-ascii?Q?Zdl5rfj4ey4ArUvBaQNhA3bGXdrvMsFWUrZ+p1c+16eUkUhXvRUC/lSVZGFV?= =?us-ascii?Q?WE/3gVgve8vSh7JrDK2MK+rGydmk/B3lxVWUtlzVK0sou8qxlktlw+hasMu8?= =?us-ascii?Q?YMwa1mRYRzBP3UcFmqZfydW+3lpKoj6UbLvVaisiJd0c2CUc7aNG+HID7D9r?= =?us-ascii?Q?GSGMwYIxMzTThgzGDEACqQjjrfR2/WAVSIK9v0iGfbukxprTfi5YYH8yoNTv?= =?us-ascii?Q?3MaUrLxSwTYG2dRQbgcMGN9MKfWQARaQxU43iHq0suMSILcVOAlztAImfRN5?= =?us-ascii?Q?Rru6935WbtuitPVrBFfURumumYps1+oggEoM/fbLPNLlO3rrmXFfPXhod6RL?= =?us-ascii?Q?4V5ahCdiQ0tgb6YJYqX4li8UAzRx4DBpAsebxSTnUbYiAcT/H/lUU60IPsmS?= =?us-ascii?Q?OJ99I3aft449/NttEEt4mu0Ie/eDDhJk5rS82oUoqpWt7pcdxBqv9qla2hZt?= =?us-ascii?Q?GQlVQ6sMjMBypsDXLVdTW6wo+AH0Oh8OyBmyb9NRJ65uzllI81Qkf4QIr2rY?= =?us-ascii?Q?puuT6oKYrKZQ3eT/yFDV+qhAyCiZevMFqkgXEsqUFxblEeLWkqZv5belv2jL?= =?us-ascii?Q?+g3yn8spRlLYaekvr+rJ7ublNedrIOuX6nl8/YBTHtqTGjV7pebqbSFOxNkX?= =?us-ascii?Q?0VOzvTt2FnGv5D4ErHq38c9UIHEFW0c/hweU8m/VahmrpA5t+FTHA8BUk2tl?= =?us-ascii?Q?eBgQvZkkWqNsQ5GxKqt9bL3sgDmSeBPqNRK8GpK/E4hZC+adMwwIV/oOPIqk?= =?us-ascii?Q?uDTAsr412rxfmObx2Zhws7BJfQEDuG7Gj0csa0pAPGxHQW9041QwBFOZw07b?= =?us-ascii?Q?4ZBj5qW/o307y8EN69KPWgcRc3ONfZoxtC26S5dCgxHa+UOQon1hNJMJjsIO?= =?us-ascii?Q?7ayIwsCRTl2fZ0xPDzmCIMB6Hck6b5Apk/+w+h+AXvTLUD57yW17FmB1qe1V?= =?us-ascii?Q?P0AbPJbwwC5REDUszcfzb0wKCm0p5VjtlzmT8Heuu+RkVUVoEmdyDWd1z7SZ?= =?us-ascii?Q?6X1ovZheuR1MGDsuk3yijp7mhgrWJPVqCcfTZij5sD7yVjp+NNAnluOQySnf?= =?us-ascii?Q?v7XOQIo5bBzYF8AXYZPiaA6RX1PYZ9Rds/fv5MjI?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700013)(1800799024)(82310400026)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Dec 2025 12:14:01.5239 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 446f90a2-1aaa-4164-7d3e-08de421cc21b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4476 Content-Type: text/plain; charset="utf-8" Add cppc_get_perf() function to read values of performance control registers including desired_perf, min_perf, max_perf, energy_perf, and auto_sel. This provides a read interface to complement the existing cppc_set_perf() write interface for performance control registers. Note that auto_sel is read by cppc_get_perf() but not written by cppc_set_perf() to avoid unintended mode changes during performance updates. It can be updated with existing dedicated cppc_set_auto_sel() API. Also call cppc_get_perf() in cppc_cpufreq_get_cpu_data() to initialize perf_ctrls with current hardware register values during cpufreq initialization for each CPU policy. Signed-off-by: Sumit Gupta --- drivers/acpi/cppc_acpi.c | 79 ++++++++++++++++++++++++++++++++++ drivers/cpufreq/cppc_cpufreq.c | 6 +++ include/acpi/cppc_acpi.h | 5 +++ 3 files changed, 90 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index e66e20d1f31b..a4e89fe6aab5 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1732,6 +1732,85 @@ int cppc_set_enable(int cpu, bool enable) return cppc_set_reg_val(cpu, ENABLE, enable); } EXPORT_SYMBOL_GPL(cppc_set_enable); +/** + * cppc_get_perf - Get a CPU's performance controls. + * @cpu: CPU for which to get performance controls. + * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h + * + * Return: 0 for success with perf_ctrls, -ERRNO otherwise. + */ +int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +{ + struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpu); + struct cpc_register_resource *desired_perf_reg, + *min_perf_reg, *max_perf_reg, + *energy_perf_reg, *auto_sel_reg; + u64 desired_perf =3D 0, min =3D 0, max =3D 0, energy_perf =3D 0, auto_sel= =3D 0; + int pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpu); + struct cppc_pcc_data *pcc_ss_data =3D NULL; + int ret =3D 0, regs_in_pcc =3D 0; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpu); + return -ENODEV; + } + + if (!perf_ctrls) { + pr_debug("Invalid perf_ctrls pointer\n"); + return -EINVAL; + } + + desired_perf_reg =3D &cpc_desc->cpc_regs[DESIRED_PERF]; + min_perf_reg =3D &cpc_desc->cpc_regs[MIN_PERF]; + max_perf_reg =3D &cpc_desc->cpc_regs[MAX_PERF]; + energy_perf_reg =3D &cpc_desc->cpc_regs[ENERGY_PERF]; + auto_sel_reg =3D &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; + + /* Are any of the regs PCC ?*/ + if (CPC_IN_PCC(desired_perf_reg) || CPC_IN_PCC(min_perf_reg) || + CPC_IN_PCC(max_perf_reg) || CPC_IN_PCC(energy_perf_reg) || + CPC_IN_PCC(auto_sel_reg)) { + if (pcc_ss_id < 0) { + pr_debug("Invalid pcc_ss_id for CPU:%d\n", cpu); + return -ENODEV; + } + pcc_ss_data =3D pcc_data[pcc_ss_id]; + regs_in_pcc =3D 1; + down_write(&pcc_ss_data->pcc_lock); + /* Ring doorbell once to update PCC subspace */ + if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { + ret =3D -EIO; + goto out_err; + } + } + + /* Read optional elements if present */ + if (CPC_SUPPORTED(max_perf_reg)) + cpc_read(cpu, max_perf_reg, &max); + perf_ctrls->max_perf =3D max; + + if (CPC_SUPPORTED(min_perf_reg)) + cpc_read(cpu, min_perf_reg, &min); + perf_ctrls->min_perf =3D min; + + if (CPC_SUPPORTED(desired_perf_reg)) + cpc_read(cpu, desired_perf_reg, &desired_perf); + perf_ctrls->desired_perf =3D desired_perf; + + if (CPC_SUPPORTED(energy_perf_reg)) + cpc_read(cpu, energy_perf_reg, &energy_perf); + perf_ctrls->energy_perf =3D energy_perf; + + if (CPC_SUPPORTED(auto_sel_reg)) + cpc_read(cpu, auto_sel_reg, &auto_sel); + perf_ctrls->auto_sel =3D (bool)auto_sel; + +out_err: + if (regs_in_pcc) + up_write(&pcc_ss_data->pcc_lock); + return ret; +} +EXPORT_SYMBOL_GPL(cppc_get_perf); =20 /** * cppc_set_perf - Set a CPU's performance controls. diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 7c26ce554e29..a87e7bb2e2f1 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -562,6 +562,12 @@ static struct cppc_cpudata *cppc_cpufreq_get_cpu_data(= unsigned int cpu) goto free_mask; } =20 + ret =3D cppc_get_perf(cpu, &cpu_data->perf_ctrls); + if (ret) { + pr_debug("Err reading CPU%d perf ctrls: ret:%d\n", cpu, ret); + goto free_mask; + } + return cpu_data; =20 free_mask: diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index a090b010f5f1..12a1dc31bf2a 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -150,6 +150,7 @@ extern int cppc_get_desired_perf(int cpunum, u64 *desir= ed_perf); extern int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf); extern int cppc_get_highest_perf(int cpunum, u64 *highest_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_c= trs); +extern int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); extern int cppc_set_enable(int cpu, bool enable); extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); @@ -191,6 +192,10 @@ static inline int cppc_get_perf_ctrs(int cpu, struct c= ppc_perf_fb_ctrs *perf_fb_ { return -EOPNOTSUPP; } +static inline int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrl= s) +{ + return -EOPNOTSUPP; +} static inline int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrl= s) { return -EOPNOTSUPP; --=20 2.34.1 From nobody Sat Feb 7 17:56:00 2026 Received: from BL0PR03CU003.outbound.protection.outlook.com (mail-eastusazon11012034.outbound.protection.outlook.com [52.101.53.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BAC1F330646; Tue, 23 Dec 2025 12:14:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.53.34 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492060; cv=fail; b=HmVn6X8NGc7M0J6rqMUSti32LuNrMWBQ0VjBrkvDf+1NBliI+z8mCsR3MWUYSOaDwk0vPUhVLpg04EG5gD1wXjUs2yECue2ayEkr5y41d0HPAcJQLs2vjLvaSTMbzIFQhvyTjIDummckc8pN1nksrVvCwyywJuLlgTY0UeRsCEk= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492060; c=relaxed/simple; bh=shdKa5h2p18t6+JtyVP5tfIbvV3xxqQNgzynS2mRYEE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=c8FkVvI2L9iOLSyjofiWNpMacb3cecuchRVnDjd//lsMZsxoiUYcBa2uEX1U/cn63G2m4AzFqGYFvgMbu05bFsFxkHOf7L9e6j9qRpmGVvHSAcl06ZazGTan8is5D0+XTNDWivaqT9WMdYAR+c5tEurKLPRSRw+14rAHK9ekQrI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=NrM/x5y4; arc=fail smtp.client-ip=52.101.53.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="NrM/x5y4" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=OapVgQLpofZRnPVmKLZYXgUqlKxKqyKE88PjSPh0IV572NYM+gc2GJuFT2LUjHEdREn6onw6U6P28pMCjMNkjSFqPognYZmJj8HL9ld/ZSwcwHzKWOHEVngiXmNCnFcRARCbJBGKX4Ids2TL2rKvDHgh2PiavHBn/UwVxLsxfcyJdJAP7re6Dr/Mb774ejbsoFV3O1C6Y8zRE5cZuxh/AdmN5YInNPTpRUH3g6YGGizuBO7frCbqbbkhpYwWybOaseX76ChW2aVxTE4UiNzoPM0zS4cfbSOpTNc8srt96kvIwubIiUIjnBVAe8PfGvGtG2aE3Fl/acxOjqTyarebLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=83kf3fk6F8ypQOgtwJ2pzGIMfoyGA2hx1odEXex+gj4=; b=oUoqN67zhETO/+ErjBO1IYxXqZtkNMcUjIIWLZVhvzKzqDRYFub5KoRjUiVXTShYPLnmSLm+d9f9BstCk4x9Kuja19odnlbZeWSjSzoyOi9jZtDI43WQFhmvKooprqN5V39aGrNhAXT7M7JIaZIJmFA4eZIVpqvc+D2X9hc/wxxU+l6CPTwBa+twTme26tBDC7/GnEGXLYww4yA5LMaEFNGfyQcN2GsiCgtb3g85ciJY+BtUQLyP8rb9o4dT19D3YznKBo/MNTmgeMxvOMygdi+TCeRiRmByObEYuhmi6N6EyS85WJyKA4sFFLlUL2cevk9MxRIkmq5Ass3MZvRGLQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=83kf3fk6F8ypQOgtwJ2pzGIMfoyGA2hx1odEXex+gj4=; b=NrM/x5y4w65qotulVgxbctJRgsrRlYID8NBzG+LndFj4foM+T0KCGRMJfJUck9xp2ySgyyQeyyqKJY7Mx/vGG3YslM49V+/e8f146gC8SQ0kHqKXhQk1SVU7/+HZUW+ombInh4DKBMa9eikC/Tekw4Zk5pcxMDjgDW/EbwKpNFfZUXHEpky/AQi9sSxltwkQO1ycJniwqI1UcO039T2t6sbB/6nZ1Qc5MLvb2DFIrDgVHcoglNCk3S4DDFiQf6i3IOAwg0tFAUdEJXNXeD/YcJds44S9hVEpHpQodTEywGoGgF+/FImsPqr3r1XNHpDp7xOmYsZaNosDaQU0/FpT+w== Received: from PH8PR02CA0030.namprd02.prod.outlook.com (2603:10b6:510:2da::34) by SA3PR12MB7975.namprd12.prod.outlook.com (2603:10b6:806:320::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9434.11; Tue, 23 Dec 2025 12:14:12 +0000 Received: from CY4PEPF0000EE30.namprd05.prod.outlook.com (2603:10b6:510:2da:cafe::92) by PH8PR02CA0030.outlook.office365.com (2603:10b6:510:2da::34) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.11 via Frontend Transport; Tue, 23 Dec 2025 12:14:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE30.mail.protection.outlook.com (10.167.242.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9456.9 via Frontend Transport; Tue, 23 Dec 2025 12:14:12 +0000 Received: from rnnvmail205.nvidia.com (10.129.68.10) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:13:58 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:13:57 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 23 Dec 2025 04:13:50 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 04/11] ACPI: CPPC: Extend cppc_set_epp_perf() to support auto_sel and epp Date: Tue, 23 Dec 2025 17:43:00 +0530 Message-ID: <20251223121307.711773-5-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251223121307.711773-1-sumitg@nvidia.com> References: <20251223121307.711773-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE30:EE_|SA3PR12MB7975:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b3d1d24-0c11-4514-2900-08de421cc871 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|7416014|82310400026|376014|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?UHkNIJMaHTlXEURG5e54IhMPNiRq1FD64MU1EO+Vi91NOiJpEaG2CWghUUT8?= =?us-ascii?Q?in1nvMs4IuzZu8qFXchLfHY7dV3fNy0fHFmmbOxVrMwsD7UqsBd0aeiXiDN7?= =?us-ascii?Q?whpiMvPLoEh/9NszHNdHj+ljzJRnEugK059xFPHClXE30gSGcI2DrPErfbR3?= =?us-ascii?Q?ZVxWL8qqm3/ZSMKkrRSB378oKn3BMhDb6aWUghtcqOZe5od/EtRaN0RX0OeI?= =?us-ascii?Q?yG6RZer7G8RAZvegdiqmpTL2okUZ10nq//o+g2YwcKf9DYAVGmPHMWVcyoOa?= =?us-ascii?Q?r93H+CiwwmaVEVHT+Q6Jj9B2byFNnC9zMo+MVkruZViFhw7SYThihBBJyIbW?= =?us-ascii?Q?gnD9OmR60h19FY6rVE+cygs3g0vOU63fug/W855NHyjWVhHZ59+LT9u25I41?= =?us-ascii?Q?EpFkJLb1YQPSvE6Vft7QKkBQQci2rawdyNfCVnzr833PZukcT7mNjdf4Kh7H?= =?us-ascii?Q?n40MeWgFeVh/TMzacF1dBzTq1OJo5HuYt6Fdy/TYnQoipbLXlb4jxUksATmb?= =?us-ascii?Q?e4Jt2KWeeHHGp84zWd3wMnblWh8E4gCGEG/zaj4RrsqF5g0rfYqaeVM4TegC?= =?us-ascii?Q?GAy9FFIRLQiInRC/la0V+j198Fm1zQw8NcsFI8ZDbws4dncQKHhN+iFty1CW?= =?us-ascii?Q?2wGFAz9Gfuju1sCu3XnwbHlCqTnjdLnRVPgKScbo+xAkah51asF8xYi5ksRR?= =?us-ascii?Q?1PKZs8sbEG1TKEa+WNTngDvO1E7E+CJE/W4OwJtJ2sUnOAX8IS66vr4v0qhD?= =?us-ascii?Q?kI/4xbNXh1sR0ngUvCGNNW2LvWFw55/zIi48YXk5rh24Z2i4uDHrtMs+UGfh?= =?us-ascii?Q?zhLr67ZFbGi0vLBdaTDy1Tvwahwu9cflkvcfjnqlTHHxQsE6myZn33wV/H5k?= =?us-ascii?Q?PNsSr+UDQqXnt1HE1Lgp3mjfOrwS+w+AjVQgo2jYVpgObMdD9SL5EOKektPl?= =?us-ascii?Q?Dl15NCRjQs/3LYQWeC6vgIaZ6TdbzCvaJ+ouY1Cet8Pm0MEqigYC5kdIX4J4?= =?us-ascii?Q?1hOeTTn0VaU9yk9OFFmCxcLUxdC6mcZqDglaQcfQ2Pzo/YCmuuSXqELjhVI2?= =?us-ascii?Q?7otH58bccVRkNrU4ecT2up48uC54Sk6SrCrB6E0vhnxNV2g0jitgdiRLwBXY?= =?us-ascii?Q?Mdm8gHkQPPMaaAiiRUKDULiHtv4ZOOgclX4JiDSXspfucN5yv7tgLZ8gCDzR?= =?us-ascii?Q?Aqmi6jhXBFqAFPqh7QJzRgzMOL2N2Cqa3V/HIxR4agYniyAszUwKI/OFWyh8?= =?us-ascii?Q?UYUiX4LCR0w9SIYTl/l95HxjBpaOaDN4vc8BjoaxPEb5iQDw7B+WmQIhtuSw?= =?us-ascii?Q?mwdKkEbztzUGJsmXpOT2bSGouC1Q+hIbk4ESuCTqf4RD7XSduIcXfisvkSHV?= =?us-ascii?Q?UGqupEzBEYiS0ty07VCnmLX3A8zpGdDE5EGmbNM79BzBVXAbaS8I9CftQKI6?= =?us-ascii?Q?dJHZZx/hmS0H3Yll96DyU7/OcyWPWwgm3qHtTY0Rf0qX1lKPvnnHz2m+6TPN?= =?us-ascii?Q?P4BQ/gX0/mB58HKKnAS6ohkOT4CSqLb85SfhnatNtj5lqdIO8HNeLWsz6J5F?= =?us-ascii?Q?g1wA+pz2jBHtJ+fgprqhj8k/HoO2l/GXtGZANM3m?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(7416014)(82310400026)(376014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Dec 2025 12:14:12.1442 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3b3d1d24-0c11-4514-2900-08de421cc871 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE30.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7975 Content-Type: text/plain; charset="utf-8" Extend cppc_set_epp_perf() to write both auto_sel and energy_perf registers when they are in FFH or SystemMemory address space. This keeps the behavior consistent with PCC case where both registers are already updated together, but was missing for FFH/SystemMemory. Also update EPP constants for better clarity: - Add CPPC_EPP_PERFORMANCE_PREF (0x00) for performance preference - Add CPPC_EPP_ENERGY_EFFICIENCY_PREF (0xFF) for energy efficiency Signed-off-by: Sumit Gupta --- drivers/acpi/cppc_acpi.c | 35 +++++++++++++++++++++++++++++------ include/acpi/cppc_acpi.h | 3 ++- 2 files changed, 31 insertions(+), 7 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index a4e89fe6aab5..403ee988a8c6 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1556,6 +1556,8 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls= *perf_ctrls, bool enable) struct cpc_register_resource *auto_sel_reg; struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpu); struct cppc_pcc_data *pcc_ss_data =3D NULL; + bool autosel_ffh_sysmem; + bool epp_ffh_sysmem; int ret; =20 if (!cpc_desc) { @@ -1566,6 +1568,11 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrl= s *perf_ctrls, bool enable) auto_sel_reg =3D &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; epp_set_reg =3D &cpc_desc->cpc_regs[ENERGY_PERF]; =20 + epp_ffh_sysmem =3D CPC_SUPPORTED(epp_set_reg) && + (CPC_IN_FFH(epp_set_reg) || CPC_IN_SYSTEM_MEMORY(epp_set_reg)); + autosel_ffh_sysmem =3D CPC_SUPPORTED(auto_sel_reg) && + (CPC_IN_FFH(auto_sel_reg) || CPC_IN_SYSTEM_MEMORY(auto_sel_reg)); + if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) { if (pcc_ss_id < 0) { pr_debug("Invalid pcc_ss_id for CPU:%d\n", cpu); @@ -1590,14 +1597,30 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctr= ls *perf_ctrls, bool enable) /* after writing CPC, transfer the ownership of PCC to platform */ ret =3D send_pcc_cmd(pcc_ss_id, CMD_WRITE); up_write(&pcc_ss_data->pcc_lock); - } else if (osc_cpc_flexible_adr_space_confirmed && - CPC_SUPPORTED(epp_set_reg) && CPC_IN_FFH(epp_set_reg)) { - ret =3D cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf); + } else if (osc_cpc_flexible_adr_space_confirmed) { + if (!epp_ffh_sysmem && !autosel_ffh_sysmem) { + ret =3D -EOPNOTSUPP; + } else { + if (autosel_ffh_sysmem) { + ret =3D cpc_write(cpu, auto_sel_reg, enable); + if (ret) + return ret; + } + + if (epp_ffh_sysmem) { + ret =3D cpc_write(cpu, epp_set_reg, + perf_ctrls->energy_perf); + if (ret) + return ret; + } + } } else { - ret =3D -ENOTSUPP; - pr_debug("_CPC in PCC and _CPC in FFH are not supported\n"); + ret =3D -EOPNOTSUPP; } =20 + if (ret =3D=3D -EOPNOTSUPP) + pr_debug("CPU%d: _CPC not in PCC/FFH/SystemMemory\n", cpu); + return ret; } EXPORT_SYMBOL_GPL(cppc_set_epp_perf); @@ -1609,7 +1632,7 @@ EXPORT_SYMBOL_GPL(cppc_set_epp_perf); */ int cppc_set_epp(int cpu, u64 epp_val) { - if (epp_val > CPPC_ENERGY_PERF_MAX) + if (epp_val > CPPC_EPP_ENERGY_EFFICIENCY_PREF) return -EINVAL; =20 return cppc_set_reg_val(cpu, ENERGY_PERF, epp_val); diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 12a1dc31bf2a..2860a0252313 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -39,7 +39,8 @@ /* CPPC_AUTO_ACT_WINDOW_MAX_SIG is 127, so 128 and 129 will decay to 127 w= hen writing */ #define CPPC_AUTO_ACT_WINDOW_SIG_CARRY_THRESH 129 =20 -#define CPPC_ENERGY_PERF_MAX (0xFF) +#define CPPC_EPP_PERFORMANCE_PREF 0x00 +#define CPPC_EPP_ENERGY_EFFICIENCY_PREF 0xFF =20 /* Each register has the folowing format. */ struct cpc_reg { --=20 2.34.1 From nobody Sat Feb 7 17:56:00 2026 Received: from BYAPR05CU005.outbound.protection.outlook.com (mail-westusazon11010059.outbound.protection.outlook.com [52.101.85.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26744330646; Tue, 23 Dec 2025 12:14:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.85.59 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492075; cv=fail; b=r8+QkKE3UIVWQ7nOajZHkQsui7NwszV8fUj9nDLM3iaahZuQTzSsA+bopSM6keqIuiBs+lxllt2o0e/NrPTGOIyFwR7AMPB0u/3pbeWhjM0X1QxJRfbHxb4qKZcZ8W6c6pJUkvDr/qNIZB8pWGAzHLYrGpZLOttlNeXah67ANOc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492075; c=relaxed/simple; bh=jqVoojmB2FuGX+NjrxKdcXJAEWKwh7Ioa/di9BL0dNg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Lyw/TZMjlX0aBN+UmWcM1bQgPGYn+W4+HtkO5w4YE+Uaim5uSThiFsl3oCzppM7YRPIB9HFGQra/MbLtIa7t71dVLVwOzKC9/x5afbfZADaF68fmaIEgYQOdrDdP7ZakpuGhv1ORTDNuQQMF1/mvi9YlQx9fqySV2yHDz41PFdg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=qcFAfepa; arc=fail smtp.client-ip=52.101.85.59 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="qcFAfepa" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=qMBhzaAO0s+KunTN0bpKlxHroT4eD+rCIJU88FY+RL0cDzr7Qb2K6UUvOu75M7i+fYMJufNqH19FVnk5xIxtUEBFh6aQ6JZ+9XMVyyx1ScTh1cFMX5i6TPzJ1Smr43WWfX3pImvpPVB0/3UuzyofnS8naHQYxyndDErEQ8c69vzc1hLTvkdcJILVCKNC/vSBXUtm8ob3P7V/crPcO5QMLfL1UHpcnGxAMbM85akc2e2PCuXcWENqflDvtxVVw1xTnnqG/iWJUnXajgyXP7S9s4b7+ARLN9vTKEbAIihhwhHBO/rI5MW0zBqCUNyxybPW/6aUst7QV6vwZQH0cGC9AQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rVdeNsGG/txkSwOfF+JHPgUGK4izmGc700A2tS6XRlY=; b=HKEPydLs3mO1KmX8BJicwcdz44Vgv9y7fvSvvErZfBfDTsfQ8yf0SBWe/e/EukDRfFcmYpt5A9bzmDn53SvKz2a5z6tTOc1CZ1QSrw52CiYLiEm8amJ3dFaOqBvvW2SKifsOqI8SZ3fHJ9ePjcSPaI6aKXtPSjFDjZb7SKReUV1OziZ0lciquzhhgcmnOk+zqnzCGKKEN4beEDsziIV+jPcVCE57yPoQvcWxRhrSq11gXoSWWntnt2Z663E7fYyKDReDCgPw8RwiQGdze44ISXcY5E7KivFqF6OjvNoqaTOx6dSX1zwP3MX4L6o2pUXg9wwFSs31e5BRc4/msnMWTA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rVdeNsGG/txkSwOfF+JHPgUGK4izmGc700A2tS6XRlY=; b=qcFAfepa1xj//mpmrkikjy9U3WXoUpiQmKsgRFC39QhOSr0Bu2z52xw6okl89dPBUpgLdRMcnwTWJjCmc54C1qkJ0OntHna5w+pVWDwNbB9tnY9coXFPuE2h7Vpy+N61wqah8nfdC+a7ak1tz/iqPLBf7UU4nn18KdJ7IaS3s3EWNK2Tzq9vCnf6WANYo0qKuAoOmVE3EfwX9LI3953mi0DQSIPYlSTCz7XWYXB54QCXweup8SahIRuLB0Et9ojXTPQw1ZnxTvgc0TELssdZahnK5eW2N/2zrsYTHK1PQJttnIirArBhKgqglD6F5NFHUbTsc4Ypu9FjiNevqudsYQ== Received: from PH8PR02CA0042.namprd02.prod.outlook.com (2603:10b6:510:2da::31) by CH3PR12MB8235.namprd12.prod.outlook.com (2603:10b6:610:120::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9434.11; Tue, 23 Dec 2025 12:14:29 +0000 Received: from CY4PEPF0000EE30.namprd05.prod.outlook.com (2603:10b6:510:2da:cafe::15) by PH8PR02CA0042.outlook.office365.com (2603:10b6:510:2da::31) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.11 via Frontend Transport; Tue, 23 Dec 2025 12:14:28 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE30.mail.protection.outlook.com (10.167.242.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9456.9 via Frontend Transport; Tue, 23 Dec 2025 12:14:28 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:14:14 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:14:13 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 23 Dec 2025 04:14:06 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 05/11] ACPI: CPPC: add APIs and sysfs interface for min/max_perf Date: Tue, 23 Dec 2025 17:43:01 +0530 Message-ID: <20251223121307.711773-6-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251223121307.711773-1-sumitg@nvidia.com> References: <20251223121307.711773-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE30:EE_|CH3PR12MB8235:EE_ X-MS-Office365-Filtering-Correlation-Id: bc236c0f-5d28-4997-16e2-08de421cd24f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|1800799024|36860700013|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?rEwZEoMxbcAEUx6qBcxqEpjZ2Y+wuLASSADihnIXmuDUJfhsIK4cOnYsSzCP?= =?us-ascii?Q?KIvK6yKeVmjTzvb2/9xI40bo6aJ6IXtwUWHb9adf2C6r3V3UMDl3ucWT/7PZ?= =?us-ascii?Q?9jDwq1unW7SQVlVQ3RDtq4PmnAeKOP1jw6oQseG7OPSB466RyRSx9/eeOX6D?= =?us-ascii?Q?KogVW4O2dRg9W8OU4oplDpRe6kF+8kowohRc8VOSywvVVCfSuCI+LOSAFJK9?= =?us-ascii?Q?7VZXZdgQJOE7g3j3/sJYVKfKqMlbQzR+zsv9zKUz22c5BR9OeEW6AWfyzdqU?= =?us-ascii?Q?3ZRNTSQcgqTLLn9vFV63Z7fvJM37QiT4lLLdWn2nra2u0nNf1pcevw7GEuXL?= =?us-ascii?Q?V0AvAkDkY+F4TWGjMyj1XNzIz/lTlPSYrI91BhjpYE/DVsxSAW2x6vF6YpxB?= =?us-ascii?Q?86DzgHWEL7a1HWizprxmA/NpKUB059+AERCOMDVe6myoD5QqT/4Jip+18jvb?= =?us-ascii?Q?3b5nt/q75pblL3xiOWrXJx/wPuhKLKcws/d6GYicqNvyypXc6Z61sx9Q2AXT?= =?us-ascii?Q?opzYQdA9EPRHTN7d0JxelcpJSVoX949Fcfpkw8tPKj1Ox3BeJKKwZQv3iTF9?= =?us-ascii?Q?iQKfqSwafW4cMB7B0vWJLq84pXQSNaKZ1o89DedjzdeFQSHT5G/ppxKFnsx9?= =?us-ascii?Q?Jeb4Lb9cMOm93RJtenVc735UtD1nY/gFKVWH0bSA1XG5LFfKflwRY0yeszkN?= =?us-ascii?Q?coOr6EA2KGRAgZfVRMUDKicqlW0hRqXuJ7fHR2tN12iS4NAWCuCjBWYSX3ky?= =?us-ascii?Q?/vvfz+sT6z6e7bzwV/tdp2FKPkz1Hf7EDz6zASddONboHI9iw+Qx9BWXhVRl?= =?us-ascii?Q?SegnNvJNqnCUK09bDJZdwpM94Io6M9jFPDXbBMR5Tuc8/+cmrxtzZ8Gn0kXO?= =?us-ascii?Q?lv2MSRtIBVfi6GKIHjwidOq+fnh3meOH2MfEQAbXWMoPOk9HbfDTAUBDcqy0?= =?us-ascii?Q?KpjIGd4mx/jmO0Z5zQ2h1ReJlBDJ9p9Bp1PpdIhitUlewLzze1OB8HUhJYpR?= =?us-ascii?Q?9DKAT6JZapcSIijbz4oGDmItzpYTUn9yvrPQi5FaEoGEq5XbBZpchCzM+C8l?= =?us-ascii?Q?xrQWxlWzJLERQA8yu0Z+lL2Dil0IU+DdCwOQjAOoTJrm07bxPvMub9TaSy7L?= =?us-ascii?Q?oEJ54/claPrk3ciGALh4xD95Ev+qP0OVPOdZm5wkJc9Tog0BSPjQo25+W6Dn?= =?us-ascii?Q?C93wj7nmfrdfAQa3rGOKJyBTrp7U6ttLKZacQKoxQrtuEqchq88EwjbS3Qjy?= =?us-ascii?Q?s4lwqyhhzfFAKNeHGoYf+eiPIYd39dPNuTnUxI1JoJf3BjfgNDP+YfmJRZKz?= =?us-ascii?Q?DvcnWgBFbcv6EcsxRUqjuH5b+Vy7xnfkewpl8awkwwsulRLrhrkX4/SS1g0i?= =?us-ascii?Q?dfb8jKBjwpaYdR+agZLMW8M28OKD4t3c5yMFZmexVfMHFP98m5NxF3TFEU4w?= =?us-ascii?Q?9UyDw1YhQz8nuDvyuJAo7o23OucP/mPE3f3WceZpmmEh7dFXWoGYoFMwCFhZ?= =?us-ascii?Q?/kysN8X9RDDoQXkgZtDcyLwetC9tw0aEP6Z4yKxGYbQuAPXCc3ni+G2VoTIg?= =?us-ascii?Q?op6SwXcIFALpMz9aDZyi64/o3Ceu5SM39wuETVRv?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(1800799024)(36860700013)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Dec 2025 12:14:28.7048 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bc236c0f-5d28-4997-16e2-08de421cd24f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE30.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8235 Content-Type: text/plain; charset="utf-8" Add cppc_get/set_min_perf() and cppc_get/set_max_perf() APIs to read and write the MIN_PERF and MAX_PERF registers. Also add sysfs interfaces (min_perf, max_perf) in cppc_cpufreq driver to expose these controls to userspace. The sysfs values are in frequency (kHz) for consistency with other cpufreq sysfs files. A mutex is used to serialize sysfs store operations to ensure hardware register writes and perf_ctrls updates are atomic. Signed-off-by: Sumit Gupta --- drivers/acpi/cppc_acpi.c | 44 +++++++++ drivers/cpufreq/cppc_cpufreq.c | 160 +++++++++++++++++++++++++++++++++ include/acpi/cppc_acpi.h | 20 +++++ 3 files changed, 224 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 403ee988a8c6..9f28c20d902d 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1742,6 +1742,50 @@ int cppc_set_auto_sel(int cpu, bool enable) } EXPORT_SYMBOL_GPL(cppc_set_auto_sel); =20 +/** + * cppc_get_min_perf - Read minimum performance register. + * @cpu: CPU from which to read register. + * @min_perf: Return address. + */ +int cppc_get_min_perf(int cpu, u64 *min_perf) +{ + return cppc_get_reg_val(cpu, MIN_PERF, min_perf); +} +EXPORT_SYMBOL_GPL(cppc_get_min_perf); + +/** + * cppc_set_min_perf - Write minimum performance register. + * @cpu: CPU to which to write register. + * @min_perf: the desired minimum performance value to be updated. + */ +int cppc_set_min_perf(int cpu, u32 min_perf) +{ + return cppc_set_reg_val(cpu, MIN_PERF, min_perf); +} +EXPORT_SYMBOL_GPL(cppc_set_min_perf); + +/** + * cppc_get_max_perf - Read maximum performance register. + * @cpu: CPU from which to read register. + * @max_perf: Return address. + */ +int cppc_get_max_perf(int cpu, u64 *max_perf) +{ + return cppc_get_reg_val(cpu, MAX_PERF, max_perf); +} +EXPORT_SYMBOL_GPL(cppc_get_max_perf); + +/** + * cppc_set_max_perf - Write maximum performance register. + * @cpu: CPU to which to write register. + * @max_perf: the desired maximum performance value to be updated. + */ +int cppc_set_max_perf(int cpu, u32 max_perf) +{ + return cppc_set_reg_val(cpu, MAX_PERF, max_perf); +} +EXPORT_SYMBOL_GPL(cppc_set_max_perf); + /** * cppc_set_enable - Set to enable CPPC on the processor by writing the * Continuous Performance Control package EnableRegister field. diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index a87e7bb2e2f1..1e282dfabc76 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -28,6 +28,8 @@ =20 static struct cpufreq_driver cppc_cpufreq_driver; =20 +static DEFINE_MUTEX(cppc_cpufreq_update_autosel_config_lock); + #ifdef CONFIG_ACPI_CPPC_CPUFREQ_FIE static enum { FIE_UNSET =3D -1, @@ -538,6 +540,46 @@ static void populate_efficiency_class(void) } #endif =20 +/** + * cppc_cpufreq_set_mperf_limit - Set min/max performance limit + * @policy: cpufreq policy + * @val: performance value to set + * @is_min: true for min_perf, false for max_perf + */ +static int cppc_cpufreq_set_mperf_limit(struct cpufreq_policy *policy, u64= val, + bool is_min) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + struct cppc_perf_caps *caps =3D &cpu_data->perf_caps; + unsigned int cpu =3D policy->cpu; + u32 perf; + int ret; + + perf =3D clamp(val, caps->lowest_perf, caps->highest_perf); + + ret =3D is_min ? cppc_set_min_perf(cpu, perf) : + cppc_set_max_perf(cpu, perf); + if (ret) { + if (ret !=3D -EOPNOTSUPP) + pr_warn("Failed to set %s_perf (%llu) on CPU%d (%d)\n", + is_min ? "min" : "max", (u64)perf, cpu, ret); + return ret; + } + + if (is_min) + cpu_data->perf_ctrls.min_perf =3D perf; + else + cpu_data->perf_ctrls.max_perf =3D perf; + + return 0; +} + +#define cppc_cpufreq_set_min_perf(policy, val) \ + cppc_cpufreq_set_mperf_limit(policy, val, true) + +#define cppc_cpufreq_set_max_perf(policy, val) \ + cppc_cpufreq_set_mperf_limit(policy, val, false) + static struct cppc_cpudata *cppc_cpufreq_get_cpu_data(unsigned int cpu) { struct cppc_cpudata *cpu_data; @@ -896,16 +938,134 @@ store_energy_performance_preference_val(struct cpufr= eq_policy *policy, buf, count); } =20 +/** + * show_min_perf - Show minimum performance as frequency (kHz) + * @policy: cpufreq policy + * @buf: buffer to write the frequency value to + * + * Reads the MIN_PERF register and converts the performance value to + * frequency (kHz). + */ +static ssize_t show_min_perf(struct cpufreq_policy *policy, char *buf) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + u64 perf; + int ret; + + ret =3D cppc_get_min_perf(policy->cpu, &perf); + if (ret =3D=3D -EOPNOTSUPP) + return sysfs_emit(buf, "\n"); + if (ret) + return ret; + + /* Convert performance to frequency (kHz) for user */ + return sysfs_emit(buf, "%u\n", + cppc_perf_to_khz(&cpu_data->perf_caps, perf)); +} + +/** + * store_min_perf - Set minimum performance from frequency (kHz) + * @policy: cpufreq policy + * @buf: buffer containing the frequency value + * @count: size of @buf + * + * Converts the user-provided frequency (kHz) to a performance value + * and writes it to the MIN_PERF register. + */ +static ssize_t store_min_perf(struct cpufreq_policy *policy, const char *b= uf, + size_t count) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + unsigned int freq_khz; + u64 perf; + int ret; + + ret =3D kstrtouint(buf, 0, &freq_khz); + if (ret) + return ret; + + /* Convert frequency (kHz) to performance value */ + perf =3D cppc_khz_to_perf(&cpu_data->perf_caps, freq_khz); + + guard(mutex)(&cppc_cpufreq_update_autosel_config_lock); + ret =3D cppc_cpufreq_set_min_perf(policy, perf); + if (ret) + return ret; + + return count; +} + +/** + * show_max_perf - Show maximum performance as frequency (kHz) + * @policy: cpufreq policy + * @buf: buffer to write the frequency value to + * + * Reads the MAX_PERF register and converts the performance value to + * frequency (kHz). + */ +static ssize_t show_max_perf(struct cpufreq_policy *policy, char *buf) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + u64 perf; + int ret; + + ret =3D cppc_get_max_perf(policy->cpu, &perf); + if (ret =3D=3D -EOPNOTSUPP) + return sysfs_emit(buf, "\n"); + if (ret) + return ret; + + /* Convert performance to frequency (kHz) for user */ + return sysfs_emit(buf, "%u\n", + cppc_perf_to_khz(&cpu_data->perf_caps, perf)); +} + +/** + * store_max_perf - Set maximum performance from frequency (kHz) + * @policy: cpufreq policy + * @buf: buffer containing the frequency value + * @count: size of @buf + * + * Converts the user-provided frequency (kHz) to a performance value + * and writes it to the MAX_PERF register. + */ +static ssize_t store_max_perf(struct cpufreq_policy *policy, const char *b= uf, + size_t count) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + unsigned int freq_khz; + u64 perf; + int ret; + + ret =3D kstrtouint(buf, 0, &freq_khz); + if (ret) + return ret; + + /* Convert frequency (kHz) to performance value */ + perf =3D cppc_khz_to_perf(&cpu_data->perf_caps, freq_khz); + + guard(mutex)(&cppc_cpufreq_update_autosel_config_lock); + ret =3D cppc_cpufreq_set_max_perf(policy, perf); + if (ret) + return ret; + + return count; +} + cpufreq_freq_attr_ro(freqdomain_cpus); cpufreq_freq_attr_rw(auto_select); cpufreq_freq_attr_rw(auto_act_window); cpufreq_freq_attr_rw(energy_performance_preference_val); +cpufreq_freq_attr_rw(min_perf); +cpufreq_freq_attr_rw(max_perf); =20 static struct freq_attr *cppc_cpufreq_attr[] =3D { &freqdomain_cpus, &auto_select, &auto_act_window, &energy_performance_preference_val, + &min_perf, + &max_perf, NULL, }; =20 diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 2860a0252313..a49b50bddaf9 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -173,6 +173,10 @@ extern int cppc_get_auto_act_window(int cpu, u64 *auto= _act_window); extern int cppc_set_auto_act_window(int cpu, u64 auto_act_window); extern int cppc_get_auto_sel(int cpu, bool *enable); extern int cppc_set_auto_sel(int cpu, bool enable); +extern int cppc_get_min_perf(int cpu, u64 *min_perf); +extern int cppc_set_min_perf(int cpu, u32 min_perf); +extern int cppc_get_max_perf(int cpu, u64 *max_perf); +extern int cppc_set_max_perf(int cpu, u32 max_perf); extern int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf); extern int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator); extern int amd_detect_prefcore(bool *detected); @@ -265,6 +269,22 @@ static inline int cppc_set_auto_sel(int cpu, bool enab= le) { return -EOPNOTSUPP; } +static inline int cppc_get_min_perf(int cpu, u64 *min_perf) +{ + return -EOPNOTSUPP; +} +static inline int cppc_set_min_perf(int cpu, u32 min_perf) +{ + return -EOPNOTSUPP; +} +static inline int cppc_get_max_perf(int cpu, u64 *max_perf) +{ + return -EOPNOTSUPP; +} +static inline int cppc_set_max_perf(int cpu, u32 max_perf) +{ + return -EOPNOTSUPP; +} static inline int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf) { return -ENODEV; --=20 2.34.1 From nobody Sat Feb 7 17:56:00 2026 Received: from BN1PR04CU002.outbound.protection.outlook.com (mail-eastus2azon11010009.outbound.protection.outlook.com [52.101.56.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 449C0332EAC; Tue, 23 Dec 2025 12:14:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.56.9 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492084; cv=fail; b=Anu4OMIXaXRLmilGovnjytlqszC9bNoxACRESP3FrUS84RWBrQmwk/UiR4+o222HKzoD1wS4KD+sQq8Yf2Pcemw/tcS6C5HIvt0RIQBiKcGBWxKqWz0sUQ5pOHjB+I9O4wKiW16J1PkYqqv64yUmGK3ilh8Pjf+Ezcfkvy024os= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492084; c=relaxed/simple; bh=JRZ68RueAFuQnYFf6E3XDll2T/neYGf+7ny+bg7YGdU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hH+Ft2w4sxUpYknBUSMZfUS0QciYvweRNCL+T9c9bjwCFfECwcxj6JiMHU3ANRN8aOllIKVv2jU5QqeUaLrRElspuhzKSdRw/oKX6qd86K5bnepj+w574cjdOVtHPKOMXufyK+mSq+1LScCLRes7sRSRXhHtFQMypBOXwXk1Ob4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=RT6ySCbF; arc=fail smtp.client-ip=52.101.56.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="RT6ySCbF" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=VEC2PFCAxBZVE19IXjzEVnhvPW+JA5kH6iLCyWeP/t46iF48tH6RQTPOQGAoMbGFTgx4oKPkLiJ+JfVyYXLMMFHsheeAmDfuS8velqMJiVE78bgfvZPYEzKCHXJ4LDm4E4JAVZEbYE4tgax0JWCK+NkghZgVDCuSc3IUUQTGXz9xeDCBnNpEE0pqzYCXu0RXj0XRsSMKvZc5fwNb80jEk/EEya32sfCJnw9WvI2/cVCJ0DdQ5AtMhYXg88/ZYOaUCEG33Z0Xel+3seNKZfPYyFua8fVpnSq+PnhxHjElQzCxm159qpliXtpGEduKVtr4DBnUc83L3mcGNU55FsuO3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=RWpb7LQDzZCahscKXLyG+T/7DjUUqVakzKDNS2RWF20=; b=YalpOK0tBVBkM3wil0SzeCuzabSzrgtL+Z01rbOFwKwwWgQoItnVJG+7UJ+uyljrSi8Qac9d825vb7JNaSmE1FqNzcP0W0uGgWIWC3dPA7ALy6nZGNu3PUfvF7X91+k00VuwzTiYD3yvCGYWspzhEattukQXL7ZTwJkpC9wjfVjDBr1WAH43EliioL6H7VcWxyfW7YedQYrQPkDN2I0J2WG1BcjDTzsiV1HtihvwQjTqVfeywPL0OvofcojMjSiU2DfO526QQAlKrygHixEFABCjv3tIJWrzS03Ie0Jzokh/8MlM82DEumSlme7kSBCN6Zfjn13AQVbn79Vs4FQMLg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=RWpb7LQDzZCahscKXLyG+T/7DjUUqVakzKDNS2RWF20=; b=RT6ySCbFQE+0pKtjPjur0EmzZfIWcUnVcotKLPNbIn8skjaBctKElyMzmZnkVTmNb/23gScOIhB3WAeobZKeZQcIfOToU79iTGPlUVOe/pv2A0qHFtILRDtg5qXWJlRI0h4XiWp1pHWzUkaqgtbRwBKKDqCFQoSZ2SMqR3obi7cYCt1wSnjfBFwP83uvh5+OqUhTVbPDl1sVoHZ5Ms8fkbJfhCdi4A84CEsgV7Erhj5rNTJ9rctY6MZnckuNAL6HyzixvUc4NIj20p816835aZBNquOKCzKDyvdOliJxJY604rZD0OVkRu7Rb/MCRoSIrEf/4pUhtGzWPQ2h8dD0zQ== Received: from CYXP220CA0009.NAMP220.PROD.OUTLOOK.COM (2603:10b6:930:ee::17) by IA0PPFA19DE7612.namprd12.prod.outlook.com (2603:10b6:20f:fc04::bdd) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9456.11; Tue, 23 Dec 2025 12:14:34 +0000 Received: from CY4PEPF0000EE37.namprd05.prod.outlook.com (2603:10b6:930:ee:cafe::44) by CYXP220CA0009.outlook.office365.com (2603:10b6:930:ee::17) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9456.11 via Frontend Transport; Tue, 23 Dec 2025 12:14:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE37.mail.protection.outlook.com (10.167.242.43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9456.9 via Frontend Transport; Tue, 23 Dec 2025 12:14:34 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:14:23 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:14:22 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 23 Dec 2025 04:14:15 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 06/11] ACPI: CPPC: add APIs and sysfs interface for perf_limited Date: Tue, 23 Dec 2025 17:43:02 +0530 Message-ID: <20251223121307.711773-7-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251223121307.711773-1-sumitg@nvidia.com> References: <20251223121307.711773-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE37:EE_|IA0PPFA19DE7612:EE_ X-MS-Office365-Filtering-Correlation-Id: 7f81dfc7-5ac5-4208-40cc-08de421cd598 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|7416014|36860700013|376014|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?2e1qzUwN1HUA6VcK+a6YoNdfTaPnpllgz2hT/zMrDnrscFt9SWrqMjDVRDkW?= =?us-ascii?Q?sraQhdjZvKK+xFHvLa/jjWAqz4ejR2azRof5jeaRbHVwS5MI06JXRtJJbAZ8?= =?us-ascii?Q?3SJTsMgSQVWKeFeXZ9y0SWUBtBz7wLQl6I6kUjz7/9/zcld345IJtamWSlQ9?= =?us-ascii?Q?KOU4CGQhwBiG324DtzjqJtAIGf9iLKa6J/aSp0nwyNd1Hj9UPj3PpeipEv8B?= =?us-ascii?Q?7z0bGkR9G3CPtCW81WAJAo/t0JRFtZ6VGMmTo+y/qunYCU1CHbPvEYapWSc8?= =?us-ascii?Q?ihm6YttQE8lgtfXWJt8axr/mHLloioqAo99HdKTdo1jmapPGOJBPGhX64kkd?= =?us-ascii?Q?HsG7dOw2sBxE1yfc6HmHIJM3x2Oofz7M103D1LMj2oD9Ggwo1Og6osOvJXSF?= =?us-ascii?Q?h40psVA93dNEUfEhifCpZPhiRwvYv8RegEiS3btRhOCO0SCRYW4bmPkT3BVR?= =?us-ascii?Q?J1noDp0NsumbsN/Z8NP69nzKfXn+VtG+cW19G1LmACSOLNAGx4/l+0ZAKMWv?= =?us-ascii?Q?EagwdP4ssXpKX0bbQ2+UtGTi+fmTJeCQmDjsVGF4eqafSQjV31AYMSuhq8xo?= =?us-ascii?Q?RZ+8QV+8tnim43576ta/Sb1FcpDs95QlmO5bbJpX3Jc6Rq6BKT7XyuIbC+LI?= =?us-ascii?Q?cbwLR0J8RNCDxdCraUdSLDHiXwLTQnFU22x9J3BRf9eWGPGI0nKfQEFRYqlS?= =?us-ascii?Q?41ADI6LEJDyAG9eP09+Z/Xt+TqpvkxvLtonvrLrHbvi17vDwog+A8ZJogVyM?= =?us-ascii?Q?ereQ0ok0rwLjy8pbMuPJcMx7kgn6x98RGfR/0zvqRcmyFWi8D47/YhmecVXp?= =?us-ascii?Q?1dGbeoketplb8NQROlycDPD3emHGZVcnHfGZZ3osdVYNWk7+SS13vmQosQci?= =?us-ascii?Q?017wxzhluO/GkZ+M8N4mA3RtJ83MTIGY43MsXlCe7NfFeJDFlv1A2g04+ToM?= =?us-ascii?Q?gQ9U7wFT4bJK7wHgKlWYHd3CK9AGXqoRP0J/nx1gt4y7ESkUsL7P4WKBMGbT?= =?us-ascii?Q?OWM72A1m9cB6MOAgBH3C1tG72rU7XuBGxxlBF8jrc7h9Nksw3XM3q9n4ZK2s?= =?us-ascii?Q?vIdhvFGmvJA78QcMxAVcIucQ1VIv51nUAsh1DNdo5SJEhfufEGnYUtmK+17i?= =?us-ascii?Q?qEehIBElRU8DMnmVylJjdIrmH54Xpk0VwzGFrhIJIbdWZoHknTwnFvxxQKJ5?= =?us-ascii?Q?1d8JM8/+2y6yl+4IQzcoM5UwIQb+qf2CEpEebuuEIdi6UCA8uRwksEKOQciI?= =?us-ascii?Q?/HYqyYy8xGiyA7lpVhsTDzYDzb87C7PrCEUdc7PeyuukBFQkbdvc/4GDtRDv?= =?us-ascii?Q?LFLXchMywoH70mKTnMRxDp7N29GQlofsVIqYNam2quHWlMT0/vdr/WJqGXu3?= =?us-ascii?Q?i4d6ZGadbFhPgZVP0DDoFgLbxvAeUcM+JRIhCIKu6GJkH1iIAXCGMxapK99t?= =?us-ascii?Q?RdWUZdF1wAvYR81MGekBoLfWqa+3yFZQ/MjTijNa12QctlfVDc8Pc2hH+6yL?= =?us-ascii?Q?qwnpgJpWebG8Ut56ZmyC485RnDxlNuN4C8bLpnNTqtlaSsO5lkDFAMTK1WjL?= =?us-ascii?Q?fxvaStSeaxtFFiGjPSOp/jQEUwuA1vRheApVef+y?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(7416014)(36860700013)(376014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Dec 2025 12:14:34.2048 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7f81dfc7-5ac5-4208-40cc-08de421cd598 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE37.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PPFA19DE7612 Content-Type: text/plain; charset="utf-8" Add sysfs interface to read/write the Performance Limited register. The Performance Limited register indicates to the OS that an unpredictable event (like thermal throttling) has limited processor performance. It contains two sticky bits set by the platform: - Bit 0 (Desired_Excursion): Set when delivered performance is constrained below desired performance. Not used when Autonomous Selection is enabled. - Bit 1 (Minimum_Excursion): Set when delivered performance is constrained below minimum performance. These bits remain set until OSPM explicitly clears them. The write operation accepts a bitmask of bits to clear: - Write 1 to clear bit 0 - Write 2 to clear bit 1 - Write 3 to clear both bits This enables users to detect if platform throttling impacted a workload. Users clear the register before execution, run the workload, then check afterward - if set, hardware throttling occurred during that time window. The interface is exposed as: /sys/devices/system/cpu/cpuX/cpufreq/perf_limited Signed-off-by: Sumit Gupta --- drivers/acpi/cppc_acpi.c | 56 ++++++++++++++++++++++++++++++++++ drivers/cpufreq/cppc_cpufreq.c | 31 +++++++++++++++++++ include/acpi/cppc_acpi.h | 15 +++++++++ 3 files changed, 102 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 9f28c20d902d..ffd866c1c00d 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1786,6 +1786,62 @@ int cppc_set_max_perf(int cpu, u32 max_perf) } EXPORT_SYMBOL_GPL(cppc_set_max_perf); =20 +/** + * cppc_get_perf_limited - Get the Performance Limited register value. + * @cpu: CPU from which to get Performance Limited register. + * @perf_limited: Pointer to store the Performance Limited value. + * + * The returned value contains sticky status bits indicating platform-impo= sed + * performance limitations. + * + * Return: 0 for success, -EIO on failure, -EOPNOTSUPP if not supported. + */ +int cppc_get_perf_limited(int cpu, u64 *perf_limited) +{ + return cppc_get_reg_val(cpu, PERF_LIMITED, perf_limited); +} +EXPORT_SYMBOL_GPL(cppc_get_perf_limited); + +/** + * cppc_set_perf_limited() - Clear bits in the Performance Limited registe= r. + * @cpu: CPU on which to write register. + * @bits_to_clear: Bitmask of bits to clear in the perf_limited register. + * + * The Performance Limited register contains two sticky bits set by platfo= rm: + * - Bit 0 (Desired_Excursion): Set when delivered performance is constr= ained + * below desired performance. Not used when Autonomous Selection is en= abled. + * - Bit 1 (Minimum_Excursion): Set when delivered performance is constr= ained + * below minimum performance. + * + * These bits are sticky and remain set until OSPM explicitly clears them. + * This function only allows clearing bits (the platform sets them). + * + * Return: 0 for success, -EINVAL for invalid bits, -EIO on register + * access failure, -EOPNOTSUPP if not supported. + */ +int cppc_set_perf_limited(int cpu, u64 bits_to_clear) +{ + u64 current_val, new_val; + int ret; + + /* Only bits 0 and 1 are valid */ + if (bits_to_clear & ~CPPC_PERF_LIMITED_MASK) + return -EINVAL; + + if (!bits_to_clear) + return 0; + + ret =3D cppc_get_perf_limited(cpu, ¤t_val); + if (ret) + return ret; + + /* Clear the specified bits */ + new_val =3D current_val & ~bits_to_clear; + + return cppc_set_reg_val(cpu, PERF_LIMITED, new_val); +} +EXPORT_SYMBOL_GPL(cppc_set_perf_limited); + /** * cppc_set_enable - Set to enable CPPC on the processor by writing the * Continuous Performance Control package EnableRegister field. diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 1e282dfabc76..1f8825006940 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -1052,12 +1052,42 @@ static ssize_t store_max_perf(struct cpufreq_policy= *policy, const char *buf, return count; } =20 +/** + * show_perf_limited - Show Performance Limited register status + * @policy: cpufreq policy + * @buf: buffer to write the value to + * + * Read the Performance Limited register to check if platform throttling + * (thermal/power/current limits) occurred. + */ +static ssize_t show_perf_limited(struct cpufreq_policy *policy, char *buf) +{ + return cppc_cpufreq_sysfs_show_u64(policy->cpu, + cppc_get_perf_limited, buf); +} + +/** + * store_perf_limited - Clear Performance Limited register bits + * @policy: cpufreq policy + * @buf: buffer containing the bitmask of bits to clear + * @count: number of bytes in buf + * + * Write 1 to clear bit 0, 2 to clear bit 1, or 3 to clear both. + */ +static ssize_t store_perf_limited(struct cpufreq_policy *policy, + const char *buf, size_t count) +{ + return cppc_cpufreq_sysfs_store_u64(policy->cpu, + cppc_set_perf_limited, buf, count); +} + cpufreq_freq_attr_ro(freqdomain_cpus); cpufreq_freq_attr_rw(auto_select); cpufreq_freq_attr_rw(auto_act_window); cpufreq_freq_attr_rw(energy_performance_preference_val); cpufreq_freq_attr_rw(min_perf); cpufreq_freq_attr_rw(max_perf); +cpufreq_freq_attr_rw(perf_limited); =20 static struct freq_attr *cppc_cpufreq_attr[] =3D { &freqdomain_cpus, @@ -1066,6 +1096,7 @@ static struct freq_attr *cppc_cpufreq_attr[] =3D { &energy_performance_preference_val, &min_perf, &max_perf, + &perf_limited, NULL, }; =20 diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index a49b50bddaf9..57e04326a4b6 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -42,6 +42,11 @@ #define CPPC_EPP_PERFORMANCE_PREF 0x00 #define CPPC_EPP_ENERGY_EFFICIENCY_PREF 0xFF =20 +#define CPPC_PERF_LIMITED_DESIRED_EXCURSION BIT(0) +#define CPPC_PERF_LIMITED_MINIMUM_EXCURSION BIT(1) +#define CPPC_PERF_LIMITED_MASK (CPPC_PERF_LIMITED_DESIRED_EXCURSION | \ + CPPC_PERF_LIMITED_MINIMUM_EXCURSION) + /* Each register has the folowing format. */ struct cpc_reg { u8 descriptor; @@ -177,6 +182,8 @@ extern int cppc_get_min_perf(int cpu, u64 *min_perf); extern int cppc_set_min_perf(int cpu, u32 min_perf); extern int cppc_get_max_perf(int cpu, u64 *max_perf); extern int cppc_set_max_perf(int cpu, u32 max_perf); +extern int cppc_get_perf_limited(int cpu, u64 *perf_limited); +extern int cppc_set_perf_limited(int cpu, u64 perf_limited); extern int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf); extern int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator); extern int amd_detect_prefcore(bool *detected); @@ -285,6 +292,14 @@ static inline int cppc_set_max_perf(int cpu, u32 max_p= erf) { return -EOPNOTSUPP; } +static inline int cppc_get_perf_limited(int cpu, u64 *perf_limited) +{ + return -EOPNOTSUPP; +} +static inline int cppc_set_perf_limited(int cpu, u64 perf_limited) +{ + return -EOPNOTSUPP; +} static inline int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf) { return -ENODEV; --=20 2.34.1 From nobody Sat Feb 7 17:56:00 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013013.outbound.protection.outlook.com [40.93.201.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F2463314CC; Tue, 23 Dec 2025 12:14:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.13 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492092; cv=fail; b=rvyXeAmMvh7zKY5OxuVVkCxgvi9UvpE1f/kF9b3MnHoJeJyV50hzU1aBMdQa9QciEu+3w7ueArRQcdDPOtnfL4ymPu+Sv6TNYGgvPrVB9uGrYIKPPPLdsGJKZlqjHtJvT/28CXY6Z721D7EKj73NSfaZ9+tYcRFSVTpHXRhEU6Q= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492092; c=relaxed/simple; bh=fbIecVL9ld70PyE2O2TAg0Or49loBCDsvAvEN3kiYNw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WnPdxlBWngcKacydbvLaRwWnmQwkcKiihCSbdPkHGfwBG5a0QSE+Sp2OXcOfQTlzOyewamGw9341A1Tuoq/0nZ6xUkkQdhaA0FntzSWDbi6xgpmHqw9DVOHk/5pRwOig1Bj5aP//gfdrSvm+tpSXkOHTzL5t+rtvfxM4+HbCR1s= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=XkCK6erB; arc=fail smtp.client-ip=40.93.201.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="XkCK6erB" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=iRbiO9HzlvypBhXzci5+A/f7DoqCilU2DUMAV4ik2yGx0YO+hBw+cq4K/XJOzA76+i3GfAMOW+rziM0yW7mrWAsGTOKjW8QhSJiLwwNXjHsjx0mY2R1wtnCwo6mnVUg+dOYX2tITWjhfbU+XXgbKMa8V5+DKf8iuwCPURFuCEJNWjPe4gL8fGYpZ9CHdLNSpypCkr0hrnM1BGEGZLgZU+MiDT8q1sjSlrLGD72O/xd2HwVtKBtqcZkpzg48/cdBm/gF2tL/3ut5pA+MRNpNRt0OSukwZraHl8bXO3Xx6I9nfBw/LFXLpohBt+DHgKjz3To28vWHIoNqHlFI52LKSMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=7RcQ99u8HAYAQLy6Rf14H4VIjyENayglQU/Wgm7H+1w=; b=Uf1FehxgmBuSB+HQMmeciA4PFrm3v2Jjkgxw5Dlu/9mRuVKXAorRfi0rGlAQQXVQTVR36uH2KfbZ8L7zMt+RRvNa9CiFIOlM9RFvvM6XrZWxqWv5tpv/jt6LwIAEgM6jLS9Z05dZtKbneTqnYUJU9lz9VEgTn4Wu+Ky08xgCKgtYWDraI17yy/WvfYXKIhSfknBzDCH+7SPd/PytccpKlh/9nhZ3rR3sqneRcb8Cg1vVVKBaHVHmaf85BcznlyIuxjhKyrBGwSaSpHMm1zLj5qnrwzDyLhD6Mulq256CiAhLP1O1qeC+7YpmRdhEiG5aQP/CPYmyOazDdgWr3RgqxQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7RcQ99u8HAYAQLy6Rf14H4VIjyENayglQU/Wgm7H+1w=; b=XkCK6erBAEgUpQgIyatu7egJxD1G/+/232emL7OChumcvkxD+2B33vnDIbA+wOaekQTIqJW6UyAAdnxmJtBhA1guWE+/c7eELzft1LgWMZW0oLUCjjK9OwcLOUiFaXq9v5lusZO6ZDmtQD7IOD45HPXuTJuGNzFWufN/YPMqG8VEU8x3i905Ckzl/Y6psoceQbXE2JuEgW+oBAr1hJ6OWa5exJIBl3FwyiuHD4SJD7O0U4U2iWsCwykAs1WxWHFt0S2l0rD1ZG87UCqmA3jncypb95yHfAA25sCz8+xtPCVJ4kGVgdILf+Uu9DF3qhNTlFLQ6nFZjJVvHRS6ZgFoSg== Received: from BL1P223CA0001.NAMP223.PROD.OUTLOOK.COM (2603:10b6:208:2c4::6) by SA1PR12MB7442.namprd12.prod.outlook.com (2603:10b6:806:2b5::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9434.11; Tue, 23 Dec 2025 12:14:47 +0000 Received: from BL6PEPF0001AB72.namprd02.prod.outlook.com (2603:10b6:208:2c4:cafe::2a) by BL1P223CA0001.outlook.office365.com (2603:10b6:208:2c4::6) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.11 via Frontend Transport; Tue, 23 Dec 2025 12:14:14 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL6PEPF0001AB72.mail.protection.outlook.com (10.167.242.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9456.9 via Frontend Transport; Tue, 23 Dec 2025 12:14:47 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:14:32 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:14:31 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 23 Dec 2025 04:14:24 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 07/11] cpufreq: CPPC: Add sysfs for min/max_perf and perf_limited Date: Tue, 23 Dec 2025 17:43:03 +0530 Message-ID: <20251223121307.711773-8-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251223121307.711773-1-sumitg@nvidia.com> References: <20251223121307.711773-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB72:EE_|SA1PR12MB7442:EE_ X-MS-Office365-Filtering-Correlation-Id: b736fcda-47d7-4d85-7d69-08de421cdd97 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|1800799024|36860700013|376014|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?VhlTfhbKRqH5t5wkjLVMa+JjveqH5Mkx+4Mjt3G+dKq+O9d8E5vA3+EgtmvK?= =?us-ascii?Q?etj8ZbZYuncgkOjq9zyO6/4iD05/a9SKti9BmBuNbZbLVek06Vbvn+b+X9JK?= =?us-ascii?Q?nmIni5r9ICVSUAHNh1I6cMUvh3r5HgXXTRKyAxbvk2Y/fCU8zwAd5ReZGMjH?= =?us-ascii?Q?ppsMEE26BCEJ4la0X+C85VH02ZQ6VJh+LulotRAr6fAkrrUOJhGGIJmlGcv6?= =?us-ascii?Q?FobI8EEIp+V3VzGWB+4fCea2CnIBFOYlAyW/G5bxKUZ4dEDy59w6FQvtIjNO?= =?us-ascii?Q?dPoYGDjhrTXqHTWIriSVyVZ242Fg9KLoUgGTUjZzd84Up1uBbYTb1t4jj8yr?= =?us-ascii?Q?83XgilhmczwOCDsi8AYn2Th9b2tj9bqS2Qdnp6N1a6QBfpFnwZHAWupzjAXc?= =?us-ascii?Q?B4bSfuYn+Utk6Y8v8DM9GirMoML76CQs3f/LYJIOF/IPE4obsnWeYaSiGxCf?= =?us-ascii?Q?KC04kzVS66XmHTUa0f/QBnpCCq15s9C4JkIS/27I0zoLI//A/CmtJAEsCLzT?= =?us-ascii?Q?MRmYk0xBK1DokQzoWSXjWJG1VtpUYf9/sGaMym8Wnog5h0I6ZXAwtg4RX/BB?= =?us-ascii?Q?MoTzPpfggb8cSsDcB103SyTuOyodFpbCrFvSPLfaYXW/ot/GuOc2ujHdShh3?= =?us-ascii?Q?OHEaWtCAwQcRDh3Bnz4x3ojvJpvcsEVb7f2JRCgrZFhOnaNXe2TkZRBM5fik?= =?us-ascii?Q?jtUqA9gZ0OM5A0Pz+tD0/MwWZdGyXFtX4n7hF/L+FYQqQxjJDH2f1vBGGyUR?= =?us-ascii?Q?QroBL4oTEkWGwRkK14i7HympeQrUQ+63YDsXfL274Ny9/OSPLM4KKygZkG9+?= =?us-ascii?Q?z0ae+foKbRtZ23qT6Vf8i9kI6XyIonXVaPLZWvPDurZPIgK1enG3LBTfrjDk?= =?us-ascii?Q?ycJ2As17UHWbbnaN6B+tceXn+ScPIpzRi71l02jS1dxArfmk6j1w7hx7AAYr?= =?us-ascii?Q?RhXFRL/iHkBt1V7FF8pgO+CcUhEnt6Lx5DPvyrLMT8qKviYoV5SyfQViFZl9?= =?us-ascii?Q?AHHQOE5Y6XQ3UlifXjIT6EMMPCYjQOIZDhgCULOYFdNVBbEBYLrlh6mVettu?= =?us-ascii?Q?dkYPgZSnWIRvP/rVBGSE3RboLZzdDzCqec5EMzVO07cMVVm+ZfJobUoR8DFy?= =?us-ascii?Q?M1mOZDbnvWcEpi28ueWuLgGnnVZ4ymuiPCU8qzJEskvU4casNle9+d7jZYW6?= =?us-ascii?Q?d7gNObq/3BJMhUwsmfhVoM16A0FVLQfacwPyL7VwEr5FXKm+tcP/qyiwDdEd?= =?us-ascii?Q?ITpKH9X686Ye8A3HNg09/LP/1ggP+VHHyN1GHYf3liT8tGEj5mLSyyJyVg0q?= =?us-ascii?Q?gkxXYYOs0NJlYoMN7ht61Gptta3JS74WQAAnzHn58FWdJgmwUeaZ0SMKr6Uj?= =?us-ascii?Q?0QM8aF1TIcd+ou8hHBqnHNwPwLmw//l0diwbUOl3BnZZHg0nO2D2Olhs8g7j?= =?us-ascii?Q?aGyYAOc/7Cl9zxCG/RYJlX+8c8p1Dpn0ooF/MRGn2tOXEL5T5q8ZSxQlIl9j?= =?us-ascii?Q?n0ZnkgynGIr3rcs5w65NBbrtBIJ+XTHOy+XsFWT5zJFvFsOQkdh9n6mFM1og?= =?us-ascii?Q?QX883K03McxMgtjVubnZJ4hmpO0frJT6Wnq3mvzd?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(82310400026)(1800799024)(36860700013)(376014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Dec 2025 12:14:47.5437 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b736fcda-47d7-4d85-7d69-08de421cdd97 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB72.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7442 Content-Type: text/plain; charset="utf-8" Add sysfs interfaces for Minimum Performance, Maximum Performance and Performance Limited Register in the cppc_cpufreq driver. Reviewed-by: Randy Dunlap Signed-off-by: Sumit Gupta --- .../ABI/testing/sysfs-devices-system-cpu | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documenta= tion/ABI/testing/sysfs-devices-system-cpu index 3a05604c21bf..b022cbf46adc 100644 --- a/Documentation/ABI/testing/sysfs-devices-system-cpu +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -327,6 +327,48 @@ Description: Energy performance preference =20 This file is only present if the cppc-cpufreq driver is in use. =20 +What: /sys/devices/system/cpu/cpuX/cpufreq/min_perf +Date: February 2026 +Contact: linux-pm@vger.kernel.org +Description: Minimum Performance Frequency + + Read/write a frequency value in kHz from/to this file. This + file sets the minimum performance level (as frequency) at + which the platform may run. The frequency value is internally + converted to a performance value and must be in the range + [cpuinfo_min_freq, cpuinfo_max_freq], inclusive. + + This file is only present if the cppc-cpufreq driver is in use. + +What: /sys/devices/system/cpu/cpuX/cpufreq/max_perf +Date: February 2026 +Contact: linux-pm@vger.kernel.org +Description: Maximum Performance Frequency + + Read/write a frequency value in kHz from/to this file. This + file sets the maximum performance level (as frequency) at + which the platform may run. The frequency value is internally + converted to a performance value and must be in the range + [cpuinfo_min_freq, cpuinfo_max_freq], inclusive. + + This file is only present if the cppc-cpufreq driver is in use. + +What: /sys/devices/system/cpu/cpuX/cpufreq/perf_limited +Date: February 2026 +Contact: linux-pm@vger.kernel.org +Description: Performance Limited + + Read to check if platform throttling (thermal/power/current + limits) caused delivered performance to fall below the + requested level. A non-zero value indicates throttling occurred. + + Write the bitmask of bits to clear: + 1 =3D clear bit 0 (desired performance excursion) + 2 =3D clear bit 1 (minimum performance excursion) + 3 =3D clear both bits + The platform sets these bits; OSPM can only clear them. + + This file is only present if the cppc-cpufreq driver is in use. =20 What: /sys/devices/system/cpu/cpu*/cache/index3/cache_disable_{0,1} Date: August 2008 --=20 2.34.1 From nobody Sat Feb 7 17:56:00 2026 Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazon11010000.outbound.protection.outlook.com [52.101.61.0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C54EC3346B2; Tue, 23 Dec 2025 12:14:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.61.0 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492103; cv=fail; b=pKrdA7kDZZrVHqVeG4sDVJpSKvFa4XLJEZXPye3HsWckO9+FAGEOtpTnlJ45swSFx1Tty+fAmM+zBcwyQENd83VZbw5UdqfDarezk9CmfMAkBJ8nV55GEDaGW+Y8SpI9P3NM12kwjmHH5EqZaqw9DNk1kgEHRNtDSQ4naeoo64c= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492103; c=relaxed/simple; bh=WdODi1WmSm+IR+zLFmF2KeN7sKDOqRbMiZPmc1Uj6Ps=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=t/73Gt25ZGzSj5mLg1Z9/3r6aAIyCBFY0D79BnFhK/udizRfHIew/5FoJkQYWQbkt/hk+ho+UoKJzRm/fPHAHglxAc+1T+zi03xs/af2RxY6MdICE9axRXEpsbiGFHb915alVsGrxS8jCvphxNAoWzbBV0W6MBjCi+OuHZNbh44= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=OFp+1Opq; arc=fail smtp.client-ip=52.101.61.0 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="OFp+1Opq" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=vcakTAFiSbZ01Bc1L7ObNLWMfjzPias6gWQ695LLUlQ1gGNMXvLt/Kyu9QoaEpmCP1lxxGCo2avMaxYg9e63DQh5qzPewy8yJbuRmEEQAWbg9mCwBmUjhli6+xkZAMR+79KUuYLBubnSuLGeqquWHcL/JchAVY25Sw0LA7HN9bTzoxTNpe0MwMD7wT+/BB1KnwHLC3oXxaJ2iFkXhGHz8+UHhJATgPO8rwrILg7UwdednGpqTpMV3810zTdx7MA39ngX41G0guj1BaPvNCgAlp/e7SrQU+gKymp1V1cgjNyDdQeQ/8EhFR1G+qcx1l70x1D57OUOS9jetVO5zvn9lA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=032Lch60KVpKRCrGtT/1AV+RLGA1Ep7c9DfWPKoA40w=; b=vEoQ5dCsp/rrr2NPviC5/aBdcF+Er4GAF3TpjBrSxgv5JnzdToJO35ewvRoGEH7iN55tbuhn8asixAHAw6E3MMqHwA9MV5AFlnUN4PZWmm+lPYGswDdYophFkq6do/6KYvHZ9K3tQIidW27DvI4lt+tv1lsa/jRSTVulsjzEl24e2z7uwDj6UonZRw0YJwJ04WJIoCfHavl4cCiOKmyHnSfcmfvPJYp8OaLAa66V4pck22lh+zDiCZwV7rLlq3DLGc+Zfc8deGmBTk/62gVtu/mF55LAsp7Yuu0IHvlWiFrmuaAPQDd0d7T1N8JisDOYH9ALdpXqmE+UaO+i54Qslg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=032Lch60KVpKRCrGtT/1AV+RLGA1Ep7c9DfWPKoA40w=; b=OFp+1OpqdrKUFV+wqh0yHC055vVAtUZdJJh8E5k2R8DY2Ej82/7/Z+ni59TTHtDVBR0dijsJhFfFymf+Xjdam0MjJn+Xn4D1znF7U+lfKBw2VzAbWw/OOYGUKGhCTyaKX5sDli7z/cMpoaAt8D3BmeFEuzRrAR4mMefo+vR7/9g0UeQTxg4s4bOmB2ZOSRzprMpqXLkEAGXmKfDhofvTJGY1FR/gtSl1cjP31043rCOB+wlJQ6klKdVhzQzRyGB/tWueN+/t6i/Y5sFXlBkgRHhn+60ppAGsj8vQqX0jvlS+LaS3DF7GrgQ5PCpd9nqFYBP+TTztzRmbqQEpwy41uw== Received: from BLAPR03CA0173.namprd03.prod.outlook.com (2603:10b6:208:32f::35) by DS0PR12MB8479.namprd12.prod.outlook.com (2603:10b6:8:155::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9434.11; Tue, 23 Dec 2025 12:14:55 +0000 Received: from BL6PEPF0001AB75.namprd02.prod.outlook.com (2603:10b6:208:32f:cafe::44) by BLAPR03CA0173.outlook.office365.com (2603:10b6:208:32f::35) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.11 via Frontend Transport; Tue, 23 Dec 2025 12:14:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL6PEPF0001AB75.mail.protection.outlook.com (10.167.242.168) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9456.9 via Frontend Transport; Tue, 23 Dec 2025 12:14:55 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:14:41 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:14:40 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 23 Dec 2025 04:14:33 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 08/11] cpufreq: CPPC: sync policy limits when updating min/max_perf Date: Tue, 23 Dec 2025 17:43:04 +0530 Message-ID: <20251223121307.711773-9-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251223121307.711773-1-sumitg@nvidia.com> References: <20251223121307.711773-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB75:EE_|DS0PR12MB8479:EE_ X-MS-Office365-Filtering-Correlation-Id: 767b4306-eac8-4113-db47-08de421ce251 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|7416014|82310400026|376014|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?jScBhSt/YFn0tweJ6l/Zyl31psjp/JXgNxOE00QJB/7zuMGnkjvaDAAS/A0g?= =?us-ascii?Q?DPlEJaSC5JNKkkuj0XEk6RuBcdTFSB58i7gFCpmOkc0Pb0Yx0dIsoEe/XsEX?= =?us-ascii?Q?ziMUUa2C1DIN3qXlzuuUGf+tn3h2G2c8eHZuV48lZjCprM2oYgWRxwotvA5S?= =?us-ascii?Q?+Krt/E5ZgzEIYUGAqrGzWQMOtP94h+Do4odzQbglX5J1D4+IOTCtC+e4BVcL?= =?us-ascii?Q?k8aPnZZT7Xif9Pa4be2IkTiRU84PDXPnft4ehvRPOA+l3ZtqBUmvDqDXeZDZ?= =?us-ascii?Q?OSXYjcIST2GFPNSP+gPR6EvZDJZDMUC5avMXL8YQNylNCxYhikhNmnQGmm2P?= =?us-ascii?Q?1q+c0tNnT8iF0nPpgvc6zavYUa3POdL7z8qxI1ZhuXXPCGUsTQpJy4gtmrSu?= =?us-ascii?Q?zqOretkNoK4SV4J+NiASe8tDLhLt9WdwSVQ93WK3xHvL+IGALb5nbNSPId/F?= =?us-ascii?Q?zkGS/toyeCJIIBZWI8gV6sFyZhQTfZ+MRQx1MSdmu1eGZBM/LgR7geWpXst9?= =?us-ascii?Q?ktkS1xKF4e2NLdSZ+5mfJ/y6/O2qnjQTnTBfhLGDsQMujH3mRzOANMmDFqpf?= =?us-ascii?Q?oEFEa/MzYFC+lsOvNHBPFWrphwfauWH58SwYzUkAv9/G+umPR5H6iMpgNJx3?= =?us-ascii?Q?yy8NSZ/Ni7bWI8INBE1d+eeJ51oWTFNyRnnPqfz9q+VeZD54/orpMncRDPcr?= =?us-ascii?Q?uXixu7UBW2n7N62889gKPMrZcTd7GIA91RIdkTpq4hjklsCe9Sbd/YZ1/xW3?= =?us-ascii?Q?1YCLPH3NeO026kJEex36ad5SttO8FLKZDLApSrzHgqzoEDpDbk/VjD6suNUz?= =?us-ascii?Q?SgIYTflyyvY5WVqTT/CWFSxJyL8KCJ9w10wH7q+70BGa/iiZKAvfngPEnkCi?= =?us-ascii?Q?lkgYt3OcfIOBCRT8cVFXrho3JHqEyipxOv4vf4MzZlgR9LKarwI+B48TT/CO?= =?us-ascii?Q?aYUGfKXTLNIxOjrmkXiHoByGZ8bhx+R8pxtoAvsSss6CyQxank0NyiFjX8pH?= =?us-ascii?Q?6tgtUdcDyhlx9hIiuMKWRVFE6DyQOHFCt5bnYK/GSrjlKN8qg8lepOcVvQIB?= =?us-ascii?Q?lm8om12eFoc9Wc8A4N1O0pAU7WKIXQK4Ssyjmka5FOwxS31Ok81Nf3G9RkOf?= =?us-ascii?Q?LC9Exm5OiPf4SvQk5otGQnh0Ta8VtABS6i/QWkgWtKZSp0CXLgtBPDNOsqpy?= =?us-ascii?Q?Fe0CW8hNg7E+jE0az0RkQI6OD4zXaq6CypBLNcSN8ecPTbpV49nGYgSP7p+t?= =?us-ascii?Q?i4VrAMoHqv0JJdDg/JJn0FxGXoL6ktqhI6kGCOQCurFwe74vtwiyAUWbaK/y?= =?us-ascii?Q?k/PgjiEjpOu1cEexBqylZA/W/GDkXGenzIwWZr+oqb+TdndTRUV8tWyjsTqz?= =?us-ascii?Q?ODU4GwcaG+QQ+rJOWOL318wdkwH4PuzhZYOqKfCBc8/+abafvomfPfqtTi6x?= =?us-ascii?Q?vbgQwG5jOvoTJJak3YClRsTXINtdRmyNCKgwmSu7yxbo9ziNS3IbgpA0pQ5O?= =?us-ascii?Q?5yBMOoD5YT1lBg/X42RzsmEOsoxWzZ46riYpBoFFViqRAr7+6sUy8rcaDIzm?= =?us-ascii?Q?3YOjiolDQuDRJnE12rH0e5+ZnTVc9JAR+pNrce/3?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(7416014)(82310400026)(376014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Dec 2025 12:14:55.4786 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 767b4306-eac8-4113-db47-08de421ce251 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB75.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8479 Content-Type: text/plain; charset="utf-8" When min_perf or max_perf is updated via sysfs in autonomous mode, the policy frequency limits should also be updated to reflect the new performance bounds. Add @update_policy parameter to cppc_cpufreq_set_mperf_limit() to control whether policy constraints are synced with HW registers. The policy is updated only when autonomous selection is enabled to keep SW limits in sync with HW. This ensures that scaling_min_freq and scaling_max_freq values remain consistent with the actual min/max_perf register values when operating in autonomous mode. Signed-off-by: Sumit Gupta --- drivers/cpufreq/cppc_cpufreq.c | 35 ++++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 1f8825006940..0202c7b823e6 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -544,14 +544,20 @@ static void populate_efficiency_class(void) * cppc_cpufreq_set_mperf_limit - Set min/max performance limit * @policy: cpufreq policy * @val: performance value to set + * @update_policy: whether to update policy constraints * @is_min: true for min_perf, false for max_perf + * + * When @update_policy is true, updates cpufreq policy frequency limits. + * @update_policy is false during cpu_init when policy isn't fully set up. */ static int cppc_cpufreq_set_mperf_limit(struct cpufreq_policy *policy, u64= val, - bool is_min) + bool update_policy, bool is_min) { struct cppc_cpudata *cpu_data =3D policy->driver_data; struct cppc_perf_caps *caps =3D &cpu_data->perf_caps; unsigned int cpu =3D policy->cpu; + struct freq_qos_request *req; + unsigned int freq; u32 perf; int ret; =20 @@ -571,15 +577,26 @@ static int cppc_cpufreq_set_mperf_limit(struct cpufre= q_policy *policy, u64 val, else cpu_data->perf_ctrls.max_perf =3D perf; =20 + if (update_policy) { + freq =3D cppc_perf_to_khz(caps, perf); + req =3D is_min ? policy->min_freq_req : policy->max_freq_req; + + ret =3D freq_qos_update_request(req, freq); + if (ret < 0) { + pr_warn("Failed to update %s_freq constraint for CPU%d: %d\n", + is_min ? "min" : "max", cpu, ret); + return ret; + } + } + return 0; } =20 -#define cppc_cpufreq_set_min_perf(policy, val) \ - cppc_cpufreq_set_mperf_limit(policy, val, true) - -#define cppc_cpufreq_set_max_perf(policy, val) \ - cppc_cpufreq_set_mperf_limit(policy, val, false) +#define cppc_cpufreq_set_min_perf(policy, val, update_policy) \ + cppc_cpufreq_set_mperf_limit(policy, val, update_policy, true) =20 +#define cppc_cpufreq_set_max_perf(policy, val, update_policy) \ + cppc_cpufreq_set_mperf_limit(policy, val, update_policy, false) static struct cppc_cpudata *cppc_cpufreq_get_cpu_data(unsigned int cpu) { struct cppc_cpudata *cpu_data; @@ -988,7 +1005,8 @@ static ssize_t store_min_perf(struct cpufreq_policy *p= olicy, const char *buf, perf =3D cppc_khz_to_perf(&cpu_data->perf_caps, freq_khz); =20 guard(mutex)(&cppc_cpufreq_update_autosel_config_lock); - ret =3D cppc_cpufreq_set_min_perf(policy, perf); + ret =3D cppc_cpufreq_set_min_perf(policy, perf, + cpu_data->perf_ctrls.auto_sel); if (ret) return ret; =20 @@ -1045,7 +1063,8 @@ static ssize_t store_max_perf(struct cpufreq_policy *= policy, const char *buf, perf =3D cppc_khz_to_perf(&cpu_data->perf_caps, freq_khz); =20 guard(mutex)(&cppc_cpufreq_update_autosel_config_lock); - ret =3D cppc_cpufreq_set_max_perf(policy, perf); + ret =3D cppc_cpufreq_set_max_perf(policy, perf, + cpu_data->perf_ctrls.auto_sel); if (ret) return ret; =20 --=20 2.34.1 From nobody Sat Feb 7 17:56:00 2026 Received: from BN1PR04CU002.outbound.protection.outlook.com (mail-eastus2azon11010051.outbound.protection.outlook.com [52.101.56.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06E8D338925; Tue, 23 Dec 2025 12:15:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.56.51 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492114; cv=fail; b=F7XiQ1acTxNYIGwN5eqmVZTmCr5MDRrcz1l6xqtjCmIl3RMiU57o0QPf7puC3avYO2ERRlRm+ZO7k2vGtIRrYZzuGomD/YhR+XgZG6J++nT3jU3AfnQgvsYeZQA1+PBgbvGaNqgqMHkxKe17GFN9ZSjUPHhuEDolw16oMrzNyss= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492114; c=relaxed/simple; bh=Mq0090VypYrNCoveLUnonXSbgQBzkp6V2UypJ7GAPtg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BEH4pL5n8xYM3cvEauLbzPlm6qg2XijGTTp+6ZqSEv99sGCq21uWpHq8uF0MTsMtIutLpRJhP88kROkev4olng2t/2zj5fyAcXCS35a1Vv8k4/JmiYfelJc4U13n7Ri3SuxJloUrVuMjrQgeV3V2Tz8qt56X8vAFOBPCKIkOnCc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=cFOD2kpS; arc=fail smtp.client-ip=52.101.56.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="cFOD2kpS" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=y8SwITT3ZuSVJjq9MWTW8nsPZCle7U6Efby1wZ5wowYExVWS+m2tm/cI4gBKig3o2K7T/+osZ0ZmYq4Q3l6O0s+KEsfRqUeZCweG5O8cG1JBr6V32mFQ4iLbwbROz2g7DkoPck68KEVTS5g4RIF4PVvnBJhV5nJHLgbis2Va83NgNcpVKuRV6JBzd5w9aTE5/47aJZ6iWxJ2xjRgCQcv4zeQkHdkPlXzr0olcvM2dFUvFTkXi9NA/RxTSk9fGkgrLwqDFryV9I7h/2mMobIDO3EJtYiELicB0Bi+7+bnW3nhl8J0x/F/6JeHOgMXJxMn26dprF/XZDSANrQx67d7qA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PZt1BFpFuKzS++SiUMz9Xsp97XlHfnnqGxV31r5Rbf4=; b=FzL/uovk3lpNDIZ9mUjM01XqUvchB8QIKyIMx0IHQY2fcjY3qaCIUg8mKkvqINAtNjA1wAKFXZg12hPFwqwDUVLNZO/g3IeIzuXjNhCBQrt3+1Zm+3iyU2oT08dCQ74jbIyCjC0P0XK9R/LFJRJpljQD3gDeyD9wIEAW9LDLKetXC0dCZ5bqLnGOhtXZ9t28eX1zMWRfUFftX3glEP1YbCjFDeYHLC7yYMzX0rycAITb0Qr6mNvi6ntJelQpz3y4S7n7jj90K4diPa3YAD7Js8NKbDJ2tpUEHv3hzxMAe1wnH5xS3d/2z659Kt5Du6ZpeRpnAbm/sqhAGLl/ZabM2A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PZt1BFpFuKzS++SiUMz9Xsp97XlHfnnqGxV31r5Rbf4=; b=cFOD2kpSs9Y3KT51+ZZbUW3I5GxTPAUSRFNqWtuJ6mQEaT3MOqCYpLdg0F7EqsXJTlk8+2FHcnx6Yof4WdZJHWDNd2P7jluyp/ciJhgEad4qXakP34ZHISOvbA2maEsXRbRnk+UPk2X0y/aMKOB4eg3COI6Ww6hYzAJDAR+FVwUH4kGDsQvmm+pGnz9aakwWFTbdVDtcBimYyOhTMObDG1N50BplOqEUlU8HNLllZ2afy4/70qpOCmEz68Ba2m4NyWryGsualQyZtrF8x+KYE6Xt579rN0yq8htw867RupfYmoJDEUaExW4JHWFBoRMfo4sgqup4mTMmD2SP6K5QqQ== Received: from CY5PR15CA0172.namprd15.prod.outlook.com (2603:10b6:930:81::15) by BY5PR12MB4097.namprd12.prod.outlook.com (2603:10b6:a03:213::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9456.11; Tue, 23 Dec 2025 12:15:02 +0000 Received: from CY4PEPF0000EE35.namprd05.prod.outlook.com (2603:10b6:930:81:cafe::95) by CY5PR15CA0172.outlook.office365.com (2603:10b6:930:81::15) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9456.10 via Frontend Transport; Tue, 23 Dec 2025 12:15:01 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE35.mail.protection.outlook.com (10.167.242.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9456.9 via Frontend Transport; Tue, 23 Dec 2025 12:15:02 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:14:51 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:14:50 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 23 Dec 2025 04:14:43 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 09/11] cpufreq: CPPC: sync policy limits when toggling auto_select Date: Tue, 23 Dec 2025 17:43:05 +0530 Message-ID: <20251223121307.711773-10-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251223121307.711773-1-sumitg@nvidia.com> References: <20251223121307.711773-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE35:EE_|BY5PR12MB4097:EE_ X-MS-Office365-Filtering-Correlation-Id: d4e26f29-eff5-4ddf-b65c-08de421ce628 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700013|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?+GnMo7nsp7pGfWMOOTdKUGfKHVYwhLjKFz7msjYuj1N5zS8Wn0XnxpSkLV++?= =?us-ascii?Q?ECpqImUUG4Srka5HuLOZK3pSJ7/n7Ryysqf15m8ZjG59KFYvfZEVhbRLQAYi?= =?us-ascii?Q?zx3PXfeHeD24tOYH32NQxjryS50IC7l9hPRzFL3Ha7VfIcl/gg/e6y/Z3621?= =?us-ascii?Q?2RvzEuWguwgiS+MmTC4gS4FwFUFdt6cNQPQILi9JAGa0C/8DDG+0pjROPjQN?= =?us-ascii?Q?xyz9Wel2arYQVhg/Gw9echQNxnF2udRRn2mQaIMMnGA/PN8GU+bf3AHhUfoY?= =?us-ascii?Q?+nNWP3duVnKQ5uYmklFmMQXV6cEO7KPxM59SjEATcyyr73lAoEnl29p1a8Rt?= =?us-ascii?Q?PhahU5BZ3Cx8YJ3rQ57jeFFKDEZ2AlY0m/zCypNt0mceJ7X1cS6zPc6QlAoY?= =?us-ascii?Q?uNWpwkyQWlsnEKY6psgXlt58wLGVIxDpp9cxJbxA9OLTjFD0v8XRSa15AVBm?= =?us-ascii?Q?RZvaqvKqokKFkrpdADhLqofxbNG89paDtjbsjKSihtETUszfB3vPZiA7xyc7?= =?us-ascii?Q?Mf7VREe07aCX2RDSt8AbUpzDCEM3HgO/A7gVkc7aiaPLKiv7HaYdXKOeVVha?= =?us-ascii?Q?9z4hH8/mNm0rvTGibr70tSYrczMptE42CPrkBtKSYhtAahyaeTI3In/tt+j3?= =?us-ascii?Q?fhqM1quWhwsWyQuqDJ83ywdvrjfgzGMOqiOjlFxYezLzcQfVZeznFCFoq/6l?= =?us-ascii?Q?mZA09hKb9tCi+oC2rF8DuForPW3j/scWM2LbOkRn7+w+QusbV+unoxE8z3pQ?= =?us-ascii?Q?wBG4yUNjdQvZC5yvPoVBQZykGmypmTECoiDvUOpkjlc3EDwyeH2wD6oWnfXn?= =?us-ascii?Q?A0Eqx/dxNHBbWjVkJbMlwpTnU8LHiy969C/J1qiM4leovrCOT51DYWCahLfq?= =?us-ascii?Q?ra4kdbY2H/yIpjF3L9vOg9Q1QUe2RrhZwfQDwzup+gqe50eB7i4rrHpI71yu?= =?us-ascii?Q?prSNto9eUegKWwzWnq47aLOKws7kOEVpJ+Yj0BetKFsh5zhhPseekIjOskYL?= =?us-ascii?Q?fmB0DYthsRBhHz2K62+7++Z3EYTUs5bFkmJd14PHMFQvSvNegzR4UP9y61pZ?= =?us-ascii?Q?upd4E6tpGpUUih2sfxVzIrxsel1Zt8awB+9lwAW3v1iqpiWD+8EHABcj/0XT?= =?us-ascii?Q?7wFJTiwmdGIcljHCAh/5g6wpNet/weBTqlr8mk3jABn41zX/9Bq8Xa7fAAjw?= =?us-ascii?Q?y94osSwun5Bdx017Xc03X+1kNo9gelpIJWRGNdOVXhQK3U8uR1nho7L6PiaE?= =?us-ascii?Q?Cd6brRtXcLXmklYJFwWDxJFcjco6vUXTvvVS1QCJPxi2OF2/G9HyOPEKvkcP?= =?us-ascii?Q?TgGmvMgkFooQwyrtO2UBB8ivGZhgH7UKZAvrH8LDbP2KtGmx82YuTotvn8w1?= =?us-ascii?Q?//yodXwAuYclg88x5f07FHl7BQJ5IrjJig874x9KTCYAwZWoHnAq2eVQx9dx?= =?us-ascii?Q?8VW5vLXoRTq6ha/bYweN+3PGaO+RRYj2Gq6z1udcU4dZb49S9VcFG2HdPBn8?= =?us-ascii?Q?Mi3Cn5x9sWOOex/sCvkfDPc689nOp/GD2zg3/vHR7CnNFys/QhB3N3oBRWXa?= =?us-ascii?Q?KPCWiG1a0mvSSP7Z5xI=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(1800799024)(36860700013)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Dec 2025 12:15:02.0070 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d4e26f29-eff5-4ddf-b65c-08de421ce628 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE35.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4097 Content-Type: text/plain; charset="utf-8" When CPPC autonomous selection (auto_select) is enabled or disabled, the policy min/max frequency limits should be updated appropriately to reflect the new operating mode. Currently, toggling auto_select only changes the hardware register but doesn't update the cpufreq policy constraints, which can lead to inconsistent behavior between the hardware state and the policy limits visible to userspace. Add cppc_cpufreq_update_autosel_config() function to handle the auto_select toggle by syncing min/max_perf values with policy constraints. When enabling auto_sel, restore preserved min/max_perf values to policy limits. When disabling, reset policy to defaults while preserving hardware register values for later use. Signed-off-by: Sumit Gupta --- drivers/cpufreq/cppc_cpufreq.c | 112 +++++++++++++++++++++++++++------ 1 file changed, 92 insertions(+), 20 deletions(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 0202c7b823e6..b1f570d6de34 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -544,14 +544,20 @@ static void populate_efficiency_class(void) * cppc_cpufreq_set_mperf_limit - Set min/max performance limit * @policy: cpufreq policy * @val: performance value to set + * @update_reg: whether to update hardware register * @update_policy: whether to update policy constraints * @is_min: true for min_perf, false for max_perf * + * When @update_reg is true, writes to HW registers and preserves values. * When @update_policy is true, updates cpufreq policy frequency limits. + * + * @update_reg is false when disabling auto_sel to preserve HW values. + * The preserved value is used on next enabling of the autonomous mode. * @update_policy is false during cpu_init when policy isn't fully set up. */ static int cppc_cpufreq_set_mperf_limit(struct cpufreq_policy *policy, u64= val, - bool update_policy, bool is_min) + bool update_reg, bool update_policy, + bool is_min) { struct cppc_cpudata *cpu_data =3D policy->driver_data; struct cppc_perf_caps *caps =3D &cpu_data->perf_caps; @@ -563,19 +569,22 @@ static int cppc_cpufreq_set_mperf_limit(struct cpufre= q_policy *policy, u64 val, =20 perf =3D clamp(val, caps->lowest_perf, caps->highest_perf); =20 - ret =3D is_min ? cppc_set_min_perf(cpu, perf) : - cppc_set_max_perf(cpu, perf); - if (ret) { - if (ret !=3D -EOPNOTSUPP) - pr_warn("Failed to set %s_perf (%llu) on CPU%d (%d)\n", - is_min ? "min" : "max", (u64)perf, cpu, ret); - return ret; - } + if (update_reg) { + ret =3D is_min ? cppc_set_min_perf(cpu, perf) : + cppc_set_max_perf(cpu, perf); + if (ret) { + if (ret !=3D -EOPNOTSUPP) + pr_warn("CPU%d: set %s_perf=3D%llu failed (%d)\n", + cpu, is_min ? "min" : "max", + (u64)perf, ret); + return ret; + } =20 - if (is_min) - cpu_data->perf_ctrls.min_perf =3D perf; - else - cpu_data->perf_ctrls.max_perf =3D perf; + if (is_min) + cpu_data->perf_ctrls.min_perf =3D perf; + else + cpu_data->perf_ctrls.max_perf =3D perf; + } =20 if (update_policy) { freq =3D cppc_perf_to_khz(caps, perf); @@ -592,11 +601,74 @@ static int cppc_cpufreq_set_mperf_limit(struct cpufre= q_policy *policy, u64 val, return 0; } =20 -#define cppc_cpufreq_set_min_perf(policy, val, update_policy) \ - cppc_cpufreq_set_mperf_limit(policy, val, update_policy, true) +#define cppc_cpufreq_set_min_perf(policy, val, update_reg, update_policy) = \ + cppc_cpufreq_set_mperf_limit(policy, val, update_reg, update_policy, \ + true) + +#define cppc_cpufreq_set_max_perf(policy, val, update_reg, update_policy) = \ + cppc_cpufreq_set_mperf_limit(policy, val, update_reg, update_policy, \ + false) + +/** + * cppc_cpufreq_update_autosel_config - Update autonomous selection config + * @policy: cpufreq policy + * @is_auto_sel: enable/disable autonomous selection + * + * Return: 0 on success, negative error code on failure + */ +static int cppc_cpufreq_update_autosel_config(struct cpufreq_policy *polic= y, + bool is_auto_sel) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + struct cppc_perf_caps *caps =3D &cpu_data->perf_caps; + u64 min_perf =3D caps->lowest_nonlinear_perf; + u64 max_perf =3D caps->nominal_perf; + unsigned int cpu =3D policy->cpu; + bool update_reg =3D is_auto_sel; + bool update_policy =3D true; + int ret; + + guard(mutex)(&cppc_cpufreq_update_autosel_config_lock); + + if (is_auto_sel) { + /* Use preserved values if available, else use defaults */ + if (cpu_data->perf_ctrls.min_perf) + min_perf =3D cpu_data->perf_ctrls.min_perf; + if (cpu_data->perf_ctrls.max_perf) + max_perf =3D cpu_data->perf_ctrls.max_perf; + } + + /* + * Set min/max performance and update policy constraints. + * When enabling: update both HW registers and policy. + * When disabling: update policy only, preserve HW registers. + * Continue even if min/max are not supported, as EPP and autosel + * might still be supported. + */ + ret =3D cppc_cpufreq_set_min_perf(policy, min_perf, update_reg, + update_policy); + if (ret && ret !=3D -EOPNOTSUPP) + return ret; + + ret =3D cppc_cpufreq_set_max_perf(policy, max_perf, update_reg, + update_policy); + if (ret && ret !=3D -EOPNOTSUPP) + return ret; + + /* Update auto_sel register */ + ret =3D cppc_set_auto_sel(cpu, is_auto_sel); + if (ret && ret !=3D -EOPNOTSUPP) { + pr_warn("Failed to set auto_sel=3D%d for CPU%d (%d)\n", + is_auto_sel, cpu, ret); + return ret; + } + if (!ret) + cpu_data->perf_ctrls.auto_sel =3D is_auto_sel; + + return 0; +} + =20 -#define cppc_cpufreq_set_max_perf(policy, val, update_policy) \ - cppc_cpufreq_set_mperf_limit(policy, val, update_policy, false) static struct cppc_cpudata *cppc_cpufreq_get_cpu_data(unsigned int cpu) { struct cppc_cpudata *cpu_data; @@ -889,7 +961,7 @@ static ssize_t store_auto_select(struct cpufreq_policy = *policy, if (ret) return ret; =20 - ret =3D cppc_set_auto_sel(policy->cpu, val); + ret =3D cppc_cpufreq_update_autosel_config(policy, val); if (ret) return ret; =20 @@ -1005,7 +1077,7 @@ static ssize_t store_min_perf(struct cpufreq_policy *= policy, const char *buf, perf =3D cppc_khz_to_perf(&cpu_data->perf_caps, freq_khz); =20 guard(mutex)(&cppc_cpufreq_update_autosel_config_lock); - ret =3D cppc_cpufreq_set_min_perf(policy, perf, + ret =3D cppc_cpufreq_set_min_perf(policy, perf, true, cpu_data->perf_ctrls.auto_sel); if (ret) return ret; @@ -1063,7 +1135,7 @@ static ssize_t store_max_perf(struct cpufreq_policy *= policy, const char *buf, perf =3D cppc_khz_to_perf(&cpu_data->perf_caps, freq_khz); =20 guard(mutex)(&cppc_cpufreq_update_autosel_config_lock); - ret =3D cppc_cpufreq_set_max_perf(policy, perf, + ret =3D cppc_cpufreq_set_max_perf(policy, perf, true, cpu_data->perf_ctrls.auto_sel); if (ret) return ret; --=20 2.34.1 From nobody Sat Feb 7 17:56:00 2026 Received: from PH7PR06CU001.outbound.protection.outlook.com (mail-westus3azon11010058.outbound.protection.outlook.com [52.101.201.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF1E632827D; Tue, 23 Dec 2025 12:15:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.201.58 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492125; cv=fail; b=qyEJG96LTfXNgK0VrO8Vi14RHM0QyyoFU/E4f9kB0oAa2k8p75sjhEdZanLJbISjo3RlS4gL5Fkynjr6W+pwkki5PscZc1C+7sYi2cDEPc912QqriE8u+ZqbBy4CNOrMjc2j/yUcB903t55nPFTyautVPoUUGq4R4RZlQqReJ4Y= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492125; c=relaxed/simple; bh=DtJjOQ4nYqxkDJTvrGFeE+9ZOkBkpKo2cTbXRK4uSZg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=l+B+ENwTXy31bd9disM1UOlpUD2RKlXxk15h3IFW3y+OhHMbA1vRzDTzNY58UO/fbHz+1T8I1USQIX0ik7aO7Sb9uRVcXbUKDk2LXoNcljFlQ+81xhWxroherYRYH2nH8ndCl/QVsYshy92seu6lT0p/NnV9VkH36wnJZPwEfoc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=UhQ7WzZ1; arc=fail smtp.client-ip=52.101.201.58 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="UhQ7WzZ1" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=bXEHPlQNbbwqrvBRPUGvV97mZ+3Fv7x45WuA71V45lSqG0VVuDCjJJmpgH9Rg4HEwiFej1zY6REc1unniUvm6I6GqgSPlW/EMDbDJ2JhNFlhJ5MUrYaSnMfuYhVYfTpbPmtbIrilqKsHnSQQ1hoNAtrMmPiEqI9wt4vzVixbQ0wOdBpfcBBFMTfYpUe+RZ1Em6gvrMJDisVsXE1QOp0Adv8+sbeHoXwF7N+3wtSu3XjEcyoNnF2/A2mP5S9t+WOcvHC7HVKr4tqYFQqmCD6lFEf7eG3l8v5ub5U33k5gUoOcrF6RZSjWigt2pPwu6FHKUSO4NiREvbtrvWr8OlRVxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Pc6pR+hLCr4FNbuTi0xCuzjZuNeWKYe560pw+1crU2w=; b=KqailBJNm/8fc87ehDGUq2dKmFtbhOgl6KJ9aeCYf8oI3pJAItoDbJm7J1pboQFAOD6TtttfcT58efj4NATlfCYHPfYWMKmQfsvgS+flDNnjTIpImo4ZmNeqwiHJYgYlmMMV6oKiWnr4UVH2sKldizkGqFuNgsHNaiM9cF7Pd0h5tWtBjD7ypFlDtD2H0sRtYvYu9rMMBNDbPoJasidkr50d6uWccwAgTPFmSbuUl7phyrylOb4Lhc0voNvEakvm8v1UrOvsIOdGaP5RPyQwedrMvLt9GsWDBtTFrcX8667dax9AVScMPF63FJaCnAW0cZj7a9L45smmXxoF6JVbgQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Pc6pR+hLCr4FNbuTi0xCuzjZuNeWKYe560pw+1crU2w=; b=UhQ7WzZ1wVKOWyP0WNmW7Wm4H6CGyUPS7FcTzD5RzTYwym7k+Brkzn0ijvBs3pv/vbzcS18dPfdMsRCcV9EGlzpm/v+HWz4yIEV6EhBmG26pNJFFXCHQQmFEaHIKOQ/qXIEpB0rFrEFnTRXbv6re9hnG4lM4aeX/eF6SslqsWIkY3AZM/km/zs1IQbvbWMGh+zwyRO9yZf43FKHgvY5V2P675H0XyGSJSgQ1z/Fd56noGnYlqVRFCTZyYKsS3w/cWR1TvstSNcoDbT1moss1bWItWWyQ9sQbFrq5VnRmzv1DDZdWEjQ4NTDoNkXsNDgfT7CID+ge//Htmy1dg+XKKg== Received: from DS7PR03CA0162.namprd03.prod.outlook.com (2603:10b6:5:3b2::17) by MN0PR12MB5761.namprd12.prod.outlook.com (2603:10b6:208:374::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9388.13; Tue, 23 Dec 2025 12:15:19 +0000 Received: from CY4PEPF0000EE36.namprd05.prod.outlook.com (2603:10b6:5:3b2:cafe::e) by DS7PR03CA0162.outlook.office365.com (2603:10b6:5:3b2::17) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9456.11 via Frontend Transport; Tue, 23 Dec 2025 12:15:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE36.mail.protection.outlook.com (10.167.242.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9456.9 via Frontend Transport; Tue, 23 Dec 2025 12:15:19 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:15:06 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:15:06 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 23 Dec 2025 04:14:59 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 10/11] cpufreq: CPPC: make scaling_min/max_freq read-only when auto_sel enabled Date: Tue, 23 Dec 2025 17:43:06 +0530 Message-ID: <20251223121307.711773-11-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251223121307.711773-1-sumitg@nvidia.com> References: <20251223121307.711773-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE36:EE_|MN0PR12MB5761:EE_ X-MS-Office365-Filtering-Correlation-Id: cf48e479-fd63-4c72-e46f-08de421cf057 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013|7416014|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?SmxIot0XkDPZlzySF+8Y0YnN+Z+ryukxZe5/dLNWzBmhoOvshT+1l9fRhSW0?= =?us-ascii?Q?lG8JZJkyM20u6Uh0928Jid3VhsKELxGiNnHUC/luZRQbN6Gkq/qtxWLlGc3i?= =?us-ascii?Q?D5h4BU9xSNDQZT0+R7NEkCH0IhQ7mrhUKvEOTPZAidw5nU66+NyUjKGpjs6j?= =?us-ascii?Q?c6BN9Crd5lUt5JD+76xDkoAth3cT2Gynyl9yMrOK8fkhkdLTMuhk4FHdzWVi?= =?us-ascii?Q?Yexc60w2yH+V+XuBPZW5nuyOCmgaBpObUJFMvF25zFqDIs1H1KJgjNNwLqCU?= =?us-ascii?Q?FX0iP+cObJDcAGjLOlwF1H3vVbH+9nl+eMa15q09mqOJ+qChFigeWwS6vD2h?= =?us-ascii?Q?EF/errJM2V0clA5p4yu1DlBBOQOBxMpqbN1ZD2hCUUYn2wAuSzrSZAFsI7bm?= =?us-ascii?Q?hHweihb8gx2KIkGqv/ofGodl83D6/LcYH0uYYEobFjldJVakkwdu7NAxIQUa?= =?us-ascii?Q?zjyUb2ISUi6Uw/I2RRpdXDuI1NPutXRRXGFUDQljiAvD5RULFs2m3/XAVqWy?= =?us-ascii?Q?Zekdox9v23m6Kdbs+bpXw0P27OdCuMx8m3bTECB+ym1KFFh9ylueJSTPtUA5?= =?us-ascii?Q?IoAa1ObHsiMOr0yn+TZ8Z5dcRYJE9zKUPX5cljl8j7yEkVp+InTrdhXSjNRC?= =?us-ascii?Q?CwcifxFueiplH3mamrsigcEfVh1e5dfpgeQfkX4AU3DIYM/KlkHog/kTMnOe?= =?us-ascii?Q?L2mFGB5fSuFOtrw24DHgNfW4+nTbBZ/KilDRhtsGOlUpyMWGRKiG9DW5NBii?= =?us-ascii?Q?j/hOgf8bQklYP0AUM60dG/V0tgzf5dDKxvFYsnlVhr1Oqp7EFWZbvKHRYAG5?= =?us-ascii?Q?eMo0WmKh9K97bWrGsCG40hgvhDRS0ckL43KLMpvsRt7i0rBGtwqaoye0HOP8?= =?us-ascii?Q?PnOC30YZYUQUlXi1cOEcco6vm5+oT5Uxpk/rMOpRI5A5St3lfIIPQcUZ2Rgt?= =?us-ascii?Q?XPVQZxP1Cqrdh+WMOpNCsjsQSuMr42PZx6GxT3s/n1ZzsWoVOa+1oUJkliOk?= =?us-ascii?Q?Z+TyyT2YufW65edJ0El2q/jBB9H9AxE6JvTgB0dEp7NbxHRK8axHVAOrAveN?= =?us-ascii?Q?JPZ/mAtt996TLKqp7K4j5YZKkHLmngdGhd6uTz045SODi9ruMxuABvJKfvW5?= =?us-ascii?Q?2ztUHUdhb7MpANt/pZD6S/XCgHr+2KQittPiwAAT8duiTJgrN7cLlgOMhdER?= =?us-ascii?Q?TObB+KoAmUxR2QeHMDEGxxKUHU8ZPCgnp4aonsNgTv1VnVyqP2YYE3Tu8QVs?= =?us-ascii?Q?1L0//6LzxrVe2Io+EQoZFrtVQRFW6xkvPQedbR9855cI+eYI0p/J8r66Nrk3?= =?us-ascii?Q?LuuOflA+UDHn8sYlNuk1isyK6y8Dvrv1wmwHIL/k8LXnWNJnsXOPd3DREyBp?= =?us-ascii?Q?kKw/ALx2K4kV03pbfWz99CZuDUcg1J6ruPTJNlIYMv0lxNKV7VKfcxq87Xvq?= =?us-ascii?Q?1KXdmrDjzMepb7khixjJVfJ/kPbvcyX4SFTdh7eLSvi2O+OpqQEl7bDj+ijz?= =?us-ascii?Q?f35Vpt6xyJtpVlB/qSLmG1suIwAIY+smJgtYjyxylQrRddEnagoWZN40up5N?= =?us-ascii?Q?vETj30Ctd5NAOxKEQJKXQw1YssCh1xd5TH1i6+jT?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013)(7416014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Dec 2025 12:15:19.0934 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf48e479-fd63-4c72-e46f-08de421cf057 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5761 Content-Type: text/plain; charset="utf-8" When autonomous selection (auto_sel) is enabled, the hardware controls performance within min_perf/max_perf register bounds making the scaling_min/max_freq effectively read-only. Enforce this by setting policy limits to min/max_perf bounds in cppc_verify_policy(). Users must use min_perf/max_perf sysfs interfaces to change performance limits in autonomous mode. Signed-off-by: Sumit Gupta --- drivers/cpufreq/cppc_cpufreq.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index b1f570d6de34..b3da263c18b0 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -305,7 +305,37 @@ static unsigned int cppc_cpufreq_fast_switch(struct cp= ufreq_policy *policy, =20 static int cppc_verify_policy(struct cpufreq_policy_data *policy) { - cpufreq_verify_within_cpu_limits(policy); + unsigned int min_freq =3D policy->cpuinfo.min_freq; + unsigned int max_freq =3D policy->cpuinfo.max_freq; + struct cpufreq_policy *cpu_policy; + struct cppc_cpudata *cpu_data; + struct cppc_perf_caps *caps; + + cpu_policy =3D cpufreq_cpu_get(policy->cpu); + if (!cpu_policy) + return -ENODEV; + + cpu_data =3D cpu_policy->driver_data; + caps =3D &cpu_data->perf_caps; + + if (cpu_data->perf_ctrls.auto_sel) { + u32 min_perf, max_perf; + + /* + * Set policy limits to HW min/max_perf bounds. In autonomous + * mode, scaling_min/max_freq is effectively read-only. + */ + min_perf =3D cpu_data->perf_ctrls.min_perf ?: + caps->lowest_nonlinear_perf; + max_perf =3D cpu_data->perf_ctrls.max_perf ?: caps->nominal_perf; + + policy->min =3D cppc_perf_to_khz(caps, min_perf); + policy->max =3D cppc_perf_to_khz(caps, max_perf); + } else { + cpufreq_verify_within_limits(policy, min_freq, max_freq); + } + + cpufreq_cpu_put(cpu_policy); return 0; } =20 --=20 2.34.1 From nobody Sat Feb 7 17:56:00 2026 Received: from BL0PR03CU003.outbound.protection.outlook.com (mail-eastusazon11012014.outbound.protection.outlook.com [52.101.53.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5045302773; Tue, 23 Dec 2025 12:16:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.53.14 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492215; cv=fail; b=rFe/Vmz2inO1MCfVQ20INcaGDzNrcv+JHpVWcybfs//rjykiqBR5/NNPpl54kTQ4farEY/YmBwq0rBD1vOEEWvkv1LTE91g+2TrVrzVFbhhaMpLNNo/s34a2Tc1Vm3+KlPXS0tdt/Ht8ax36psMCdTust8Xt5bWMz5YrfwKQ8Qc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766492215; c=relaxed/simple; bh=Lg/QBkJm1scDfbw3S/fN2MPWMfybznUBGCviT6jddFw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ijDzaMTiEYv9cGTz2nUA1gNp/pu3cq/mHExzEVPEJN/Gi8XKXQm/JJTUpwuYVOdDiRPm6pKa6gFvd5tG3h0fbltVPWXF8D3yaJP/3eVai6Z5nFY40EGtuyS5FhCoh1soJvXVJpw4fjSd1Sbg9POQ5y+Fq+jqIIuaqJ9ok3QucEo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Ej/++Vha; arc=fail smtp.client-ip=52.101.53.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Ej/++Vha" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=IC1DZM68lSVnoWkClFYjUgdttfQHw5XyIbCILalkUELiihX2XOuoKTGotjGWsdAAw8QjWewzntU5a9crOyZOaUd3EsdIf6J5HsPQBlT02DEnse1f5ZEC7ipLSxlepJHJy+bWyvgLbSVNcct+kSQGdF9885GMdw7PtsHA6b9ZR5zWD/smhh3SXeHX/3uczrjtgn+9i5XqY+8+dX5iJwhi2VGYOYSKqJGThSWXdWcUuesp8GJoxP9LfYwu7q1LTZeg4XZDnRPxXCcHbZO3QKFGu32s5gD9tkuF9mc82zWcVjM3yxcDSAYegOnlj/NFt5Lg5FnegPoNpfeFOxm92KZskw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=h/nMe4z0VlqCnjLYQsMkKM+KdQn7+ClDI32HmHVvV4k=; b=AhoA7UfEq+cHaRTrVorxKKICQ8mA2FyViUpmmNF/8caCX+MPKHZBO+IDcVZZ/Ol0Qb9BPEG0+UgXqBcK0nXcCpyzlSOt64eaZAsnGzNCyBYE9uCxXwonG+mI8ME75ONXBHCqiVzRwaUKkfGPFFVwE5pAat1b8AniQU0+VBju1c9Nukn7Q958u8MZx4AymPyUb9zI/FjYDX8QJ1/0UK2XNbdlpBlWrE4cpyyZem8Zsb2Zulof2zf4oaNE2SnsE0abk6F3tg61BuvVdIhoZlsuy2G66l3jdncRfFTIN/XB/x62PxLv3tfHE1NDZXyixAT8l40lm1ktzCmn80BfrDpKEw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=h/nMe4z0VlqCnjLYQsMkKM+KdQn7+ClDI32HmHVvV4k=; b=Ej/++VhaAzz/rnbYsY5D+qkoxyiTUcqjtPE0an5nn/8r2XA5YBHNFiGZ1wbshzzv4qR+/JqszWxUj3i/XkCBIb8RdZxvhMHn5nfQyRpDYuBVg16LHa1ccDBtg7u0uXjAI6vWfrY2rGabVVvd7OYWfgcML5ztiJX7TDpxwEI7FkQl2Q8cOt2KuC9iV3DOez/RqMxSVicbszOXcA9soheYijfg6XQGO0McxaXeR1Nz5ZE7JnlM8YZz075XbOajFG8jVDcmeqO8fUI9lRe9MX0AQvSrpeXDocOB0sQStQWyzpa3ql3pn9gpkLhI7g30si5fG2F7unlEmOx+aYotECb94w== Received: from MN0PR05CA0011.namprd05.prod.outlook.com (2603:10b6:208:52c::17) by DS5PPFA3734E4BA.namprd12.prod.outlook.com (2603:10b6:f:fc00::65c) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9434.11; Tue, 23 Dec 2025 12:15:34 +0000 Received: from BL6PEPF0001AB73.namprd02.prod.outlook.com (2603:10b6:208:52c:cafe::e8) by MN0PR05CA0011.outlook.office365.com (2603:10b6:208:52c::17) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9456.11 via Frontend Transport; Tue, 23 Dec 2025 12:15:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL6PEPF0001AB73.mail.protection.outlook.com (10.167.242.166) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9456.9 via Frontend Transport; Tue, 23 Dec 2025 12:15:33 +0000 Received: from rnnvmail205.nvidia.com (10.129.68.10) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:15:16 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Dec 2025 04:15:15 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 23 Dec 2025 04:15:08 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 11/11] cpufreq: CPPC: add autonomous mode boot parameter support Date: Tue, 23 Dec 2025 17:43:07 +0530 Message-ID: <20251223121307.711773-12-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251223121307.711773-1-sumitg@nvidia.com> References: <20251223121307.711773-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB73:EE_|DS5PPFA3734E4BA:EE_ X-MS-Office365-Filtering-Correlation-Id: fd0263d8-089a-444d-656a-08de421cf8d3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|1800799024|82310400026|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?IONdS240Wyf9hAqQ8+g/04EZ+98edV9OPeY/aCoMOd7rHv1WaIv+uRjyplN9?= =?us-ascii?Q?o0K+SUvzcUBkFM1ga/9FuJoZkLyvDxRvq0cNnWquCN7Yjr1UVHVbyr9RPBeH?= =?us-ascii?Q?o1JcZbTo9kBSB2Wucswae9K8Nh9bfp0SEi9VbTNrW9dEv7GOGtOJX7gOaMA+?= =?us-ascii?Q?Tu1abeRSTnr85x5tPg4xRJplEacpB48j+Ib7Q/5h9AQa6lptIP08qLV4L8gK?= =?us-ascii?Q?oBWIWHsaYGgYPe1R7xJE4npQ54Mftc2JSwwOy03+Th4P+4meZS+4RZdkvROS?= =?us-ascii?Q?jjiPoGFZnSsH9EOd83t43GYXy8D3ZGpTE14qRjTLuO8ewfCsq+GUalZDQoeu?= =?us-ascii?Q?Y/kg69l6o7w6dKFuIE5T0/2XZDBkzynFhWlM1lGt8jq7jL6zSYt2/s2RVUU5?= =?us-ascii?Q?KBpNWcM3HNczbIfZaj9p1nwOzBZcQLwikGiIHKETZlB1deD1cOcc8CN9SD+X?= =?us-ascii?Q?WxE8H7vQezuplTHYtiLSzDB6T5uP9oSSWXeAJ5CUAWE9B9Nc72WuK6Leq4qT?= =?us-ascii?Q?UXdmfCxwa0m3oO98XI9MEeYV+hzHcujZpTKJKMrGYzI9bGIvljnXOyypxUDB?= =?us-ascii?Q?Ext5dNmn/2cXDZ4AhKUlKFKTxlOpdSi+SPs6ydauymsLF3TLXsq8cEI1xqEd?= =?us-ascii?Q?5ULVaOgVFrSRNNhPD30RXKwkITXUQ5PDRmGq0imnWDKXfxXw2BjTZEdMiD+3?= =?us-ascii?Q?8sLKCRUGNCtHyTUDyqW32fPJjuS186TWgFXQPy0OIKPU4tintUafBV/YWDze?= =?us-ascii?Q?0a4xkfXHFj/oD6CPWm6fb0/seF2l7N0Rwx/5VjjUUEjX5zQ8cox+G1QR4+z3?= =?us-ascii?Q?JPXhkw9fRePez9vjY9lvKag9+xyHdQfwQWo6d5pI6M8AUXrZjS6NLcZhmVqI?= =?us-ascii?Q?leDahEgl3mWpbi62/tbbCkqQ8JSkbjlw5mdi8mDJYfT+E0AdKkvEyS7CqvLe?= =?us-ascii?Q?cuZR959R053YgSzBsMPhctOQVrGS5sufoqxRpVJh6sR8Y/cgvSFAucgFS/bV?= =?us-ascii?Q?vXR//9XtzkBCAPl/9s0DhfmIusk42FopiBCCrsJemiz2LtNa3B25jmVB41B/?= =?us-ascii?Q?X2sL8DkUxLxDjp8OPboMLpZ8cnmYSqxRZSEuj5wvWGIvQ/C3cXs1bc8ooJSq?= =?us-ascii?Q?mKdPET3LtzP1/qYSk3NFGfq3uyhJ8da04485D4mTRSz8PHTadfF8Fz8PvMpW?= =?us-ascii?Q?lX5FL2tZXQUB9G7lQJ5GqWZNgs+myYqHqjSxVGGzc5QYHBN5pOrFv1NCc2Gw?= =?us-ascii?Q?jKSQjztY5oTJrB/itAtCcYVVs2hecrEFfwq8PahmMhP+gWmlMU2EXNgOZ4oc?= =?us-ascii?Q?hhAWGkA21/04KyTg8KPy8qczy8At1nqC908lWD4SLmwyglJRrICYsFjAcsyf?= =?us-ascii?Q?fF/iXmHGn/EwBjLHefd8g/DkziwGkVGiqvc3VmcLVxcqAhOZSZx7FGJ02++F?= =?us-ascii?Q?RKSzaFAB2UfejxfC5DfGVgtpO/FeDi7+Qr8nJEYPMjHQMqOLl71z9Mlt3Xo+?= =?us-ascii?Q?fSRbm6HbDqT02iJkR33ldqIkL1QUhHYey++7YMdDKBsKfZbFNy92S9KRWA3v?= =?us-ascii?Q?ZF+uTqNLxZaeesKY6hF1jXKF33+Bur2y3syR76HP?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700013)(1800799024)(82310400026)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Dec 2025 12:15:33.2402 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fd0263d8-089a-444d-656a-08de421cf8d3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB73.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPFA3734E4BA Content-Type: text/plain; charset="utf-8" Add kernel boot parameter 'cppc_cpufreq.auto_sel_mode' to enable CPPC autonomous performance selection on all CPUs at system startup without requiring runtime sysfs manipulation. When autonomous mode is enabled, the hardware automatically adjusts CPU performance based on workload demands using Energy Performance Preference (EPP) hints. When auto_sel_mode=3D1: - All CPUs are configured for autonomous operation during init - EPP is set to performance preference (0x0) by default - Min/max performance bounds use defaults or already set values - CPU frequency scaling is handled by hardware instead of OS governor The boot parameter is applied only during first policy initialization. User's runtime sysfs configuration is preserved across hotplug. For Documentation/: Reviewed-by: Randy Dunlap Signed-off-by: Sumit Gupta --- .../admin-guide/kernel-parameters.txt | 13 +++ drivers/cpufreq/cppc_cpufreq.c | 85 +++++++++++++++++-- 2 files changed, 90 insertions(+), 8 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index aab72efa1acd..450f0b0225dc 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1035,6 +1035,19 @@ Kernel parameters Format: ,,,[,] =20 + cppc_cpufreq.auto_sel_mode=3D + [CPU_FREQ] Enable ACPI CPPC autonomous performance + selection. When enabled, hardware automatically adjusts + CPU frequency on all CPUs based on workload demands. + In Autonomous mode, Energy Performance Preference (EPP) + hints guide hardware toward performance (0x0) or energy + efficiency (0xff). + Requires ACPI CPPC autonomous selection register support. + Format: + Default: 0 (disabled) + 0: use cpufreq governors + 1: enable if supported by hardware + cpuidle.off=3D1 [CPU_IDLE] disable the cpuidle sub-system =20 diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index b3da263c18b0..8c6869e68504 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -30,6 +30,9 @@ static struct cpufreq_driver cppc_cpufreq_driver; =20 static DEFINE_MUTEX(cppc_cpufreq_update_autosel_config_lock); =20 +/* Autonomous Selection boot parameter */ +static bool auto_sel_mode; + #ifdef CONFIG_ACPI_CPPC_CPUFREQ_FIE static enum { FIE_UNSET =3D -1, @@ -643,11 +646,16 @@ static int cppc_cpufreq_set_mperf_limit(struct cpufre= q_policy *policy, u64 val, * cppc_cpufreq_update_autosel_config - Update autonomous selection config * @policy: cpufreq policy * @is_auto_sel: enable/disable autonomous selection + * @epp_val: EPP value (used only if update_epp true) + * @update_epp: whether to update EPP register + * @update_policy: whether to update policy constraints * * Return: 0 on success, negative error code on failure */ static int cppc_cpufreq_update_autosel_config(struct cpufreq_policy *polic= y, - bool is_auto_sel) + bool is_auto_sel, u32 epp_val, + bool update_epp, + bool update_policy) { struct cppc_cpudata *cpu_data =3D policy->driver_data; struct cppc_perf_caps *caps =3D &cpu_data->perf_caps; @@ -655,7 +663,6 @@ static int cppc_cpufreq_update_autosel_config(struct cp= ufreq_policy *policy, u64 max_perf =3D caps->nominal_perf; unsigned int cpu =3D policy->cpu; bool update_reg =3D is_auto_sel; - bool update_policy =3D true; int ret; =20 guard(mutex)(&cppc_cpufreq_update_autosel_config_lock); @@ -685,6 +692,17 @@ static int cppc_cpufreq_update_autosel_config(struct c= pufreq_policy *policy, if (ret && ret !=3D -EOPNOTSUPP) return ret; =20 + /* Update EPP register */ + if (update_epp) { + ret =3D cppc_set_epp(cpu, epp_val); + if (ret && ret !=3D -EOPNOTSUPP) { + pr_warn("Failed to set EPP for CPU%d (%d)\n", cpu, ret); + return ret; + } + if (!ret) + cpu_data->perf_ctrls.energy_perf =3D epp_val; + } + /* Update auto_sel register */ ret =3D cppc_set_auto_sel(cpu, is_auto_sel); if (ret && ret !=3D -EOPNOTSUPP) { @@ -816,11 +834,54 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_polic= y *policy) policy->cur =3D cppc_perf_to_khz(caps, caps->highest_perf); cpu_data->perf_ctrls.desired_perf =3D caps->highest_perf; =20 - ret =3D cppc_set_perf(cpu, &cpu_data->perf_ctrls); - if (ret) { - pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", - caps->highest_perf, cpu, ret); - goto out; + /* + * Enable autonomous mode on first init if boot param is set. + * Check last_governor to detect first init and skip if auto_sel + * is already enabled. + */ + if (auto_sel_mode && policy->last_governor[0] =3D=3D '\0' && + !cpu_data->perf_ctrls.auto_sel) { + /* Enable CPPC - optional register, some platforms need it */ + ret =3D cppc_set_enable(cpu, true); + if (ret) { + if (ret =3D=3D -EOPNOTSUPP) + pr_debug("CPPC enable not supported CPU%d\n", + cpu); + else + pr_warn("Failed enable CPPC CPU%d (%d)\n", + cpu, ret); + } + + /* + * Enable autonomous mode; Pass false for update_policy to avoid + * updating policy limits prematurely as they are not yet fully setup. + */ + ret =3D cppc_cpufreq_update_autosel_config(policy, + true, /* is_auto_sel */ + CPPC_EPP_PERFORMANCE_PREF, + true, /* update_epp */ + false); /* update_policy */ + if (ret) + pr_warn("Failed autonomous config CPU%d (%d)\n", + cpu, ret); + } + + /* If auto mode is enabled, sync policy limits with HW registers */ + if (cpu_data->perf_ctrls.auto_sel) { + policy->min =3D cppc_perf_to_khz(caps, + cpu_data->perf_ctrls.min_perf ?: + caps->lowest_nonlinear_perf); + policy->max =3D cppc_perf_to_khz(caps, + cpu_data->perf_ctrls.max_perf ?: + caps->nominal_perf); + } else { + /* Standard mode: governors control frequency */ + ret =3D cppc_set_perf(cpu, &cpu_data->perf_ctrls); + if (ret) { + pr_debug("Err setting perf value:%d CPU:%d ret:%d\n", + caps->highest_perf, cpu, ret); + goto out; + } } =20 cppc_cpufreq_cpu_fie_init(policy); @@ -991,7 +1052,7 @@ static ssize_t store_auto_select(struct cpufreq_policy= *policy, if (ret) return ret; =20 - ret =3D cppc_cpufreq_update_autosel_config(policy, val); + ret =3D cppc_cpufreq_update_autosel_config(policy, val, 0, false, true); if (ret) return ret; =20 @@ -1253,10 +1314,18 @@ static int __init cppc_cpufreq_init(void) =20 static void __exit cppc_cpufreq_exit(void) { + unsigned int cpu; + + for_each_present_cpu(cpu) + cppc_set_auto_sel(cpu, false); + cpufreq_unregister_driver(&cppc_cpufreq_driver); cppc_freq_invariance_exit(); } =20 +module_param(auto_sel_mode, bool, 0000); +MODULE_PARM_DESC(auto_sel_mode, "Enable Autonomous Performance Level Selec= tion"); + module_exit(cppc_cpufreq_exit); MODULE_AUTHOR("Ashwin Chaugule"); MODULE_DESCRIPTION("CPUFreq driver based on the ACPI CPPC v5.0+ spec"); --=20 2.34.1