From nobody Mon Feb 9 15:12:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCF662F2605; Tue, 23 Dec 2025 08:05:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766477121; cv=none; b=JSHaZwxL2OAlT3dtZn1C3aGjwbHHqE8wHVdr+dwqGL5xJ2+ZGJPDA0grf+lD182gXnJHcy+EmXgvdfuoWuPKPYUNdCVrrYSBUthZwKRg3ow+ou7fzBMlD54RTPgM/sqVY4oT9EJfp7Aovop74CpFrJ7Pa4RGeRkN9jxGoPCtj3w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766477121; c=relaxed/simple; bh=aNJBU7VGzPbbxm83zUmBI7loH37O7VVFfybp/nU7iiY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=h+5YpSshrs4YjBmKWZJE4FjT3PxMgA858J7W3dm3BLM7r+67b/VY1xXm+9HbiOeVe9VH/bGXMEvIF7i5guVs0YclI/1jB4Qz4spz5MPRH9/mfgYEZXdHJlo6XHt8cAxDaNlUclIxYVzVb4/XfwUawrNnlaRIjXKHJMkU060MRsM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9FF17C113D0; Tue, 23 Dec 2025 08:05:19 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH 1/7] irqchip/loongarch-avec: Adjust irqchip driver for 32BIT/64BIT Date: Tue, 23 Dec 2025 16:04:31 +0800 Message-ID: <20251223080437.3367240-2-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251223080437.3367240-1-chenhuacai@loongson.cn> References: <20251223080437.3367240-1-chenhuacai@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" csr_read64() is only available on 64BIT LoongArch platform, so use recently added adaptive csr_read() instead, so as to make the driver work on both 32BIT and 64BIT platform. BTW, make avecintc_enable() be a no-op since it is only needed by 64BIT platform. Signed-off-by: Jiaxun Yang Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongarch-avec.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-loongarch-avec.c b/drivers/irqchip/irq-loo= ngarch-avec.c index ba556c008cf3..fb8efde95393 100644 --- a/drivers/irqchip/irq-loongarch-avec.c +++ b/drivers/irqchip/irq-loongarch-avec.c @@ -58,11 +58,13 @@ struct avecintc_data { =20 static inline void avecintc_enable(void) { +#ifdef CONFIG_MACH_LOONGSON64 u64 value; =20 value =3D iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC); value |=3D IOCSR_MISC_FUNC_AVEC_EN; iocsr_write64(value, LOONGARCH_IOCSR_MISC_FUNC); +#endif } =20 static inline void avecintc_ack_irq(struct irq_data *d) @@ -167,7 +169,7 @@ void complete_irq_moving(void) struct pending_list *plist =3D this_cpu_ptr(&pending_list); struct avecintc_data *adata, *tdata; int cpu, vector, bias; - uint64_t isr; + unsigned long isr; =20 guard(raw_spinlock)(&loongarch_avec.lock); =20 @@ -177,16 +179,16 @@ void complete_irq_moving(void) bias =3D vector / VECTORS_PER_REG; switch (bias) { case 0: - isr =3D csr_read64(LOONGARCH_CSR_ISR0); + isr =3D csr_read(LOONGARCH_CSR_ISR0); break; case 1: - isr =3D csr_read64(LOONGARCH_CSR_ISR1); + isr =3D csr_read(LOONGARCH_CSR_ISR1); break; case 2: - isr =3D csr_read64(LOONGARCH_CSR_ISR2); + isr =3D csr_read(LOONGARCH_CSR_ISR2); break; case 3: - isr =3D csr_read64(LOONGARCH_CSR_ISR3); + isr =3D csr_read(LOONGARCH_CSR_ISR3); break; } =20 @@ -234,7 +236,7 @@ static void avecintc_irq_dispatch(struct irq_desc *desc) chained_irq_enter(chip, desc); =20 while (true) { - unsigned long vector =3D csr_read64(LOONGARCH_CSR_IRR); + unsigned long vector =3D csr_read(LOONGARCH_CSR_IRR); if (vector & IRR_INVALID_MASK) break; =20 --=20 2.47.3 From nobody Mon Feb 9 15:12:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACA632877D2; Tue, 23 Dec 2025 08:06:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766477163; cv=none; b=LJRfhUEpgPrNIx3WJvhdDAxHVpyvQFflqY2gKrFGx9a5bxknX/vGKxh2kk9LVAEkIwjAFCHEguXvQwsLN7vWOlfK7oU5MqOsZBlk9plHhbRSmlS3HWNAfG6Jq+fAka1I2CKdgJycBLTRcegiTpPtbmBZvn0xm43YcQ7/ENwN/Xo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766477163; c=relaxed/simple; bh=v0wMB9OKBwgl0i0tO5YIIXLePVV5l8Dck3oqzf/anQY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qL6NjWiDis4dZbZHDsiEHIeiPQtf+V+D8SFXctIToaa+blEX8sLnwRS1KxxY5+rqPZGDkNQlxQWUUor2XR90KxSNh9eMOsTIqaK6pAlo+Sc8QT661VjAtnOLGhygyPuGtJo0rGB+gzUyLZFkCq+LfOpOP8jtU8dHD8sKBlHO5MU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 79D4EC113D0; Tue, 23 Dec 2025 08:06:01 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH 2/7] irqchip/loongson-liointc: Adjust irqchip driver for 32BIT/64BIT Date: Tue, 23 Dec 2025 16:04:32 +0800 Message-ID: <20251223080437.3367240-3-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251223080437.3367240-1-chenhuacai@loongson.cn> References: <20251223080437.3367240-1-chenhuacai@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" irq_domain_alloc_fwnode() takes a parameter with the phys_addr_t type. Currently we pass acpi_liointc->address to it. This can only work on 64BIT platform because its type is u64, so cast it to phys_addr_t and then the driver works on both 32BIT and 64BIT platform. Signed-off-by: Jiaxun Yang Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-liointc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-l= oongson-liointc.c index 0033c2188abc..f001a34878ba 100644 --- a/drivers/irqchip/irq-loongson-liointc.c +++ b/drivers/irqchip/irq-loongson-liointc.c @@ -394,8 +394,9 @@ static int __init acpi_cascade_irqdomain_init(void) =20 int __init liointc_acpi_init(struct irq_domain *parent, struct acpi_madt_l= io_pic *acpi_liointc) { - int ret; + phys_addr_t addr =3D acpi_liointc->address; struct fwnode_handle *domain_handle; + int ret; =20 parent_int_map[0] =3D acpi_liointc->cascade_map[0]; parent_int_map[1] =3D acpi_liointc->cascade_map[1]; @@ -403,7 +404,7 @@ int __init liointc_acpi_init(struct irq_domain *parent,= struct acpi_madt_lio_pic parent_irq[0] =3D irq_create_mapping(parent, acpi_liointc->cascade[0]); parent_irq[1] =3D irq_create_mapping(parent, acpi_liointc->cascade[1]); =20 - domain_handle =3D irq_domain_alloc_fwnode(&acpi_liointc->address); + domain_handle =3D irq_domain_alloc_fwnode(&addr); if (!domain_handle) { pr_err("Unable to allocate domain handle\n"); return -ENOMEM; --=20 2.47.3 From nobody Mon Feb 9 15:12:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B7202877D2; Tue, 23 Dec 2025 08:06:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766477203; cv=none; b=rWEwkJgr7wrJj3u/5AgUvZN+vBXR+6RGdPDT6sNzxg/If4QAdmo3s3Al9bsqwY/LmUGSTqNZRs05zvBdxEMhAq2XIifaUGwaN2y4uQrtfkmHxFJXhLBhtimfrRs+9ZXsy8f/e2ibRUi5mX0mrKvM57+sGnyWQvEtDkSlsW7IO7g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766477203; c=relaxed/simple; bh=7r8cMcFUbks3jEu1KT5WilPmKDYxhwDdwyft8WEDieU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QBwMGIjE0ohX+alF35OyhncL4BE+axwbK/ZuDIcuQSorh2Qn+366jZ9b2EHTnh4nCx4yrFheHtEZK12c5goOB9gKfw+gsB0coHk5NlFKQgzBYLuejPC9YFfb7o1RenCiWOHWj3xj3z3zhESY25mMsqg36pPBU2fxGdleE280i18= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 562BCC113D0; Tue, 23 Dec 2025 08:06:41 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH 3/7] irqchip/loongson-eiointc: Adjust irqchip driver for 32BIT/64BIT Date: Tue, 23 Dec 2025 16:04:33 +0800 Message-ID: <20251223080437.3367240-4-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251223080437.3367240-1-chenhuacai@loongson.cn> References: <20251223080437.3367240-1-chenhuacai@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" iocsr_read64()/iocsr_write64() are only available on 64BIT LoongArch platform, so add and use a pair of helpers, i.e. read_isr()/write_isr() instead, so as to make the driver work on both 32BIT and 64BIT platform. BTW, make eiointc_enable() be a no-op since it is only needed by 64BIT platform. Signed-off-by: Jiaxun Yang Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-eiointc.c | 36 +++++++++++++++++++++----- 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-l= oongson-eiointc.c index ad2105685b48..e2eb4cd27f78 100644 --- a/drivers/irqchip/irq-loongson-eiointc.c +++ b/drivers/irqchip/irq-loongson-eiointc.c @@ -37,9 +37,9 @@ #define EXTIOI_ENABLE_INT_ENCODE BIT(2) #define EXTIOI_ENABLE_CPU_ENCODE BIT(3) =20 -#define VEC_REG_COUNT 4 -#define VEC_COUNT_PER_REG 64 -#define VEC_COUNT (VEC_REG_COUNT * VEC_COUNT_PER_REG) +#define VEC_COUNT 256 +#define VEC_COUNT_PER_REG BITS_PER_LONG +#define VEC_REG_COUNT (VEC_COUNT / BITS_PER_LONG) #define VEC_REG_IDX(irq_id) ((irq_id) / VEC_COUNT_PER_REG) #define VEC_REG_BIT(irq_id) ((irq_id) % VEC_COUNT_PER_REG) #define EIOINTC_ALL_ENABLE 0xffffffff @@ -85,11 +85,13 @@ static struct eiointc_priv *eiointc_priv[MAX_IO_PICS]; =20 static void eiointc_enable(void) { +#ifdef CONFIG_MACH_LOONGSON64 uint64_t misc; =20 misc =3D iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC); misc |=3D IOCSR_MISC_FUNC_EXT_IOI_EN; iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC); +#endif } =20 static int cpu_to_eio_node(int cpu) @@ -281,12 +283,34 @@ static int eiointc_router_init(unsigned int cpu) return 0; } =20 +#if VEC_COUNT_PER_REG =3D=3D 32 +static unsigned long read_isr(int i) +{ + return iocsr_read32(EIOINTC_REG_ISR + (i << 2)); +} + +static void write_isr(int i, unsigned long val) +{ + iocsr_write32(val, EIOINTC_REG_ISR + (i << 2)); +} +#else +static unsigned long read_isr(int i) +{ + return iocsr_read64(EIOINTC_REG_ISR + (i << 3)); +} + +static void write_isr(int i, unsigned long val) +{ + iocsr_write64(val, EIOINTC_REG_ISR + (i << 3)); +} +#endif + static void eiointc_irq_dispatch(struct irq_desc *desc) { struct eiointc_ip_route *info =3D irq_desc_get_handler_data(desc); struct irq_chip *chip =3D irq_desc_get_chip(desc); bool handled =3D false; - u64 pending; + unsigned long pending; int i; =20 chained_irq_enter(chip, desc); @@ -299,14 +323,14 @@ static void eiointc_irq_dispatch(struct irq_desc *des= c) * read ISR for these 64 interrupt vectors rather than all vectors */ for (i =3D info->start; i < info->end; i++) { - pending =3D iocsr_read64(EIOINTC_REG_ISR + (i << 3)); + pending =3D read_isr(i); =20 /* Skip handling if pending bitmap is zero */ if (!pending) continue; =20 /* Clear the IRQs */ - iocsr_write64(pending, EIOINTC_REG_ISR + (i << 3)); + write_isr(i, pending); while (pending) { int bit =3D __ffs(pending); int irq =3D bit + VEC_COUNT_PER_REG * i; --=20 2.47.3 From nobody Mon Feb 9 15:12:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2EDF306B06; Tue, 23 Dec 2025 08:07:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766477246; cv=none; b=f49tagKlBSjz24dGrFzyb0fSfdE/3F+pQPBtX3NoHwXlW50nyfxNSYktsr9XBbSKa0gl0l8KMuLn0BBVcQ5AZK3+BdeKA3dmIiT9y73b3lmCbZqxAKWMXmR6D9X/FQDuJJ8AgmD3EtGGKj7jl/j0TrBlMZf0lP4eLJ5f4uLGs0A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766477246; c=relaxed/simple; bh=+IVGLA5ogZ7PuqmNmMeAw93CXJPoFkzTeYSzwyuQ5Ls=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fSs4NFCNmAZuaoDnCKtOsrV9810jiMU3v+urhaD5q6XnkUkH9nT5E9g0j0fvFCn71UoawPLhDV7rbP3hNzm/X/BKvIjnBosiAs3+U6fdFamb57FvyySEQBmRScSoyTucKiAOKtVqpcBgzBOtW3rn+UASwOUEOjR6ENIijqp8uzQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id CBAE7C113D0; Tue, 23 Dec 2025 08:07:23 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH 4/7] irqchip/loongson-htvec: Adjust irqchip driver for 32BIT/64BIT Date: Tue, 23 Dec 2025 16:04:34 +0800 Message-ID: <20251223080437.3367240-5-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251223080437.3367240-1-chenhuacai@loongson.cn> References: <20251223080437.3367240-1-chenhuacai@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" irq_domain_alloc_fwnode() takes a parameter with the phys_addr_t type. Currently we pass acpi_htvec->address to it. This can only work on 64BIT platform because its type is u64, so cast it to phys_addr_t and then the driver works on both 32BIT and 64BIT platform. Signed-off-by: Jiaxun Yang Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-htvec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-loongson-htvec.c b/drivers/irqchip/irq-loo= ngson-htvec.c index d2be8e954e92..03c3992b39c8 100644 --- a/drivers/irqchip/irq-loongson-htvec.c +++ b/drivers/irqchip/irq-loongson-htvec.c @@ -298,8 +298,8 @@ static int __init acpi_cascade_irqdomain_init(void) int __init htvec_acpi_init(struct irq_domain *parent, struct acpi_madt_ht_pic *acpi_htvec) { - int i, ret; - int num_parents, parent_irq[8]; + int i, ret, num_parents, parent_irq[8]; + phys_addr_t addr =3D acpi_htvec->address; struct fwnode_handle *domain_handle; =20 if (!acpi_htvec) @@ -307,7 +307,7 @@ int __init htvec_acpi_init(struct irq_domain *parent, =20 num_parents =3D HTVEC_MAX_PARENT_IRQ; =20 - domain_handle =3D irq_domain_alloc_fwnode(&acpi_htvec->address); + domain_handle =3D irq_domain_alloc_fwnode(&addr); if (!domain_handle) { pr_err("Unable to allocate domain handle\n"); return -ENOMEM; --=20 2.47.3 From nobody Mon Feb 9 15:12:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BCEF230EF9A; Tue, 23 Dec 2025 08:08:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766477291; cv=none; b=WtrUrlhGTlmYOdrvh4q5JdvzalGEC2N5evNCjkP6nNSKI63I1ivEkKnFxSFms+ng1ffgNbAjY2QCoQMA9tvkHbLnHETE6XpR6cBp4WSIolCoM+qjIsrrz/EB59504Y//pfLLa2nqv9e6zhcswZirXFBL1VN9Sgma9f+s9/qWPNM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766477291; c=relaxed/simple; bh=F30Xn/tK26X8XyipYPeBBASRkv7sdoRmPDULBO9UX4s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mmgXQrLg9DMzQSqw6tZwvyLckFovVxMj7vko6HfUyVDlXIpA+Rq867QXIhRjvJWbsRMdGl/cx1djliZNKSDJVQvCEfVbsq/V0959hKnUfgx63sofwj7PDR6OqHuAW6f3GHBEH6pTqI3n+1X2kOKyKvsJ1PfYvOcon5wdw9Rtu6A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7EA61C113D0; Tue, 23 Dec 2025 08:08:08 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH 5/7] irqchip/loongson-pch-msi: Adjust irqchip driver for 32BIT/64BIT Date: Tue, 23 Dec 2025 16:04:35 +0800 Message-ID: <20251223080437.3367240-6-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251223080437.3367240-1-chenhuacai@loongson.cn> References: <20251223080437.3367240-1-chenhuacai@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" irq_domain_alloc_fwnode() takes a parameter with the phys_addr_t type. Currently we pass acpi_pchmsi->msg_address to it. This can only work on 64BIT platform because its type is u64, so cast it to phys_addr_t and then the driver works on both 32BIT and 64BIT platform. Signed-off-by: Jiaxun Yang Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-pch-msi.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-loongson-pch-msi.c b/drivers/irqchip/irq-l= oongson-pch-msi.c index 4aedc9b90ff7..8500662bdb33 100644 --- a/drivers/irqchip/irq-loongson-pch-msi.c +++ b/drivers/irqchip/irq-loongson-pch-msi.c @@ -263,11 +263,12 @@ struct fwnode_handle *get_pch_msi_handle(int pci_segm= ent) =20 int __init pch_msi_acpi_init(struct irq_domain *parent, struct acpi_madt_m= si_pic *acpi_pchmsi) { - int ret; + phys_addr_t msg_address =3D acpi_pchmsi->msg_address; struct fwnode_handle *domain_handle; + int ret; =20 - domain_handle =3D irq_domain_alloc_fwnode(&acpi_pchmsi->msg_address); - ret =3D pch_msi_init(acpi_pchmsi->msg_address, acpi_pchmsi->start, + domain_handle =3D irq_domain_alloc_fwnode(&msg_address); + ret =3D pch_msi_init(msg_address, acpi_pchmsi->start, acpi_pchmsi->count, parent, domain_handle); if (ret < 0) irq_domain_free_fwnode(domain_handle); --=20 2.47.3 From nobody Mon Feb 9 15:12:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC9CC30F946; Tue, 23 Dec 2025 08:08:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766477309; cv=none; b=OPKB57IMlO27SN+9aD65EI58S5/gf/h8w/L3A/R4r/vvfbaw0aSNjaWwV7jNWgCujzmhRSJNOrSndqYuWyPwmpBChBa6l0KUfC9t8TOfjzQo3lgBRksdycNyRcQjQa7pcPdx1LURyRJoGqyp1beoBlgr0W8cIoYZQzRnQ9Q23lU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766477309; c=relaxed/simple; bh=woAYGapLGYPovW9k/RNngZoOcBtkCctJJQc7gVpP1Jc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SR5aoSwKGrY49FWZ5iFbqSZMZ9JERiAinJ6x9N1BdeOZMitM8IxXIescOJ4bBP3CGmVKm6JlRUK7jyuLmX/F4kb5rM3zRUCSlP+SyyLN9FZZjqTseK0kSOUV1jgFlYDwsqBIGJbh3WfBMraQ4hyccYqyUQ73+7DVE/YdJq1P9WA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 89345C113D0; Tue, 23 Dec 2025 08:08:27 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH 6/7] irqchip/loongson-pch-pic: Adjust irqchip driver for 32BIT/64BIT Date: Tue, 23 Dec 2025 16:04:36 +0800 Message-ID: <20251223080437.3367240-7-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251223080437.3367240-1-chenhuacai@loongson.cn> References: <20251223080437.3367240-1-chenhuacai@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" irq_domain_alloc_fwnode() takes a parameter with the phys_addr_t type. Currently we pass acpi_pchpic->address to it. This can only work on 64BIT platform because its type is u64, so cast it to phys_addr_t and then the driver works on both 32BIT and 64BIT platform. BTW, use readl() to get vec_count because readq() is only available on 64BIT platform. Signed-off-by: Jiaxun Yang Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-pch-pic.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-l= oongson-pch-pic.c index c6b369a974a7..2ac7e3245b72 100644 --- a/drivers/irqchip/irq-loongson-pch-pic.c +++ b/drivers/irqchip/irq-loongson-pch-pic.c @@ -343,7 +343,7 @@ static int pch_pic_init(phys_addr_t addr, unsigned long= size, int vec_base, priv->table[i] =3D PIC_UNDEF_VECTOR; =20 priv->ht_vec_base =3D vec_base; - priv->vec_count =3D ((readq(priv->base) >> 48) & 0xff) + 1; + priv->vec_count =3D ((readl(priv->base + 4) >> 16) & 0xff) + 1; priv->gsi_base =3D gsi_base; =20 priv->pic_domain =3D irq_domain_create_hierarchy(parent_domain, 0, @@ -449,13 +449,14 @@ static int __init acpi_cascade_irqdomain_init(void) int __init pch_pic_acpi_init(struct irq_domain *parent, struct acpi_madt_bio_pic *acpi_pchpic) { - int ret; + phys_addr_t addr =3D acpi_pchpic->address; struct fwnode_handle *domain_handle; + int ret; =20 if (find_pch_pic(acpi_pchpic->gsi_base) >=3D 0) return 0; =20 - domain_handle =3D irq_domain_alloc_fwnode(&acpi_pchpic->address); + domain_handle =3D irq_domain_alloc_fwnode(&addr); if (!domain_handle) { pr_err("Unable to allocate domain handle\n"); return -ENOMEM; --=20 2.47.3 From nobody Mon Feb 9 15:12:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E0D830FF23; Tue, 23 Dec 2025 08:08:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766477331; cv=none; b=N3qhyd3OWmQEFZj1kTUJv6B01A2x71fnLDR8jBc6W2/fnMi9iRC1Xop7ss2isemJEql3LP8xPK+jO8VETZHN1mF5sMuQz13idAeTcQqv6oV6uW8zi3Ngp7BkF1VXpN+3fCfkhMtmweNQ2kqOHKR9VC0mhm4MfZNcmMSxZ/K6K8g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766477331; c=relaxed/simple; bh=Rl2FAny2OVwcdTD9DmNUnGF8zPnafuH238LDsxkuWKE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=q7U5mUb42+bq7YF/n4xZ7PtJHfPHfhhmL9yu6euyLn+Wb6M40NCg3Oz7+TMZCv3RdUuqoQmGvqkopCK+1pp00Gzet346R6ZQpK2yvz6aZ7KVKqUzcChJI4GwOuOrFehMLs+0b12OUzzwEan9R3rwO/5PH/UFEEEBTcrFDccocMI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id EA517C113D0; Tue, 23 Dec 2025 08:08:48 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH 7/7] irqchip: Allow LoongArch irqchip drivers on both 32BIT/64BIT Date: Tue, 23 Dec 2025 16:04:37 +0800 Message-ID: <20251223080437.3367240-8-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251223080437.3367240-1-chenhuacai@loongson.cn> References: <20251223080437.3367240-1-chenhuacai@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All LoongArch irqchip drivers are adjusted, allow them be built on both 32BIT and 64BIT platforms. Signed-off-by: Jiaxun Yang Signed-off-by: Huacai Chen --- drivers/irqchip/Kconfig | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index f334f49c9791..270f1c4783e3 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -698,7 +698,7 @@ config IRQ_LOONGARCH_CPU =20 config LOONGSON_LIOINTC bool "Loongson Local I/O Interrupt Controller" - depends on MACH_LOONGSON64 + depends on MACH_LOONGSON64 || LOONGARCH default y select IRQ_DOMAIN select GENERIC_IRQ_CHIP @@ -708,7 +708,6 @@ config LOONGSON_LIOINTC config LOONGSON_EIOINTC bool "Loongson Extend I/O Interrupt Controller" depends on LOONGARCH - depends on MACH_LOONGSON64 default MACH_LOONGSON64 select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_CHIP @@ -726,7 +725,7 @@ config LOONGSON_HTPIC =20 config LOONGSON_HTVEC bool "Loongson HyperTransport Interrupt Vector Controller" - depends on MACH_LOONGSON64 + depends on MACH_LOONGSON64 || LOONGARCH default MACH_LOONGSON64 select IRQ_DOMAIN_HIERARCHY help @@ -734,7 +733,7 @@ config LOONGSON_HTVEC =20 config LOONGSON_PCH_PIC bool "Loongson PCH PIC Controller" - depends on MACH_LOONGSON64 + depends on MACH_LOONGSON64 || LOONGARCH default MACH_LOONGSON64 select IRQ_DOMAIN_HIERARCHY select IRQ_FASTEOI_HIERARCHY_HANDLERS @@ -743,7 +742,7 @@ config LOONGSON_PCH_PIC =20 config LOONGSON_PCH_MSI bool "Loongson PCH MSI Controller" - depends on MACH_LOONGSON64 + depends on MACH_LOONGSON64 || LOONGARCH depends on PCI default MACH_LOONGSON64 select IRQ_DOMAIN_HIERARCHY @@ -755,7 +754,7 @@ config LOONGSON_PCH_MSI config LOONGSON_PCH_LPC bool "Loongson PCH LPC Controller" depends on LOONGARCH - depends on MACH_LOONGSON64 + depends on MACH_LOONGSON64 || LOONGARCH default MACH_LOONGSON64 select IRQ_DOMAIN_HIERARCHY help --=20 2.47.3