From nobody Tue Feb 10 05:45:00 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AADBC234973; Tue, 23 Dec 2025 05:37:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766468232; cv=none; b=pZgucRVaygXz6xWbuZahGoiEs8hZKbE109Y93nCm7iHaWbTVvXEymU2Ge5cmzI7hOENqNl0BSWlHKqN9WfKiIXm8kdNLdwVCdhYs9A47jvNbm4gk4NBp58SehW6J5xIweS8Qg/bYtBKvXVP/lthEkzwJ5W85L05O0eNa6t1yKvc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766468232; c=relaxed/simple; bh=ZYX1p8WPn44SSB2oRNOoupCJ6NnI83K5zFkFYwydXMo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=teH21MtB/oeod8dCKRAx/SdLk7nk8pODDD+EKUsUtxREMvOoL1p39w8j2buo5qoevMenBcJGGeCU9rXiz/+/jFfVr2xh3Hm6o1Z/3RPt/EI/hQHc4/6ZrQmHjPHG7L9NBITrDS/2tq887VPHEv03t6QfdXnljJeLLdz6Vx6vqaM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MUVZsIwr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MUVZsIwr" Received: by smtp.kernel.org (Postfix) with ESMTPS id 59940C116B1; Tue, 23 Dec 2025 05:37:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1766468232; bh=ZYX1p8WPn44SSB2oRNOoupCJ6NnI83K5zFkFYwydXMo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=MUVZsIwrb+yoHW1U7sylUJWNXB97oVCXCXcKW6/17EsdObXXIsZnijeqDzliiTmjR QuxpYYxyRK5xSFhdWq8rpPT31vabek3i2pwha2Y9HsGuSypOmtvvdIsmUcqmM+gjir fN62QpoEbLYOmX/hs8QHzO/TaRBrkK9WVgW9Z87Qrt2BkbQjPBWURyHW0rxePGNyAH +FYOz4SZ5syiCSNvSuu4Jf4YQVm98CHlFYIvYiWn/eTWO7G4nOqEZz6fZihkBj+H3w t1c4Trd+IMBDIzlf6eLUZBoNliE2EcqUloxjHUvXb7eW7XOF7smujtH+bcc4bWanhb zSUXq9iR+rKRQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A8FBE6B277; Tue, 23 Dec 2025 05:37:12 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Tue, 23 Dec 2025 05:37:10 +0000 Subject: [PATCH v2 2/4] arm64: dts: amlogic: Add S6 Reset Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-reset-s6-s7-s7d-v2-2-958f341449f1@amlogic.com> References: <20251223-reset-s6-s7-s7d-v2-0-958f341449f1@amlogic.com> In-Reply-To: <20251223-reset-s6-s7-s7d-v2-0-958f341449f1@amlogic.com> To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766468230; l=6199; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=S9bh6mcr56L5dWsdOMdXWvsC+NuQJMrllSpdxW2lS1k=; b=g73dEWgoyJy4vPxcpQ7DbWpu7OnmEzm+LvCpSLkwCD8OrUdkkEZGvj0yy86S/0F2Bcl4zmBEc +fzLWeMxqZFCm9ruI00qXU5JjOlhnLoz2iu4DA8gFYW1nFrlGyJndsA X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add the device node and related header file for Amlogic S6 reset controller. Signed-off-by: Xianwei Zhao Reviewed-by: Martin Blumenstingl --- arch/arm64/boot/dts/amlogic/amlogic-s6-reset.h | 171 +++++++++++++++++++++= ++++ arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi | 8 ++ 2 files changed, 179 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s6-reset.h b/arch/arm64/bo= ot/dts/amlogic/amlogic-s6-reset.h new file mode 100644 index 000000000000..90bf5a182046 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-s6-reset.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2025 Amlogic, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_AMLOGIC_S6_RESET_H +#define _DT_BINDINGS_AMLOGIC_S6_RESET_H + +/* RESET0 */ +/* 0-1 */ +#define RESET_U3DRD_USB3PHY_APB 2 +#define RESET_U3DRD_USB3PHY 3 +#define RESET_U3DRD_USB2PHY 4 +#define RESET_U3DRD 5 +#define RESET_U3DRD_COMB 6 +#define RESET_U2DRD 7 +#define RESET_U2DRD_COMB 8 +#define RESET_U2DRD_USB2PHY 9 +#define RESET_USB_CC 10 +#define RESET_BC 11 +#define RESET_VC9000E_APB 12 +#define RESET_VC9000E 13 +#define RESET_VC9000E_CORE 14 +#define RESET_HDMI20_AES 15 +#define RESET_HDMITX_CAPB3 16 +#define RESET_BRQ_VCBUS_DEC 17 +#define RESET_VCBUS 18 +#define RESET_VID_PLL_DIV 19 +#define RESET_VDI6 20 +/* 21 */ +#define RESET_HDMITXPHY 22 +#define RESET_VID_LOCK 23 +#define RESET_VENCL 24 +#define RESET_VDAC 25 +#define RESET_VENCP 26 +#define RESET_VENCI 27 +#define RESET_RDMA 28 +#define RESET_HDMITX 29 +#define RESET_VIU 30 +#define RESET_VENC 31 + +/* RESET1 */ +#define RESET_AUDIO 32 +#define RESET_MALI_CAPB3 33 +#define RESET_MALI 34 +#define RESET_DDR_APB 35 +#define RESET_DDR 36 +#define RESET_DOS_CAPB3 37 +#define RESET_DOS 38 +#define RESET_MALI_SYS 39 +#define RESET_I_DSPA 40 +#define RESET_I_DEBUGA 41 +#define RESET_U3P2_PHY_APB 42 +#define RESET_PCIE_PIPE 43 +#define RESET_PCIE_A 44 +#define RESET_PCIE_PHY 45 +#define RESET_PCIE_APB 46 +#define RESET_AMFC_APB 47 +#define RESET_ETHERNET 48 +/* 49-50 */ +#define RESET_BRG_ETH_APB_SYNC 51 +#define RESET_VICP 52 +#define RESET_DEWARP 53 +#define RESET_GE2D 54 +#define RESET_VGE 55 +#define RESET_PCIE0 56 +#define RESET_PCIE1 57 +#define RESET_PCIE2 58 +#define RESET_PCIE3 59 +#define RESET_PCIE4 60 +#define RESET_PCIE5 61 +#define RESET_PCIE6 62 +#define RESET_PCIE7 63 + +/* RESET2 */ +#define RESET_AM2AXI 64 +#define RESET_IR_CTRL 65 +#define RESET_MIPI_DSI_PHY 66 +#define RESET_TS_PLL 67 +#define RESET_MIPI_CSI2_PHY0 68 +#define RESET_ETH_AXI 69 +/* 70-71 */ +#define RESET_SMART_CARD 72 +#define RESET_SPICC_0 73 +#define RESET_BRG_VGE_PIPE1 74 +#define RESET_BRG_VC9000E_PIPE1 75 +#define RESET_BRG_AMFC_PIPE1 76 +/* 77 */ +#define RESET_NNA_APB 78 +#define RESET_NNA 79 +#define RESET_MSR_CLK 80 +/* 81 */ +#define RESET_SAR_DIG 82 +#define RESET_SAR_ANA 83 +/* 84-85 */ +#define RESET_AMFC 86 +/* 87-88 */ +#define RESET_CEC 89 +/* 90 */ +#define RESET_WATCHDOG 91 +/* 92 */ +#define RESET_MIP_DSI_HOST 93 +/* 94-95 */ + +/* RESET3 */ +/* 96 ~ 127 */ + +/* RESET4 */ +#define RESET_PWM_A 128 +#define RESET_PWM_B 129 +#define RESET_PWM_C 130 +#define RESET_PWM_D 131 +#define RESET_PWM_E 132 +#define RESET_PWM_F 133 +#define RESET_PWM_G 134 +#define RESET_PWM_H 135 +#define RESET_PWM_I 136 +#define RESET_PWM_J 137 +#define RESET_UART_A 138 +#define RESET_UART_B 139 +#define RESET_UART_C 140 +#define RESET_UART_D 141 +#define RESET_UART_E 142 +/* 143 */ +#define RESET_I2C_S_A 144 +#define RESET_I2C_M_A 145 +#define RESET_I2C_M_B 146 +#define RESET_I2C_M_C 147 +#define RESET_I2C_M_D 148 +#define RESET_I2C_M_E 149 +/* 150-151 */ +#define RESET_SDEMMC_A 152 +#define RESET_SDEMMC_B 153 +#define RESET_SDEMMC_C 154 +/* 155-159 */ + +/* RESET5 */ +#define RESET_BRG_VDEC_PIPE 160 +#define RESET_BRG_SDIOA_PIPE 161 +#define RESET_BRG_SDIOB_PIPE 162 +#define RESET_BRG_EMMC_PIPE 163 +#define RESET_BRG_GE2D_DMC_PIPE 164 +#define RESET_BRG_DMC_VPU_PIPE1 165 +#define RESET_BRG_A53_DMC_PIPE1 166 +#define RESET_BRG_MALI_DMC_PIPE 167 +/* 168 */ +#define RESET_BRG_MALI_DMC_PIPE1 169 +#define RESET_BRG_U2DRD_PIPE 170 +#define RESET_BRG_U2H_PIPE 171 +#define RESET_BRG_HEVCF_PIPE1 172 +#define RESET_BRG_AMBUS_ETH_PIPE1 173 +#define RESET_BRG_SRAM_NIC_NNA 174 +#define RESET_BRG_SRAM_NIC_MAIN 175 +#define RESET_BRG_SRAM_NIC_DEV 176 +#define RESET_BRG_SRAM_NIC_CPU 177 +#define RESET_BRG_SRAM_NIC_ALL 178 +#define RESET_BRG_CPU_NIC_RAMA 179 +#define RESET_BRG_CPU_NIC_VAPB 180 +#define RESET_BRG_CPU_NIC_DSU 181 +#define RESET_BRG_CPU_NIC_CLK81 182 +#define RESET_BRG_CPU_NIC_ALL 183 +#define RESET_BRG_NIC_CAPU 184 +#define RESET_BRG_AO_NIC_EMMC 185 +#define RESET_BRG_AO_NIC_DSPA 186 +#define RESET_BRG_AO_NIC_SDIOB 187 +#define RESET_BRG_AO_NIC_SDIOA 188 +#define RESET_BRG_AO_NIC_CLK81 189 +#define RESET_BRG_AO_NIC_MAIN 190 +#define RESET_BRG_AO_NIC_ALL 191 + +#endif diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-s6.dtsi index 8ef631939033..386244b3a1f5 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include "amlogic-s6-reset.h" / { cpus { #address-cells =3D <2>; @@ -104,6 +105,13 @@ uart_b: serial@7a000 { status =3D "disabled"; }; =20 + reset: reset-controller@2000 { + compatible =3D "amlogic,s6-reset", + "amlogic,meson-s4-reset"; + reg =3D <0x0 0x2000 0x0 0x98>; + #reset-cells =3D <1>; + }; + periphs_pinctrl: pinctrl@4000 { compatible =3D "amlogic,pinctrl-s6"; #address-cells =3D <2>; --=20 2.52.0