From nobody Mon Feb 9 08:12:13 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D5881D5146 for ; Tue, 23 Dec 2025 18:02:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766512946; cv=pass; b=meW92caVpbwOONCs0q62lZtMvx9UmARYOTgV6QjE1IKopJTeoY6oDrxCBjnhi15N+Kc1HBWLbVooa9XuosJHM2FwAJwYEjhiu/iaHqFsn19U6xbquAo2oY5eoudQr8hlCxYmUxpuU3TO4UkbbhF6TmiQx9FcuNsF+gHodUaJZXc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766512946; c=relaxed/simple; bh=ugru4usORzyGVharrOpFIzDKbsCLQyvdHJjP2SWO498=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MTjt0CHpaayShY7e99+78SKrqm1pXWnlQIu7C249i/Am/Gl/aLJL1cHY5fcKJ8ER5v8k4sPRCHfp27A9C5NgEzZ98WQHVJ4iVVf2cld55hKPg2EavEw3QhjE4DixTov+usQR57wsaFnB1oQLR2D/7ZbtQh5xnQHt2RHMOxVpwi4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=ariel.dalessandro@collabora.com header.b=Jt8BW7WW; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=ariel.dalessandro@collabora.com header.b="Jt8BW7WW" ARC-Seal: i=1; a=rsa-sha256; t=1766512916; cv=none; d=zohomail.com; s=zohoarc; b=g09L0ntADSy9B9c38knwz/8xGekpXqg4IE8DBpO/VBibeXdP8O9BHh8p7nxpThcJR2RFdAvNju7ncsyfFEtZl2uvYDxSqLLJpNLyQLoC6e+2l3tbItWpbPdCWgjj/WD4tjnEt/OS9mlgkAyywhH76XcQLSSt8vADYP38prxxzk8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766512916; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=Z7eVde9x2/ylK4NN0CCw447RxI38NXyJelzIucjvKxk=; b=KtbdPTvH2BZDqpZAQR6jwF38KjVVBtJZ6aeFrUUIrOtW/y8hoZ7Sk4WaFZwoPF+9OyOuoQzjCRCYh5KA5kSasE2AZuQrZCbg5YxhrZFyW9Kf7KKGxpYuZ8KVFHo7lMPCwdy7IHw0KmUKri3BgIWU3q4FK04nfHbbf1EpZAtAqhU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=ariel.dalessandro@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1766512916; s=zohomail; d=collabora.com; i=ariel.dalessandro@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=Z7eVde9x2/ylK4NN0CCw447RxI38NXyJelzIucjvKxk=; b=Jt8BW7WWR6h5Ey90PjbC74eeZl8eJly5g09P3nholp7s7QsA52HwFYgcIvQrknK6 xiL59CIFyrZBisFcbHPaT0NrLRTNMM/2Hr3cdwdu3FiNxtcJXHs+4hodjAArzJylqo3 8ADORy+R7TtAtS1mU7ovrxFAZvu4pVR93MwxTz5o= Received: by mx.zohomail.com with SMTPS id 1766512915055700.2932139936946; Tue, 23 Dec 2025 10:01:55 -0800 (PST) From: Ariel D'Alessandro Date: Tue, 23 Dec 2025 15:01:21 -0300 Subject: [PATCH v3 01/21] drm/crtc: Add color pipeline to CRTC state Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-post-blend-color-pipeline-v3-1-7d969f9a37a0@collabora.com> References: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> In-Reply-To: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Louis Chauvet , Haneen Mohammed , Melissa Wen Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Ariel D'Alessandro , Harry Wentland X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766512902; l=899; i=ariel.dalessandro@collabora.com; s=20251223; h=from:subject:message-id; bh=cz8QLVxeCXsQdnnR7HZ5l+beGwYFPs3Wl2Hw7fowgKM=; b=IXphtthoUydcY42e3vBK8Cy80DR1mbOU9n6zAW0xpiwZwSo2WCNhKb1LFydkLVFouA37u/rWS y6sefLFlYSbBvvbcJ9YtdYG9fAuatvnux7A/Fy/yyzkwd1H8fvXxCnc X-Developer-Key: i=ariel.dalessandro@collabora.com; a=ed25519; pk=QZRL9EsSBV3/FhDHi9L/7ZTz2dwa7iyqgl+y1UYaQXQ= X-ZohoMailClient: External From: "N=C3=ADcolas F. R. A. Prado" Add a color pipeline to the CRTC state to allow post-blend color pipelines. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Louis Chauvet Reviewed-by: Harry Wentland Reviewed-by: Ariel D'Alessandro --- include/drm/drm_crtc.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 66278ffeebd68..8490f4bc31260 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -274,6 +274,14 @@ struct drm_crtc_state { */ struct drm_property_blob *gamma_lut; =20 + /** + * @color_pipeline: + * + * The first colorop of the active color pipeline, or NULL, if no + * color pipeline is active. + */ + struct drm_colorop *color_pipeline; + /** * @target_vblank: * --=20 2.51.0 From nobody Mon Feb 9 08:12:13 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACB9F2F999F for ; Tue, 23 Dec 2025 18:02:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-post-blend-color-pipeline-v3-2-7d969f9a37a0@collabora.com> References: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> In-Reply-To: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Louis Chauvet , Haneen Mohammed , Melissa Wen Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Ariel D'Alessandro , Harry Wentland X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766512902; l=4585; i=ariel.dalessandro@collabora.com; s=20251223; h=from:subject:message-id; bh=+4lFHIOYldd0VRCezp6RS36U7f4KcV6URV+Z9zloWmk=; b=b2spIzcZQKGM2Y/y9vddf+sOUbr2tnLuzWDwuP1EReTKJoKMlIlaLzDTT33I09EwSE+6cTGyb C9ghTeKRmEZCLPFHdxOaOjiE1GkLnJdTRsllx0PUZY5oewz3ies06py X-Developer-Key: i=ariel.dalessandro@collabora.com; a=ed25519; pk=QZRL9EsSBV3/FhDHi9L/7ZTz2dwa7iyqgl+y1UYaQXQ= X-ZohoMailClient: External From: "N=C3=ADcolas F. R. A. Prado" In order to allow for post-blend color pipelines, colorops need to be assigned to a crtc rather than a plane. Add a crtc to the colorop struct to enable this. Either the plane or the crtc will be set for any given colorop depending on whether it is part of a pre- or post-blend color pipeline. Signed-off-by: N=C3=ADcolas F. R. A. Prado Co-developed-by: Ariel D'Alessandro Signed-off-by: Ariel D'Alessandro Reviewed-by: Louis Chauvet Reviewed-by: Harry Wentland --- drivers/gpu/drm/drm_atomic.c | 6 +++--- drivers/gpu/drm/drm_colorop.c | 25 +++++++++++++++++++++++++ include/drm/drm_colorop.h | 17 +++++++++++++++-- 3 files changed, 43 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 6d3ea8056b603..e9022d7ad04b0 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -620,7 +620,7 @@ drm_atomic_get_colorop_state(struct drm_atomic_state *s= tate, if (colorop_state) return colorop_state; =20 - ret =3D drm_modeset_lock(&colorop->plane->mutex, state->acquire_ctx); + ret =3D drm_colorop_modeset_lock(colorop, state->acquire_ctx); if (ret) return ERR_PTR(ret); =20 @@ -2012,10 +2012,10 @@ static void __drm_state_dump(struct drm_device *dev= , struct drm_printer *p, =20 list_for_each_entry(colorop, &config->colorop_list, head) { if (take_locks) - drm_modeset_lock(&colorop->plane->mutex, NULL); + drm_colorop_modeset_lock(colorop, NULL); drm_atomic_colorop_print_state(p, colorop->state); if (take_locks) - drm_modeset_unlock(&colorop->plane->mutex); + drm_colorop_modeset_unlock(colorop); } =20 list_for_each_entry(plane, &config->plane_list, head) { diff --git a/drivers/gpu/drm/drm_colorop.c b/drivers/gpu/drm/drm_colorop.c index 44eb823585d2e..bf3b8ff51571b 100644 --- a/drivers/gpu/drm/drm_colorop.c +++ b/drivers/gpu/drm/drm_colorop.c @@ -24,6 +24,7 @@ * */ =20 +#include #include #include #include @@ -597,3 +598,27 @@ void drm_colorop_set_next_property(struct drm_colorop = *colorop, struct drm_color colorop->next =3D next; } EXPORT_SYMBOL(drm_colorop_set_next_property); + +int drm_colorop_modeset_lock(struct drm_colorop *colorop, struct drm_modes= et_acquire_ctx *ctx) +{ + if (colorop->plane) + return drm_modeset_lock(&colorop->plane->mutex, ctx); + + if (colorop->crtc) + return drm_modeset_lock(&colorop->crtc->mutex, ctx); + + drm_err(colorop->dev, "Dangling colorop, it must be attached to a plane o= r a CRTC\n"); + return -EINVAL; +} +EXPORT_SYMBOL(drm_colorop_modeset_lock); + +void drm_colorop_modeset_unlock(struct drm_colorop *colorop) +{ + if (colorop->plane) + drm_modeset_unlock(&colorop->plane->mutex); + else if (colorop->crtc) + drm_modeset_unlock(&colorop->crtc->mutex); + else + drm_err(colorop->dev, "Dangling colorop, it must be attached to a plane = or a CRTC\n"); +} +EXPORT_SYMBOL(drm_colorop_modeset_unlock); diff --git a/include/drm/drm_colorop.h b/include/drm/drm_colorop.h index a3a32f9f918c7..49d342b7f8b0b 100644 --- a/include/drm/drm_colorop.h +++ b/include/drm/drm_colorop.h @@ -29,6 +29,7 @@ =20 #include #include +#include #include =20 /* DRM colorop flags */ @@ -223,11 +224,21 @@ struct drm_colorop { /** * @plane: * - * The plane on which the colorop sits. A drm_colorop is always unique - * to a plane. + * The plane on which the colorop sits if it is a pre-blend colorop. + * In this case it is unique to the plane. + * NOTE: plane and crtc are mutually exclusive. */ struct drm_plane *plane; =20 + /** + * @crtc: + * + * The CRTC on which the colorop sits if it is a post-blend colorop. + * In this case it is unique to the CRTC. + * NOTE: plane and crtc are mutually exclusive. + */ + struct drm_crtc *crtc; + /** * @state: * @@ -460,5 +471,7 @@ const char * drm_get_colorop_lut3d_interpolation_name(enum drm_colorop_lut3d_interpolat= ion_type type); =20 void drm_colorop_set_next_property(struct drm_colorop *colorop, struct drm= _colorop *next); +int drm_colorop_modeset_lock(struct drm_colorop *colorop, struct drm_modes= et_acquire_ctx *ctx); +void drm_colorop_modeset_unlock(struct drm_colorop *colorop); =20 #endif /* __DRM_COLOROP_H__ */ --=20 2.51.0 From nobody Mon Feb 9 08:12:13 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F36A2ECE85 for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-post-blend-color-pipeline-v3-3-7d969f9a37a0@collabora.com> References: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> In-Reply-To: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Louis Chauvet , Haneen Mohammed , Melissa Wen Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Ariel D'Alessandro X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766512902; l=4529; i=ariel.dalessandro@collabora.com; s=20251223; h=from:subject:message-id; bh=pXUAhGp4YOn3VSWvXDCPIq61Qsa1Bmj3Jy8ZAyYUCkc=; b=lYPrKkc9rid3IkMNgun/1saiJEubBmxIrZQQR0RDt8t0cH6mUxQFPUQOA7S0SZNjbYqD++7Rn MA1fgpIg1gHBrYKgb4VdoOS0VMFpDZ/ECGAq0JrLhKIILztVMf2R+sG X-Developer-Key: i=ariel.dalessandro@collabora.com; a=ed25519; pk=QZRL9EsSBV3/FhDHi9L/7ZTz2dwa7iyqgl+y1UYaQXQ= X-ZohoMailClient: External From: "N=C3=ADcolas F. R. A. Prado" In preparation for sharing the initialization code for the color pipeline property between pre-blend (plane) and post-blend (crtc) color pipelines, factor out the common initialization to a separate function. Signed-off-by: N=C3=ADcolas F. R. A. Prado Co-developed-by: Ariel D'Alessandro Signed-off-by: Ariel D'Alessandro Reviewed-by: Louis Chauvet --- drivers/gpu/drm/drm_plane.c | 35 ++++----------------------------- drivers/gpu/drm/drm_property.c | 44 ++++++++++++++++++++++++++++++++++++++= ++++ include/drm/drm_property.h | 5 +++++ 3 files changed, 53 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index bed2562bf911b..3d7324757d7b2 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -1839,43 +1839,16 @@ int drm_plane_create_color_pipeline_property(struct= drm_plane *plane, const struct drm_prop_enum_list *pipelines, int num_pipelines) { - struct drm_prop_enum_list *all_pipelines; struct drm_property *prop; - int len =3D 0; - int i; - - all_pipelines =3D kcalloc(num_pipelines + 1, - sizeof(*all_pipelines), - GFP_KERNEL); - - if (!all_pipelines) { - drm_err(plane->dev, "failed to allocate color pipeline\n"); - return -ENOMEM; - } - - /* Create default Bypass color pipeline */ - all_pipelines[len].type =3D 0; - all_pipelines[len].name =3D "Bypass"; - len++; =20 - /* Add all other color pipelines */ - for (i =3D 0; i < num_pipelines; i++, len++) { - all_pipelines[len].type =3D pipelines[i].type; - all_pipelines[len].name =3D pipelines[i].name; - } + prop =3D drm_property_create_color_pipeline(plane->dev, &plane->base, + pipelines, num_pipelines); + if (IS_ERR(prop)) + return PTR_ERR(prop); =20 - prop =3D drm_property_create_enum(plane->dev, DRM_MODE_PROP_ATOMIC, - "COLOR_PIPELINE", - all_pipelines, len); - if (!prop) { - kfree(all_pipelines); - return -ENOMEM; - } =20 - drm_object_attach_property(&plane->base, prop, 0); plane->color_pipeline_property =3D prop; =20 - kfree(all_pipelines); return 0; } EXPORT_SYMBOL(drm_plane_create_color_pipeline_property); diff --git a/drivers/gpu/drm/drm_property.c b/drivers/gpu/drm/drm_property.c index 596272149a359..cc2a1422599ac 100644 --- a/drivers/gpu/drm/drm_property.c +++ b/drivers/gpu/drm/drm_property.c @@ -997,3 +997,47 @@ void drm_property_change_valid_put(struct drm_property= *property, } else if (drm_property_type_is(property, DRM_MODE_PROP_BLOB)) drm_property_blob_put(obj_to_blob(ref)); } + +struct drm_property * +drm_property_create_color_pipeline(struct drm_device *dev, struct drm_mode= _object *obj, + const struct drm_prop_enum_list *pipelines, + int num_pipelines) +{ + struct drm_prop_enum_list *all_pipelines; + struct drm_property *prop; + int len =3D 0; + int i; + + all_pipelines =3D kcalloc(num_pipelines + 1, + sizeof(*all_pipelines), + GFP_KERNEL); + + if (!all_pipelines) { + drm_err(dev, "failed to allocate color pipeline\n"); + return ERR_PTR(-ENOMEM); + } + + /* Create default Bypass color pipeline */ + all_pipelines[len].type =3D 0; + all_pipelines[len].name =3D "Bypass"; + len++; + + /* Add all other color pipelines */ + for (i =3D 0; i < num_pipelines; i++, len++) { + all_pipelines[len].type =3D pipelines[i].type; + all_pipelines[len].name =3D pipelines[i].name; + } + + prop =3D drm_property_create_enum(dev, DRM_MODE_PROP_ATOMIC, + "COLOR_PIPELINE", + all_pipelines, len); + if (!prop) { + kfree(all_pipelines); + return ERR_PTR(-ENOMEM); + } + + drm_object_attach_property(obj, prop, 0); + + kfree(all_pipelines); + return prop; +} diff --git a/include/drm/drm_property.h b/include/drm/drm_property.h index 082f29156b3e3..3acf340635226 100644 --- a/include/drm/drm_property.h +++ b/include/drm/drm_property.h @@ -296,6 +296,11 @@ bool drm_property_replace_blob(struct drm_property_blo= b **blob, struct drm_property_blob *drm_property_blob_get(struct drm_property_blob *= blob); void drm_property_blob_put(struct drm_property_blob *blob); =20 +struct drm_property * +drm_property_create_color_pipeline(struct drm_device *dev, struct drm_mode= _object *obj, + const struct drm_prop_enum_list *pipelines, + int num_pipelines); + /** * drm_property_find - find property object * @dev: DRM device --=20 2.51.0 From nobody Mon Feb 9 08:12:13 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BEDC2E54BB for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-post-blend-color-pipeline-v3-4-7d969f9a37a0@collabora.com> References: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> In-Reply-To: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Louis Chauvet , Haneen Mohammed , Melissa Wen Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Ariel D'Alessandro X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766512902; l=7203; i=ariel.dalessandro@collabora.com; s=20251223; h=from:subject:message-id; bh=YB1+hkXA1HGdyeKDXoHQeTfPUOFoak8L7NumiJSe/xM=; b=N6SRDG7MQoLpRppDC8gcNccMMa5ye+Iq5+BtPRqqyPyVAeFKxksTFn4S5gD6TyC3Hb2biX7ZL 4Y6ubjCPEGjBm7wVRnoQRvZYRgcABK656WJ18qa+T9LDM2W6R6RyGHV X-Developer-Key: i=ariel.dalessandro@collabora.com; a=ed25519; pk=QZRL9EsSBV3/FhDHi9L/7ZTz2dwa7iyqgl+y1UYaQXQ= X-ZohoMailClient: External From: "N=C3=ADcolas F. R. A. Prado" Add a COLOR_PIPELINE property to the CRTC to allow userspace to set a post-blend color pipeline analogously to how pre-blend color pipelines are set on planes. Signed-off-by: N=C3=ADcolas F. R. A. Prado Co-developed-by: Ariel D'Alessandro Signed-off-by: Ariel D'Alessandro --- drivers/gpu/drm/drm_atomic_uapi.c | 50 +++++++++++++++++++++++++++++++++++= ---- drivers/gpu/drm/drm_crtc.c | 31 ++++++++++++++++++++++++ include/drm/drm_atomic_uapi.h | 2 ++ include/drm/drm_crtc.h | 11 +++++++++ 4 files changed, 90 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic= _uapi.c index 7320db4b8489f..07d0d224fe58c 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -286,6 +286,34 @@ drm_atomic_set_colorop_for_plane(struct drm_plane_stat= e *plane_state, } EXPORT_SYMBOL(drm_atomic_set_colorop_for_plane); =20 +/** + * drm_atomic_set_colorop_for_crtc - set colorop for crtc + * @crtc_state: atomic state object for the crtc + * @colorop: colorop to use for the crtc + * + * Helper function to select the color pipeline on a crtc by setting + * it to the first drm_colorop element of the pipeline. + */ +void +drm_atomic_set_colorop_for_crtc(struct drm_crtc_state *crtc_state, + struct drm_colorop *colorop) +{ + struct drm_crtc *crtc =3D crtc_state->crtc; + + if (colorop) + drm_dbg_atomic(crtc->dev, + "Set [COLOROP:%d] for [CRTC:%d:%s] state %p\n", + colorop->base.id, crtc->base.id, crtc->name, + crtc_state); + else + drm_dbg_atomic(crtc->dev, + "Set [NOCOLOROP] for [CRTC:%d:%s] state %p\n", + crtc->base.id, crtc->name, crtc_state); + + crtc_state->color_pipeline =3D colorop; +} +EXPORT_SYMBOL(drm_atomic_set_colorop_for_crtc); + /** * drm_atomic_set_crtc_for_connector - set CRTC for connector * @conn_state: atomic state object for the connector @@ -394,8 +422,8 @@ static s32 __user *get_out_fence_for_connector(struct d= rm_atomic_state *state, } =20 static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, - struct drm_crtc_state *state, struct drm_property *property, - uint64_t val) + struct drm_crtc_state *state, struct drm_file *file_priv, + struct drm_property *property, uint64_t val) { struct drm_device *dev =3D crtc->dev; struct drm_mode_config *config =3D &dev->mode_config; @@ -404,7 +432,17 @@ static int drm_atomic_crtc_set_property(struct drm_crt= c *crtc, =20 if (property =3D=3D config->prop_active) state->active =3D val; - else if (property =3D=3D config->prop_mode_id) { + else if (property =3D=3D crtc->color_pipeline_property) { + /* find DRM colorop object */ + struct drm_colorop *colorop =3D NULL; + + colorop =3D drm_colorop_find(dev, file_priv, val); + + if (val && !colorop) + return -EACCES; + + drm_atomic_set_colorop_for_crtc(state, colorop); + } else if (property =3D=3D config->prop_mode_id) { struct drm_property_blob *mode =3D drm_property_lookup_blob(dev, val); ret =3D drm_atomic_set_mode_prop_for_crtc(state, mode); @@ -489,6 +527,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc, *val =3D state->scaling_filter; else if (property =3D=3D crtc->sharpness_strength_property) *val =3D state->sharpness_strength; + else if (property =3D=3D crtc->color_pipeline_property) + *val =3D (state->color_pipeline) ? state->color_pipeline->base.id : 0; else if (crtc->funcs->atomic_get_property) return crtc->funcs->atomic_get_property(crtc, state, property, val); else { @@ -1050,6 +1090,8 @@ int drm_atomic_get_property(struct drm_mode_object *o= bj, =20 if (colorop->plane) WARN_ON(!drm_modeset_is_locked(&colorop->plane->mutex)); + else if (colorop->crtc) + WARN_ON(!drm_modeset_is_locked(&colorop->crtc->mutex)); =20 ret =3D drm_atomic_colorop_get_property(colorop, colorop->state, propert= y, val); break; @@ -1206,7 +1248,7 @@ int drm_atomic_set_property(struct drm_atomic_state *= state, } =20 ret =3D drm_atomic_crtc_set_property(crtc, - crtc_state, prop, prop_value); + crtc_state, file_priv, prop, prop_value); break; } case DRM_MODE_OBJECT_PLANE: { diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index a7797d260f1e2..133ff9212fbc4 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -994,3 +994,34 @@ bool drm_crtc_in_clone_mode(struct drm_crtc_state *crt= c_state) return hweight32(crtc_state->encoder_mask) > 1; } EXPORT_SYMBOL(drm_crtc_in_clone_mode); + +/** + * drm_crtc_create_color_pipeline_property - create a new color pipeline + * property + * + * @crtc: drm CRTC + * @pipelines: list of pipelines + * @num_pipelines: number of pipelines + * + * Create the COLOR_PIPELINE CRTC property to specify color pipelines on + * the CRTC. + * + * RETURNS: + * Zero for success or -errno + */ +int drm_crtc_create_color_pipeline_property(struct drm_crtc *crtc, + const struct drm_prop_enum_list *pipelines, + int num_pipelines) +{ + struct drm_property *prop; + + prop =3D drm_property_create_color_pipeline(crtc->dev, &crtc->base, + pipelines, num_pipelines); + if (IS_ERR(prop)) + return PTR_ERR(prop); + + crtc->color_pipeline_property =3D prop; + + return 0; +} +EXPORT_SYMBOL(drm_crtc_create_color_pipeline_property); diff --git a/include/drm/drm_atomic_uapi.h b/include/drm/drm_atomic_uapi.h index 4363155233267..4dc191f6f929d 100644 --- a/include/drm/drm_atomic_uapi.h +++ b/include/drm/drm_atomic_uapi.h @@ -52,6 +52,8 @@ void drm_atomic_set_fb_for_plane(struct drm_plane_state *= plane_state, struct drm_framebuffer *fb); void drm_atomic_set_colorop_for_plane(struct drm_plane_state *plane_state, struct drm_colorop *colorop); +void drm_atomic_set_colorop_for_crtc(struct drm_crtc_state *crtc_state, + struct drm_colorop *colorop); int __must_check drm_atomic_set_crtc_for_connector(struct drm_connector_state *conn_state, struct drm_crtc *crtc); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 8490f4bc31260..b3c9818715851 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -1113,6 +1113,14 @@ struct drm_crtc { */ struct drm_property *sharpness_strength_property; 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R. A. Prado" Add a new cap that drivers can set to signal they support CRTC (a.k.a. post-blend) color pipelines. Signed-off-by: N=C3=ADcolas F. R. A. Prado Co-developed-by: Ariel D'Alessandro Signed-off-by: Ariel D'Alessandro Reviewed-by: Louis Chauvet --- drivers/gpu/drm/drm_ioctl.c | 3 +++ include/drm/drm_drv.h | 6 ++++++ include/uapi/drm/drm.h | 6 ++++++ 3 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index ff193155129e7..2884075660ddd 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl.c @@ -304,6 +304,9 @@ static int drm_getcap(struct drm_device *dev, void *dat= a, struct drm_file *file_ req->value =3D drm_core_check_feature(dev, DRIVER_ATOMIC) && dev->mode_config.async_page_flip; break; + case DRM_CAP_CRTC_COLOR_PIPELINE: + req->value =3D drm_core_check_feature(dev, DRIVER_CRTC_COLOR_PIPELINE); + break; default: return -EINVAL; } diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h index 42fc085f986de..2a57c50b4223e 100644 --- a/include/drm/drm_drv.h +++ b/include/drm/drm_drv.h @@ -122,6 +122,12 @@ enum drm_driver_feature { * the cursor planes to work correctly). */ DRIVER_CURSOR_HOTSPOT =3D BIT(9), + /** + * @DRIVER_CRTC_COLOR_PIPELINE: + * + * Driver supports CRTC (post-blend) color pipeline. + */ + DRIVER_CRTC_COLOR_PIPELINE =3D BIT(10), =20 /* IMPORTANT: Below are all the legacy flags, add new ones above. */ =20 diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h index 27cc159c1d275..d726828bdf408 100644 --- a/include/uapi/drm/drm.h +++ b/include/uapi/drm/drm.h @@ -812,6 +812,12 @@ struct drm_gem_change_handle { * commits. */ #define DRM_CAP_ATOMIC_ASYNC_PAGE_FLIP 0x15 +/** + * DRM_CAP_CRTC_COLOR_PIPELINE + * + * If set to 1, the driver supports CRTC (post-blend) color pipelines. + */ +#define DRM_CAP_CRTC_COLOR_PIPELINE 0x16 =20 /* DRM_IOCTL_GET_CAP ioctl argument type */ struct drm_get_cap { --=20 2.51.0 From nobody Mon Feb 9 08:12:13 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABE152E06ED for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-post-blend-color-pipeline-v3-6-7d969f9a37a0@collabora.com> References: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> In-Reply-To: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Louis Chauvet , Haneen Mohammed , Melissa Wen Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Ariel D'Alessandro X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766512902; l=7784; i=ariel.dalessandro@collabora.com; s=20251223; h=from:subject:message-id; bh=fqIEVxRuDhlbZZQggPdeHf7nE1KjEiR2JRGFblrRdRw=; b=vvHwtG8UJ0+HhQ4FXXiOUxLBNsJc9qFqr8F82gLDkR8wDN0s83TA/BwSPHgKzfE0jsJtCWoDB iECu3QlxdO8CyzR/5N/1Pki/eWRegxWfrhhPrKjYahaH3wgVIQFR4y4 X-Developer-Key: i=ariel.dalessandro@collabora.com; a=ed25519; pk=QZRL9EsSBV3/FhDHi9L/7ZTz2dwa7iyqgl+y1UYaQXQ= X-ZohoMailClient: External From: "N=C3=ADcolas F. R. A. Prado" Introduce DRM_CLIENT_CAP_CRTC_COLOR_PIPELINE which a DRM client can set to enable the usage of CRTC (post-blend) color pipelines instead of the now deprecated CRTC color management properties: "GAMMA_LUT", "DEGAMMA_LUT" and "CTM". Signed-off-by: N=C3=ADcolas F. R. A. Prado Co-developed-by: Ariel D'Alessandro Signed-off-by: Ariel D'Alessandro Reviewed-by: Louis Chauvet --- drivers/gpu/drm/drm_atomic_uapi.c | 20 ++++++++++++++++++++ drivers/gpu/drm/drm_connector.c | 1 + drivers/gpu/drm/drm_crtc_internal.h | 1 + drivers/gpu/drm/drm_ioctl.c | 9 +++++++++ drivers/gpu/drm/drm_mode_object.c | 9 +++++++++ include/drm/drm_file.h | 7 +++++++ include/uapi/drm/drm.h | 19 +++++++++++++++++++ 7 files changed, 66 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic= _uapi.c index 07d0d224fe58c..d1bc78b2567a9 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -433,6 +433,11 @@ static int drm_atomic_crtc_set_property(struct drm_crt= c *crtc, if (property =3D=3D config->prop_active) state->active =3D val; else if (property =3D=3D crtc->color_pipeline_property) { + if (!file_priv->crtc_color_pipeline) { + drm_dbg_atomic(dev, + "Setting COLOR_PIPELINE CRTC property not permitted without DRM_CLIENT= _CAP_CRTC_COLOR_PIPELINE client cap\n"); + return -EINVAL; + } /* find DRM colorop object */ struct drm_colorop *colorop =3D NULL; =20 @@ -451,6 +456,11 @@ static int drm_atomic_crtc_set_property(struct drm_crt= c *crtc, } else if (property =3D=3D config->prop_vrr_enabled) { state->vrr_enabled =3D val; } else if (property =3D=3D config->degamma_lut_property) { + if (file_priv->crtc_color_pipeline) { + drm_dbg_atomic(dev, + "Setting DEGAMMA_LUT CRTC property not permitted with DRM_CLIENT_CAP_C= RTC_COLOR_PIPELINE client cap\n"); + return -EINVAL; + } ret =3D drm_property_replace_blob_from_id(dev, &state->degamma_lut, val, @@ -459,6 +469,11 @@ static int drm_atomic_crtc_set_property(struct drm_crt= c *crtc, state->color_mgmt_changed |=3D replaced; return ret; } else if (property =3D=3D config->ctm_property) { + if (file_priv->crtc_color_pipeline) { + drm_dbg_atomic(dev, + "Setting CTM CRTC property not permitted with DRM_CLIENT_CAP_CRTC_COLO= R_PIPELINE client cap\n"); + return -EINVAL; + } ret =3D drm_property_replace_blob_from_id(dev, &state->ctm, val, @@ -467,6 +482,11 @@ static int drm_atomic_crtc_set_property(struct drm_crt= c *crtc, state->color_mgmt_changed |=3D replaced; return ret; } else if (property =3D=3D config->gamma_lut_property) { + if (file_priv->crtc_color_pipeline) { + drm_dbg_atomic(dev, + "Setting GAMMA_LUT CRTC property not permitted with DRM_CLIENT_CAP_CRT= C_COLOR_PIPELINE client cap\n"); + return -EINVAL; + } ret =3D drm_property_replace_blob_from_id(dev, &state->gamma_lut, val, diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connecto= r.c index 4d6dc9ebfdb5b..aec8a5c0d593a 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c @@ -3440,6 +3440,7 @@ int drm_mode_getconnector(struct drm_device *dev, voi= d *data, */ ret =3D drm_mode_object_get_properties(&connector->base, file_priv->atomi= c, file_priv->plane_color_pipeline, + file_priv->crtc_color_pipeline, (uint32_t __user *)(unsigned long)(out_resp->props_ptr), (uint64_t __user *)(unsigned long)(out_resp->prop_values_ptr), &out_resp->count_props); diff --git a/drivers/gpu/drm/drm_crtc_internal.h b/drivers/gpu/drm/drm_crtc= _internal.h index c094092296448..ab02e6295271d 100644 --- a/drivers/gpu/drm/drm_crtc_internal.h +++ b/drivers/gpu/drm/drm_crtc_internal.h @@ -164,6 +164,7 @@ void drm_mode_object_unregister(struct drm_device *dev, struct drm_mode_object *object); int drm_mode_object_get_properties(struct drm_mode_object *obj, bool atomi= c, bool plane_color_pipeline, + bool crtc_color_pipeline, uint32_t __user *prop_ptr, uint64_t __user *prop_values, uint32_t *arg_count_props); diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index 2884075660ddd..14746afd82783 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl.c @@ -383,6 +383,15 @@ drm_setclientcap(struct drm_device *dev, void *data, s= truct drm_file *file_priv) return -EINVAL; file_priv->plane_color_pipeline =3D req->value; break; + case DRM_CLIENT_CAP_CRTC_COLOR_PIPELINE: + if (!file_priv->atomic) + return -EINVAL; + if (req->value > 1) + return -EINVAL; + if (!drm_core_check_feature(dev, DRIVER_CRTC_COLOR_PIPELINE)) + return -EINVAL; + file_priv->crtc_color_pipeline =3D req->value; + break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/drm_mode_object.c b/drivers/gpu/drm/drm_mode_o= bject.c index b45d501b10c86..ea4508f6a09a6 100644 --- a/drivers/gpu/drm/drm_mode_object.c +++ b/drivers/gpu/drm/drm_mode_object.c @@ -388,6 +388,7 @@ EXPORT_SYMBOL(drm_object_property_get_default_value); /* helper for getconnector and getproperties ioctls */ int drm_mode_object_get_properties(struct drm_mode_object *obj, bool atomi= c, bool plane_color_pipeline, + bool crtc_color_pipeline, uint32_t __user *prop_ptr, uint64_t __user *prop_values, uint32_t *arg_count_props) @@ -416,6 +417,13 @@ int drm_mode_object_get_properties(struct drm_mode_obj= ect *obj, bool atomic, continue; } =20 + if (!crtc_color_pipeline && obj->type =3D=3D DRM_MODE_OBJECT_CRTC) { + struct drm_crtc *crtc =3D obj_to_crtc(obj); + + if (prop =3D=3D crtc->color_pipeline_property) + continue; + } + if (*arg_count_props > count) { ret =3D __drm_object_property_get_value(obj, prop, &val); if (ret) @@ -475,6 +483,7 @@ int drm_mode_obj_get_properties_ioctl(struct drm_device= *dev, void *data, =20 ret =3D drm_mode_object_get_properties(obj, file_priv->atomic, file_priv->plane_color_pipeline, + file_priv->crtc_color_pipeline, (uint32_t __user *)(unsigned long)(arg->props_ptr), (uint64_t __user *)(unsigned long)(arg->prop_values_ptr), &arg->count_props); diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h index 6ee70ad65e1fd..d0c323378ae46 100644 --- a/include/drm/drm_file.h +++ b/include/drm/drm_file.h @@ -214,6 +214,13 @@ struct drm_file { */ bool plane_color_pipeline; =20 + /** + * @crtc_color_pipeline: + * + * True if client understands CRTC (post-blend) color pipelines + */ + bool crtc_color_pipeline; + /** * @was_master: * diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h index d726828bdf408..991ef14c5377c 100644 --- a/include/uapi/drm/drm.h +++ b/include/uapi/drm/drm.h @@ -927,6 +927,25 @@ struct drm_get_cap { */ #define DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE 7 =20 +/** + * DRM_CLIENT_CAP_CRTC_COLOR_PIPELINE + * + * If set to 1 the DRM core will allow setting the COLOR_PIPELINE + * property on a &drm_crtc, as well as drm_colorop properties. + * + * Setting of these crtc properties will be rejected when this client + * cap is set: + * - GAMMA_LUT + * - DEGAMMA_LUT + * - CTM + * + * The client must enable &DRM_CLIENT_CAP_ATOMIC first. + * + * This client cap can only be set if the driver sets the corresponding dr= iver + * cap &DRM_CAP_CRTC_COLOR_PIPELINE. + */ +#define DRM_CLIENT_CAP_CRTC_COLOR_PIPELINE 8 + /* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ struct drm_set_client_cap { __u64 capability; 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R. A. Prado" Pass the state of the CRTC (post-blend) color pipeline client cap to the atomic state so that drivers can rely on it to enable color pipeline functionality and ignore the deprecated color management CRTC properties. Signed-off-by: N=C3=ADcolas F. R. A. Prado Co-developed-by: Ariel D'Alessandro Signed-off-by: Ariel D'Alessandro Reviewed-by: Louis Chauvet --- drivers/gpu/drm/drm_atomic_uapi.c | 1 + include/drm/drm_atomic.h | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic= _uapi.c index d1bc78b2567a9..03f5a80448d10 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -1668,6 +1668,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev, state->acquire_ctx =3D &ctx; state->allow_modeset =3D !!(arg->flags & DRM_MODE_ATOMIC_ALLOW_MODESET); state->plane_color_pipeline =3D file_priv->plane_color_pipeline; + state->crtc_color_pipeline =3D file_priv->crtc_color_pipeline; =20 retry: copied_objs =3D 0; diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index 74ce26fa8838b..7eb21c0426105 100644 --- a/include/drm/drm_atomic.h +++ b/include/drm/drm_atomic.h @@ -560,6 +560,26 @@ struct drm_atomic_state { */ bool plane_color_pipeline : 1; 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R. A. Prado" Print the value of the color pipeline in the CRTC state as part of the CRTC state print. Signed-off-by: N=C3=ADcolas F. R. A. Prado Co-developed-by: Ariel D'Alessandro Signed-off-by: Ariel D'Alessandro Reviewed-by: Louis Chauvet Reviewed-by: Harry Wentland --- drivers/gpu/drm/drm_atomic.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index e9022d7ad04b0..aa4aa2f589b3d 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -475,6 +475,8 @@ static void drm_atomic_crtc_print_state(struct drm_prin= ter *p, drm_printf(p, "\tplane_mask=3D%x\n", state->plane_mask); drm_printf(p, "\tconnector_mask=3D%x\n", state->connector_mask); drm_printf(p, "\tencoder_mask=3D%x\n", state->encoder_mask); + drm_printf(p, "\tcolor-pipeline=3D%d\n", + state->color_pipeline ? state->color_pipeline->base.id : 0); drm_printf(p, "\tmode: " DRM_MODE_FMT "\n", DRM_MODE_ARG(&state->mode)); =20 if (crtc->funcs->atomic_print_state) --=20 2.51.0 From nobody Mon Feb 9 08:12:13 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C69232BF35 for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-post-blend-color-pipeline-v3-9-7d969f9a37a0@collabora.com> References: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> In-Reply-To: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Louis Chauvet , Haneen Mohammed , Melissa Wen Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Ariel D'Alessandro , Harry Wentland X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766512902; l=8035; i=ariel.dalessandro@collabora.com; s=20251223; h=from:subject:message-id; bh=5Qni8H4yUQhtfmB3ydT1m5AL0OONphS8F8GXu44wugo=; b=IzIHGHHAg4aiERlzri8xSRIIzbx0Vof/Kv9r5nHjhaH7BfQCsvvmvolnAS7nGYUEbyr4QFDxd i7w968a9jKGC6xEv5fp7Ebg63623cB2mijjg+tmAHInvt5Zij5rad00 X-Developer-Key: i=ariel.dalessandro@collabora.com; a=ed25519; pk=QZRL9EsSBV3/FhDHi9L/7ZTz2dwa7iyqgl+y1UYaQXQ= X-ZohoMailClient: External From: "N=C3=ADcolas F. R. A. Prado" Factor out the common code paths from the colorop helpers so they can be reused by the post-blend colorop helpers. Signed-off-by: N=C3=ADcolas F. R. A. Prado Co-developed-by: Ariel D'Alessandro Signed-off-by: Ariel D'Alessandro Reviewed-by: Louis Chauvet Reviewed-by: Harry Wentland --- drivers/gpu/drm/drm_colorop.c | 146 ++++++++++++++++++++++++++++----------= ---- 1 file changed, 99 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/drm_colorop.c b/drivers/gpu/drm/drm_colorop.c index bf3b8ff51571b..6a285cdb0a354 100644 --- a/drivers/gpu/drm/drm_colorop.c +++ b/drivers/gpu/drm/drm_colorop.c @@ -93,9 +93,9 @@ static const struct drm_prop_enum_list drm_colorop_lut3d_= interpolation_list[] =3D =20 /* Init Helpers */ =20 -static int drm_plane_colorop_init(struct drm_device *dev, struct drm_color= op *colorop, - struct drm_plane *plane, enum drm_colorop_type type, - uint32_t flags) +static int drm_common_colorop_init(struct drm_device *dev, + struct drm_colorop *colorop, + enum drm_colorop_type type, uint32_t flags) { struct drm_mode_config *config =3D &dev->mode_config; struct drm_property *prop; @@ -108,7 +108,6 @@ static int drm_plane_colorop_init(struct drm_device *de= v, struct drm_colorop *co colorop->base.properties =3D &colorop->properties; colorop->dev =3D dev; colorop->type =3D type; - colorop->plane =3D plane; colorop->next =3D NULL; =20 list_add_tail(&colorop->head, &config->colorop_list); @@ -157,6 +156,20 @@ static int drm_plane_colorop_init(struct drm_device *d= ev, struct drm_colorop *co return ret; } =20 +static int drm_plane_colorop_init(struct drm_device *dev, + struct drm_colorop *colorop, + struct drm_plane *plane, + enum drm_colorop_type type, uint32_t flags) +{ + int ret; + + ret =3D drm_common_colorop_init(dev, colorop, type, flags); + + colorop->plane =3D plane; + + return ret; +} + /** * drm_colorop_cleanup - Cleanup a drm_colorop object in color_pipeline * @@ -210,31 +223,13 @@ EXPORT_SYMBOL(drm_colorop_pipeline_destroy); * @flags: bitmask of misc, see DRM_COLOROP_FLAG_* defines. * @return zero on success, -E value on failure */ -int drm_plane_colorop_curve_1d_init(struct drm_device *dev, struct drm_col= orop *colorop, - struct drm_plane *plane, u64 supported_tfs, uint32_t flags) +static int drm_common_colorop_curve_1d_init(struct drm_device *dev, struct= drm_colorop *colorop, + u64 supported_tfs, uint32_t flags) { struct drm_prop_enum_list enum_list[DRM_COLOROP_1D_CURVE_COUNT]; int i, len; =20 struct drm_property *prop; - int ret; - - if (!supported_tfs) { - drm_err(dev, - "No supported TFs for new 1D curve colorop on [PLANE:%d:%s]\n", - plane->base.id, plane->name); - return -EINVAL; - } - - if ((supported_tfs & -BIT(DRM_COLOROP_1D_CURVE_COUNT)) !=3D 0) { - drm_err(dev, "Unknown TF provided on [PLANE:%d:%s]\n", - plane->base.id, plane->name); - return -EINVAL; - } - - ret =3D drm_plane_colorop_init(dev, colorop, plane, DRM_COLOROP_1D_CURVE,= flags); - if (ret) - return ret; =20 len =3D 0; for (i =3D 0; i < DRM_COLOROP_1D_CURVE_COUNT; i++) { @@ -263,6 +258,41 @@ int drm_plane_colorop_curve_1d_init(struct drm_device = *dev, struct drm_colorop * =20 return 0; } + +static int drm_colorop_has_supported_tf(struct drm_device *dev, struct drm= _mode_object *obj, + const char *name, u64 supported_tfs) +{ + if (!supported_tfs) { + drm_err(dev, + "No supported TFs for new 1D curve colorop on [PLANE:%d:%s]\n", + obj->id, name); + return -EINVAL; + } + + if ((supported_tfs & -BIT(DRM_COLOROP_1D_CURVE_COUNT)) !=3D 0) { + drm_err(dev, "Unknown TF provided on [PLANE:%d:%s]\n", + obj->id, name); + return -EINVAL; + } + + return 0; +} + +int drm_plane_colorop_curve_1d_init(struct drm_device *dev, struct drm_col= orop *colorop, + struct drm_plane *plane, u64 supported_tfs, uint32_t flags) +{ + int ret; + + ret =3D drm_colorop_has_supported_tf(dev, &plane->base, plane->name, supp= orted_tfs); + if (ret) + return ret; + + ret =3D drm_plane_colorop_init(dev, colorop, plane, DRM_COLOROP_1D_CURVE,= flags); + if (ret) + return ret; + + return drm_common_colorop_curve_1d_init(dev, colorop, supported_tfs, flag= s); +} EXPORT_SYMBOL(drm_plane_colorop_curve_1d_init); =20 static int drm_colorop_create_data_prop(struct drm_device *dev, struct drm= _colorop *colorop) @@ -283,29 +313,16 @@ static int drm_colorop_create_data_prop(struct drm_de= vice *dev, struct drm_color return 0; } =20 -/** - * drm_plane_colorop_curve_1d_lut_init - Initialize a DRM_COLOROP_1D_LUT - * - * @dev: DRM device - * @colorop: The drm_colorop object to initialize - * @plane: The associated drm_plane - * @lut_size: LUT size supported by driver - * @interpolation: 1D LUT interpolation type - * @flags: bitmask of misc, see DRM_COLOROP_FLAG_* defines. - * @return zero on success, -E value on failure - */ -int drm_plane_colorop_curve_1d_lut_init(struct drm_device *dev, struct drm= _colorop *colorop, - struct drm_plane *plane, uint32_t lut_size, - enum drm_colorop_lut1d_interpolation_type interpolation, - uint32_t flags) +static int +drm_common_colorop_curve_1d_lut_init(struct drm_device *dev, + struct drm_colorop *colorop, + uint32_t lut_size, + enum drm_colorop_lut1d_interpolation_type interpolation, + uint32_t flags) { struct drm_property *prop; int ret; =20 - ret =3D drm_plane_colorop_init(dev, colorop, plane, DRM_COLOROP_1D_LUT, f= lags); - if (ret) - return ret; - /* initialize 1D LUT only attribute */ /* LUT size */ prop =3D drm_property_create_range(dev, DRM_MODE_PROP_IMMUTABLE | DRM_MOD= E_PROP_ATOMIC, @@ -337,17 +354,40 @@ int drm_plane_colorop_curve_1d_lut_init(struct drm_de= vice *dev, struct drm_color =20 return 0; } -EXPORT_SYMBOL(drm_plane_colorop_curve_1d_lut_init); =20 -int drm_plane_colorop_ctm_3x4_init(struct drm_device *dev, struct drm_colo= rop *colorop, - struct drm_plane *plane, uint32_t flags) +/** + * drm_plane_colorop_curve_1d_lut_init - Initialize a DRM_COLOROP_1D_LUT + * + * @dev: DRM device + * @colorop: The drm_colorop object to initialize + * @plane: The associated drm_plane + * @lut_size: LUT size supported by driver + * @lut1d_interpolation: 1D LUT interpolation type + * @flags: bitmask of misc, see DRM_COLOROP_FLAG_* defines. + * @return zero on success, -E value on failure + */ +int +drm_plane_colorop_curve_1d_lut_init(struct drm_device *dev, struct drm_col= orop *colorop, + struct drm_plane *plane, uint32_t lut_size, + enum drm_colorop_lut1d_interpolation_type lut1d_interpolation, + uint32_t flags) { int ret; =20 - ret =3D drm_plane_colorop_init(dev, colorop, plane, DRM_COLOROP_CTM_3X4, = flags); + ret =3D drm_plane_colorop_init(dev, colorop, plane, DRM_COLOROP_1D_LUT, f= lags); if (ret) return ret; =20 + return drm_common_colorop_curve_1d_lut_init(dev, colorop, lut_size, + lut1d_interpolation, flags); +} +EXPORT_SYMBOL(drm_plane_colorop_curve_1d_lut_init); + +static int drm_common_colorop_ctm_3x4_init(struct drm_device *dev, struct = drm_colorop *colorop, + uint32_t flags) +{ + int ret; + ret =3D drm_colorop_create_data_prop(dev, colorop); if (ret) return ret; @@ -356,6 +396,18 @@ int drm_plane_colorop_ctm_3x4_init(struct drm_device *= dev, struct drm_colorop *c =20 return 0; } + +int drm_plane_colorop_ctm_3x4_init(struct drm_device *dev, struct drm_colo= rop *colorop, + struct drm_plane *plane, uint32_t flags) +{ + int ret; + + ret =3D drm_plane_colorop_init(dev, colorop, plane, DRM_COLOROP_CTM_3X4, = flags); + if (ret) + return ret; + + return drm_common_colorop_ctm_3x4_init(dev, colorop, flags); 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Tue, 23 Dec 2025 10:02:52 -0800 (PST) From: Ariel D'Alessandro Date: Tue, 23 Dec 2025 15:01:30 -0300 Subject: [PATCH v3 10/21] drm/colorop: Introduce colorop helpers for crtc Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-post-blend-color-pipeline-v3-10-7d969f9a37a0@collabora.com> References: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> In-Reply-To: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Louis Chauvet , Haneen Mohammed , Melissa Wen Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Ariel D'Alessandro , Harry Wentland X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766512902; l=5692; i=ariel.dalessandro@collabora.com; s=20251223; h=from:subject:message-id; bh=v0EzVWC7HEgCjd42dLnml/cxbQFKAH2Q9oqX72sE3fA=; b=kWReBGXutszJ7qMtObxq1/TFBTxud2uZa8rd5ksSCLzA9UbuQs2UQvbLg8S1VWV6ky6VvK/tI P+kPxlBuHMgB6iWgALXCYyLYOxH30Lk6g/eQkDSb2IskJWDT2YCCjFQ X-Developer-Key: i=ariel.dalessandro@collabora.com; a=ed25519; pk=QZRL9EsSBV3/FhDHi9L/7ZTz2dwa7iyqgl+y1UYaQXQ= X-ZohoMailClient: External From: "N=C3=ADcolas F. R. A. Prado" Introduce colorop helper counterparts for post-blend color pipelines that take a CRTC instead of a plane. Signed-off-by: N=C3=ADcolas F. R. A. Prado Co-developed-by: Ariel D'Alessandro Signed-off-by: Ariel D'Alessandro Reviewed-by: Louis Chauvet Reviewed-by: Harry Wentland --- drivers/gpu/drm/drm_colorop.c | 73 +++++++++++++++++++++++++++++++++++++++= ++++ include/drm/drm_colorop.h | 8 +++++ 2 files changed, 81 insertions(+) diff --git a/drivers/gpu/drm/drm_colorop.c b/drivers/gpu/drm/drm_colorop.c index 6a285cdb0a354..4ce93807ea565 100644 --- a/drivers/gpu/drm/drm_colorop.c +++ b/drivers/gpu/drm/drm_colorop.c @@ -170,6 +170,20 @@ static int drm_plane_colorop_init(struct drm_device *d= ev, return ret; } =20 +static int drm_crtc_colorop_init(struct drm_device *dev, + struct drm_colorop *colorop, + struct drm_crtc *crtc, + enum drm_colorop_type type, uint32_t flags) +{ + int ret; + + ret =3D drm_common_colorop_init(dev, colorop, type, flags); + + colorop->crtc =3D crtc; + + return ret; +} + /** * drm_colorop_cleanup - Cleanup a drm_colorop object in color_pipeline * @@ -295,6 +309,23 @@ int drm_plane_colorop_curve_1d_init(struct drm_device = *dev, struct drm_colorop * } EXPORT_SYMBOL(drm_plane_colorop_curve_1d_init); =20 +int drm_crtc_colorop_curve_1d_init(struct drm_device *dev, struct drm_colo= rop *colorop, + struct drm_crtc *crtc, u64 supported_tfs, uint32_t flags) +{ + int ret; + + ret =3D drm_colorop_has_supported_tf(dev, &crtc->base, crtc->name, suppor= ted_tfs); + if (ret) + return ret; + + ret =3D drm_crtc_colorop_init(dev, colorop, crtc, DRM_COLOROP_1D_CURVE, f= lags); + if (ret) + return ret; + + return drm_common_colorop_curve_1d_init(dev, colorop, supported_tfs, flag= s); +} +EXPORT_SYMBOL(drm_crtc_colorop_curve_1d_init); + static int drm_colorop_create_data_prop(struct drm_device *dev, struct drm= _colorop *colorop) { struct drm_property *prop; @@ -383,6 +414,35 @@ drm_plane_colorop_curve_1d_lut_init(struct drm_device = *dev, struct drm_colorop * } EXPORT_SYMBOL(drm_plane_colorop_curve_1d_lut_init); =20 +/** + * drm_crtc_colorop_curve_1d_lut_init - Initialize a DRM_COLOROP_1D_LUT + * + * @dev: DRM device + * @colorop: The drm_colorop object to initialize + * @crtc: The associated drm_crtc + * @lut_size: LUT size supported by driver + * @interpolation: 1D LUT interpolation type + * @flags: bitmask of misc, see DRM_COLOROP_FLAG_* defines. + * @return zero on success, -E value on failure + */ +int +drm_crtc_colorop_curve_1d_lut_init(struct drm_device *dev, + struct drm_colorop *colorop, + struct drm_crtc *crtc, uint32_t lut_size, + enum drm_colorop_lut1d_interpolation_type interpolation, + uint32_t flags) +{ + int ret; + + ret =3D drm_crtc_colorop_init(dev, colorop, crtc, DRM_COLOROP_1D_LUT, fla= gs); + if (ret) + return ret; + + return drm_common_colorop_curve_1d_lut_init(dev, colorop, lut_size, + interpolation, flags); +} +EXPORT_SYMBOL(drm_crtc_colorop_curve_1d_lut_init); + static int drm_common_colorop_ctm_3x4_init(struct drm_device *dev, struct = drm_colorop *colorop, uint32_t flags) { @@ -410,6 +470,19 @@ int drm_plane_colorop_ctm_3x4_init(struct drm_device *= dev, struct drm_colorop *c } EXPORT_SYMBOL(drm_plane_colorop_ctm_3x4_init); =20 +int drm_crtc_colorop_ctm_3x4_init(struct drm_device *dev, struct drm_color= op *colorop, + struct drm_crtc *crtc, uint32_t flags) +{ + int ret; + + ret =3D drm_crtc_colorop_init(dev, colorop, crtc, DRM_COLOROP_CTM_3X4, fl= ags); + if (ret) + return ret; + + return drm_common_colorop_ctm_3x4_init(dev, colorop, flags); +} +EXPORT_SYMBOL(drm_crtc_colorop_ctm_3x4_init); + /** * drm_plane_colorop_mult_init - Initialize a DRM_COLOROP_MULTIPLIER * diff --git a/include/drm/drm_colorop.h b/include/drm/drm_colorop.h index 49d342b7f8b0b..a1f81fa96f66b 100644 --- a/include/drm/drm_colorop.h +++ b/include/drm/drm_colorop.h @@ -400,14 +400,22 @@ static inline struct drm_colorop *drm_colorop_find(st= ruct drm_device *dev, void drm_colorop_pipeline_destroy(struct drm_device *dev); void drm_colorop_cleanup(struct drm_colorop *colorop); =20 +int drm_crtc_colorop_curve_1d_lut_init(struct drm_device *dev, struct drm_= colorop *colorop, + struct drm_crtc *crtc, uint32_t lut_size, + enum drm_colorop_lut1d_interpolation_type interpolation, + uint32_t flags); int drm_plane_colorop_curve_1d_init(struct drm_device *dev, struct drm_col= orop *colorop, struct drm_plane *plane, u64 supported_tfs, uint32_t flags); +int drm_crtc_colorop_curve_1d_init(struct drm_device *dev, struct drm_colo= rop *colorop, + struct drm_crtc *crtc, u64 supported_tfs, uint32_t flags); int drm_plane_colorop_curve_1d_lut_init(struct drm_device *dev, struct drm= _colorop *colorop, struct drm_plane *plane, uint32_t lut_size, enum drm_colorop_lut1d_interpolation_type interpolation, uint32_t flags); int drm_plane_colorop_ctm_3x4_init(struct drm_device *dev, struct drm_colo= rop *colorop, struct drm_plane *plane, uint32_t flags); +int drm_crtc_colorop_ctm_3x4_init(struct drm_device *dev, struct drm_color= op *colorop, + struct drm_crtc *crtc, uint32_t flags); int drm_plane_colorop_mult_init(struct drm_device *dev, struct drm_colorop= *colorop, struct drm_plane *plane, uint32_t flags); int drm_plane_colorop_3dlut_init(struct drm_device *dev, struct drm_coloro= p *colorop, --=20 2.51.0 From nobody Mon Feb 9 08:12:13 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16D05346FA7 for ; Tue, 23 Dec 2025 18:03:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766513006; cv=pass; b=GozSkzNtu/olPtgrz/I3rAGfUjM24R7hgM0zlCIBEKP8nXkXyak+hE/y6G5O2f/w3/fsVS93XLP7319ZviXmMH5yZb5h6zy8A1s9M3Px0t9i1tMrWKbCJigWGMI2GM2zCOsgsseUDyEw+XrhArRQpp8vU/QMXGWLz6UE7Y8oGQ0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=8Pk1bOdW4DywWabgxSmZe43EDBa8FOVNt1pDyMGplsA=; b=JRy2l6R5GGvx9HTc2uRjX2cFIaGCFAVbQo7R3n79V2pZjad7AVE8RwqpNKHUPGyi hrJJwmJzIEhKQafLjMrLG8q1pl2SFAsRvoG9rTxYgEvJUX0Phcyc5AHHyPoR3xm6FOm 2SfZ4BOfGjXVSQC4JBLGrcD4hNA7pzmtAsw78cZ8= Received: by mx.zohomail.com with SMTPS id 1766512978817141.00038080090178; Tue, 23 Dec 2025 10:02:58 -0800 (PST) From: Ariel D'Alessandro Date: Tue, 23 Dec 2025 15:01:31 -0300 Subject: [PATCH v3 11/21] drm/crtc: Track crtc color pipeline client cap in drm_crtc_state Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-post-blend-color-pipeline-v3-11-7d969f9a37a0@collabora.com> References: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> In-Reply-To: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Louis Chauvet , Haneen Mohammed , Melissa Wen Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Ariel D'Alessandro , Harry Wentland X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766512902; l=1933; i=ariel.dalessandro@collabora.com; s=20251223; h=from:subject:message-id; bh=3y10C5Mwu/sdD+b5xMD3KEubR/Wzf/qSO2/9lBdGz3o=; b=piU06VW6Rl48awo5uv5SX1zI/5YEPFJ0cxQgVVOvlt363GPtteLDdhpnFWzhcfHHyT2tMBw/R Fdx9od8x/GCCd4jiMR2k26flrfj50B4XPqKt4UT8SfifTpfvA+OzH3d X-Developer-Key: i=ariel.dalessandro@collabora.com; a=ed25519; pk=QZRL9EsSBV3/FhDHi9L/7ZTz2dwa7iyqgl+y1UYaQXQ= X-ZohoMailClient: External From: "N=C3=ADcolas F. R. A. Prado" Some drivers, like VKMS, only have access to the drm_crtc_state but not the drm_atomic_state during composition of the output framebuffer. Store the state of the CRTC (post-blend) color pipeline client cap in the drm_crtc_state so those drivers can decide whether to look at the color pipeline or the legacy properties for the color management settings to apply. Signed-off-by: N=C3=ADcolas F. R. A. Prado Co-developed-by: Ariel D'Alessandro Signed-off-by: Ariel D'Alessandro Reviewed-by: Louis Chauvet Reviewed-by: Harry Wentland --- drivers/gpu/drm/drm_atomic.c | 1 + include/drm/drm_crtc.h | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index aa4aa2f589b3d..f2028e6cdd62f 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -389,6 +389,7 @@ drm_atomic_get_crtc_state(struct drm_atomic_state *stat= e, state->crtcs[index].new_state =3D crtc_state; state->crtcs[index].ptr =3D crtc; crtc_state->state =3D state; + crtc_state->color_pipeline_enabled =3D state->crtc_color_pipeline; =20 drm_dbg_atomic(state->dev, "Added [CRTC:%d:%s] %p state to %p\n", crtc->base.id, crtc->name, crtc_state, state); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index b3c9818715851..888a3a5aa3a27 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -282,6 +282,14 @@ struct drm_crtc_state { */ struct drm_colorop *color_pipeline; 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R. A. Prado" Allow configuring the gamma and ccorr blocks through the CRTC color pipeline API instead of the GAMMA_LUT and CTM properties. In order to achieve this, initialize the color pipeline property and colorops on the CRTC based on the DDP components available in the CRTC path. Then introduce a struct mtk_drm_colorop that extends drm_colorop and tracks the mtk_ddp_comp that implements it in hardware, and include new ddp_comp helper functions for setting gamma and ctm through the new API. These helpers will then be called during commit flush for every updated colorop if the DRM client supports the CRTC (post-blend) color pipeline API. Signed-off-by: N=C3=ADcolas F. R. A. Prado Co-developed-by: Ariel D'Alessandro Signed-off-by: Ariel D'Alessandro --- drivers/gpu/drm/mediatek/mtk_crtc.c | 222 ++++++++++++++++++++++++++++= +++- drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 2 + 2 files changed, 219 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek= /mtk_crtc.c index 991cdb3d7d5fd..1ed3157fa91f0 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -83,6 +83,12 @@ struct mtk_crtc_state { unsigned int pending_vrefresh; }; =20 +struct mtk_drm_colorop { + struct drm_colorop colorop; + struct mtk_ddp_comp *comp; + uint32_t data_id; +}; + static inline struct mtk_crtc *to_mtk_crtc(struct drm_crtc *c) { return container_of(c, struct mtk_crtc, base); @@ -93,6 +99,11 @@ static inline struct mtk_crtc_state *to_mtk_crtc_state(s= truct drm_crtc_state *s) return container_of(s, struct mtk_crtc_state, base); } =20 +static inline struct mtk_drm_colorop *to_mtk_colorop(struct drm_colorop *c= olorop) +{ + return container_of(colorop, struct mtk_drm_colorop, colorop); +} + static void mtk_crtc_finish_page_flip(struct mtk_crtc *mtk_crtc) { struct drm_crtc *crtc =3D &mtk_crtc->base; @@ -126,6 +137,19 @@ static void mtk_drm_finish_page_flip(struct mtk_crtc *= mtk_crtc) spin_unlock_irqrestore(&mtk_crtc->config_lock, flags); } =20 +static void mtk_drm_colorop_pipeline_destroy(struct drm_device *dev) +{ + struct drm_mode_config *config =3D &dev->mode_config; + struct drm_colorop *colorop, *next; + struct mtk_drm_colorop *mtk_colorop; + + list_for_each_entry_safe(colorop, next, &config->colorop_list, head) { + drm_colorop_cleanup(colorop); + mtk_colorop =3D to_mtk_colorop(colorop); + kfree(mtk_colorop); + } +} + static void mtk_crtc_destroy(struct drm_crtc *crtc) { struct mtk_crtc *mtk_crtc =3D to_mtk_crtc(crtc); @@ -147,6 +171,8 @@ static void mtk_crtc_destroy(struct drm_crtc *crtc) mtk_ddp_comp_unregister_vblank_cb(comp); } =20 + mtk_drm_colorop_pipeline_destroy(crtc->dev); + drm_crtc_cleanup(crtc); } =20 @@ -862,20 +888,103 @@ static void mtk_crtc_atomic_begin(struct drm_crtc *c= rtc, } } =20 +static bool colorop_data_update_flush_status(struct drm_colorop_state *col= orop_state) +{ + struct drm_colorop *colorop =3D colorop_state->colorop; + struct mtk_drm_colorop *mtk_colorop =3D to_mtk_colorop(colorop); + struct drm_property_blob *data_blob =3D colorop_state->data; + uint32_t data_id =3D colorop_state->bypass ? 0 : data_blob->base.id; + bool needs_flush =3D mtk_colorop->data_id !=3D data_id; + + mtk_colorop->data_id =3D data_id; + + return needs_flush; +} + +static void mtk_crtc_ddp_comp_apply_colorop(struct drm_colorop_state *colo= rop_state) +{ + struct drm_colorop *colorop =3D colorop_state->colorop; + struct mtk_drm_colorop *mtk_colorop =3D to_mtk_colorop(colorop); + struct drm_property_blob *data_blob =3D colorop_state->data; + struct mtk_ddp_comp *ddp_comp =3D mtk_colorop->comp; + struct drm_color_ctm_3x4 *ctm =3D NULL; + struct drm_color_lut32 *lut =3D NULL; + + switch (colorop->type) { + case DRM_COLOROP_1D_LUT: + if (!colorop_data_update_flush_status(colorop_state)) + return; + + if (!colorop_state->bypass) + lut =3D (struct drm_color_lut32 *)data_blob->data; + + ddp_comp->funcs->gamma_set_color_pipeline(ddp_comp->dev, lut); + break; + case DRM_COLOROP_CTM_3X4: + if (!colorop_data_update_flush_status(colorop_state)) + return; + + if (!colorop_state->bypass) + ctm =3D (struct drm_color_ctm_3x4 *)data_blob->data; + + ddp_comp->funcs->ctm_set_color_pipeline(ddp_comp->dev, ctm); + break; + default: + /* If this happens the driver is broken */ + drm_WARN(colorop->dev, 1, + "Trying to atomic flush COLOROP of type unsupported by driver: %d\n", + colorop->type); + break; + } +} + static void mtk_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state) { struct mtk_crtc *mtk_crtc =3D to_mtk_crtc(crtc); + struct drm_colorop_state *new_colorop_state; + struct drm_colorop *colorop; int i; =20 - if (crtc->state->color_mgmt_changed) - for (i =3D 0; i < mtk_crtc->ddp_comp_nr; i++) { - mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); - mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); - } + if (state->crtc_color_pipeline) { + for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) + mtk_crtc_ddp_comp_apply_colorop(new_colorop_state); + } else { + if (crtc->state->color_mgmt_changed) + for (i =3D 0; i < mtk_crtc->ddp_comp_nr; i++) { + mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); + } + } mtk_crtc_update_config(mtk_crtc, !!mtk_crtc->event); } =20 +static int mtk_crtc_atomic_check(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + struct drm_colorop_state *new_colorop_state; + struct drm_colorop *colorop; + int i; + + for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) { + switch (colorop->type) { + case DRM_COLOROP_1D_LUT: + case DRM_COLOROP_CTM_3X4: + if (!new_colorop_state->bypass && !new_colorop_state->data) { + drm_dbg_atomic(crtc->dev, + "Missing required DATA property for COLOROP:%d\n", + colorop->base.id); + return -EINVAL; + } + break; + default: + break; + } + } + + return 0; +} + static const struct drm_crtc_funcs mtk_crtc_funcs =3D { .set_config =3D drm_atomic_helper_set_config, .page_flip =3D drm_atomic_helper_page_flip, @@ -893,6 +1002,7 @@ static const struct drm_crtc_helper_funcs mtk_crtc_hel= per_funcs =3D { .mode_valid =3D mtk_crtc_mode_valid, .atomic_begin =3D mtk_crtc_atomic_begin, .atomic_flush =3D mtk_crtc_atomic_flush, + .atomic_check =3D mtk_crtc_atomic_check, .atomic_enable =3D mtk_crtc_atomic_enable, .atomic_disable =3D mtk_crtc_atomic_disable, }; @@ -995,6 +1105,100 @@ struct device *mtk_crtc_dma_dev_get(struct drm_crtc = *crtc) return mtk_crtc->dma_dev; } =20 +#define MAX_COLOR_PIPELINE_OPS 2 +#define MAX_COLOR_PIPELINES 1 + +static int mtk_colorop_init(struct mtk_crtc *mtk_crtc, + struct mtk_drm_colorop *mtk_colorop, + struct mtk_ddp_comp *ddp_comp) +{ + struct drm_colorop *colorop =3D &mtk_colorop->colorop; + int ret =3D 0; + + if (ddp_comp->funcs->gamma_set_color_pipeline) { + unsigned int lut_sz =3D mtk_ddp_gamma_get_lut_size(ddp_comp); + + ret =3D drm_crtc_colorop_curve_1d_lut_init(mtk_crtc->base.dev, colorop, + &mtk_crtc->base, + lut_sz, + DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR, + DRM_COLOROP_FLAG_ALLOW_BYPASS); + } else if (ddp_comp->funcs->ctm_set_color_pipeline) { + ret =3D drm_crtc_colorop_ctm_3x4_init(mtk_crtc->base.dev, + colorop, + &mtk_crtc->base, + DRM_COLOROP_FLAG_ALLOW_BYPASS); + } + + mtk_colorop->comp =3D ddp_comp; + + return ret; +} + +static int mtk_crtc_init_crtc_color_pipeline(struct mtk_crtc *mtk_crtc, + unsigned int gamma_lut_size) +{ + struct drm_prop_enum_list pipelines[MAX_COLOR_PIPELINES]; + struct drm_colorop *ops[MAX_COLOR_PIPELINE_OPS]; + struct mtk_drm_colorop *mtk_colorop; + unsigned int num_pipelines =3D 0; + unsigned int op_idx =3D 0; + int ret; + int j; + + memset(ops, 0, sizeof(ops)); + + for (unsigned int i =3D 0; + i < mtk_crtc->ddp_comp_nr && op_idx < MAX_COLOR_PIPELINE_OPS; + i++) { + struct mtk_ddp_comp *ddp_comp =3D mtk_crtc->ddp_comp[i]; + + if (!(ddp_comp->funcs->gamma_set_color_pipeline || + ddp_comp->funcs->ctm_set_color_pipeline)) + continue; + + mtk_colorop =3D kzalloc(sizeof(struct mtk_drm_colorop), GFP_KERNEL); + if (!mtk_colorop) { + ret =3D -ENOMEM; + goto cleanup; + } + + ops[op_idx] =3D &mtk_colorop->colorop; + + ret =3D mtk_colorop_init(mtk_crtc, mtk_colorop, ddp_comp); + if (ret) + goto cleanup; + + if (op_idx > 0) + drm_colorop_set_next_property(ops[op_idx-1], ops[op_idx]); + + op_idx++; + } + + if (op_idx > 0) { + pipelines[0].type =3D ops[0]->base.id; + pipelines[0].name =3D kasprintf(GFP_KERNEL, "Color Pipeline %d", ops[0]-= >base.id); + num_pipelines =3D 1; + } + + /* Create COLOR_PIPELINE property and attach */ + drm_crtc_create_color_pipeline_property(&mtk_crtc->base, pipelines, num_p= ipelines); + + return 0; + +cleanup: + for (j =3D 0; j < op_idx; j++) { + if (ops[j]) { + drm_colorop_cleanup(ops[j]); + mtk_colorop =3D to_mtk_colorop(ops[j]); + kfree(mtk_colorop); + kfree(ops[j]); + } + } + + return ret; +} + int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path, unsigned int path_len, int priv_data_index, const struct mtk_drm_route *conn_routes, @@ -1111,6 +1315,10 @@ int mtk_crtc_create(struct drm_device *drm_dev, cons= t unsigned int *path, if (ret < 0) return ret; =20 + ret =3D mtk_crtc_init_crtc_color_pipeline(mtk_crtc, gamma_lut_size); + if (ret < 0) + goto err_cleanup_crtc; + if (gamma_lut_size) drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size); drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); @@ -1183,4 +1391,8 @@ int mtk_crtc_create(struct drm_device *drm_dev, const= unsigned int *path, } =20 return 0; + +err_cleanup_crtc: + drm_crtc_cleanup(&mtk_crtc->base); + return ret; } diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index 3f3d43f4330da..93665b5d5358c 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -75,10 +75,12 @@ struct mtk_ddp_comp_funcs { unsigned int (*gamma_get_lut_size)(struct device *dev); void (*gamma_set)(struct device *dev, struct drm_crtc_state *state); + void (*gamma_set_color_pipeline)(struct device *dev, struct drm_color_lut= 32 *lut); void (*bgclr_in_on)(struct device *dev); void (*bgclr_in_off)(struct device *dev); void (*ctm_set)(struct device *dev, struct drm_crtc_state *state); + void (*ctm_set_color_pipeline)(struct device *dev, struct drm_color_ctm_3= x4 *ctm); struct device * (*dma_dev_get)(struct device *dev); u32 (*get_blend_modes)(struct device *dev); const u32 *(*get_formats)(struct device *dev); --=20 2.51.0 From nobody Mon Feb 9 08:12:13 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FE7E349B0D for ; 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a=ed25519; pk=QZRL9EsSBV3/FhDHi9L/7ZTz2dwa7iyqgl+y1UYaQXQ= X-ZohoMailClient: External Add a common helper to ease the conversion from both 3x3 or 3x4 matrices to a CTM 3x4 matrix. This is handy for code that needs to handle both dimensions. Signed-off-by: Ariel D'Alessandro --- include/drm/drm_color_mgmt.h | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index 5140691f476a9..51279267ed3fd 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -66,6 +66,40 @@ static inline u32 drm_color_lut32_extract(u32 user_input= , int bit_precision) (1ULL << 32) - 1); } =20 +/** + * drm_color_ctm_to_ctm_3x4 - Copy CTM matrix contents to 3x4 dimensions m= atrix + * + * @dest: The destination CTM 3x4 dimensions matrix + * @src: The source CTM matrix (3x3 or 3x4 dimensions depending on @ctm_3x= 4) + * @ctm_3x4: Boolean indicating the source CTM matrix dimensions + * + * Copy the contents of a CTM matrix from @src, to a CTM 3x4 dimensions ma= trix. + * The source matrix can be 3x3 or 3x4 dimensions depending on the @ctm_3x4 + * boolean argument. + */ +static inline void drm_color_ctm_to_ctm_3x4(struct drm_color_ctm_3x4 *dest, + void *src, bool ctm_3x4) +{ + if (ctm_3x4) { + *dest =3D *(struct drm_color_ctm_3x4 *)src; + } else { + struct drm_color_ctm *ctm =3D (struct drm_color_ctm *)src; + + dest->matrix[0] =3D ctm->matrix[0]; + dest->matrix[1] =3D ctm->matrix[1]; + dest->matrix[2] =3D ctm->matrix[2]; + dest->matrix[3] =3D 0; + dest->matrix[4] =3D ctm->matrix[3]; + dest->matrix[5] =3D ctm->matrix[4]; + dest->matrix[6] =3D ctm->matrix[5]; + dest->matrix[7] =3D 0; + dest->matrix[8] =3D ctm->matrix[6]; + dest->matrix[9] =3D ctm->matrix[7]; + dest->matrix[10] =3D ctm->matrix[8]; + dest->matrix[11] =3D 0; + } +} + u64 drm_color_ctm_s31_32_to_qm_n(u64 user_input, u32 m, u32 n); =20 void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, --=20 2.51.0 From nobody Mon Feb 9 08:12:13 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E542332EBA for ; Tue, 23 Dec 2025 18:03:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-post-blend-color-pipeline-v3-14-7d969f9a37a0@collabora.com> References: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> In-Reply-To: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Louis Chauvet , Haneen Mohammed , Melissa Wen Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Ariel D'Alessandro X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766512902; l=6744; i=ariel.dalessandro@collabora.com; s=20251223; h=from:subject:message-id; bh=bVtBy+vJLyKASPZeIhRnivNNixPjniXmL7OSooko3zk=; b=J57pdVTE2PQvT/RMzQvbI8Rx8MWTtVOIpgtTnDR8L1lnfhRnWo7QuZraw9z1Rn/7e0z1ZOtf+ yBI0Qul4zujANX8Ix0A6JYnglzlCnJIzrjKvaMqZV4nBkDnngbVXjJg X-Developer-Key: i=ariel.dalessandro@collabora.com; a=ed25519; pk=QZRL9EsSBV3/FhDHi9L/7ZTz2dwa7iyqgl+y1UYaQXQ= X-ZohoMailClient: External From: "N=C3=ADcolas F. R. A. Prado" Implement the ctm_set_color_pipeline DDP component function to allow configuring the CTM through the color pipeline API. The color pipeline API only defines a 3x4 matrix, while the driver currently only supports setting the coefficients for a 3x3 matrix. However the underlying hardware does support setting the offset coefficients that make up a 3x4 matrix, so implement support for setting them so the 3x4 matrix structure for the API can be used as is. Also make sure to enable or disable the CTM function depending on whether the block should be bypassed or not. Signed-off-by: N=C3=ADcolas F. R. A. Prado Co-developed-by: Ariel D'Alessandro Signed-off-by: Ariel D'Alessandro --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 3 +- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 88 ++++++++++++++++++++++++---= ---- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 +- 3 files changed, 73 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index 9672ea1f91a2b..69eeb36609584 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -284,7 +284,8 @@ static const struct mtk_ddp_comp_funcs ddp_ccorr =3D { .config =3D mtk_ccorr_config, .start =3D mtk_ccorr_start, .stop =3D mtk_ccorr_stop, - .ctm_set =3D mtk_ccorr_ctm_set, + .ctm_set =3D mtk_ccorr_ctm_set_legacy, + .ctm_set_color_pipeline =3D mtk_ccorr_ctm_set_color_pipeline, }; =20 static const struct mtk_ddp_comp_funcs ddp_color =3D { diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/me= diatek/mtk_disp_ccorr.c index 6d7bf4afa78d3..e2bd8010d22e5 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -28,6 +28,11 @@ #define DISP_CCORR_COEF_2 0x0088 #define DISP_CCORR_COEF_3 0x008C #define DISP_CCORR_COEF_4 0x0090 +#define DISP_CCORR_OFFSET_0 0x0100 +#define CCORR_OFFSET_EN BIT(31) +#define DISP_CCORR_OFFSET_1 0x0104 +#define DISP_CCORR_OFFSET_2 0x0108 +#define DISP_CCORR_OFFSET_MASK GENMASK(26, 14) =20 struct mtk_disp_ccorr_data { u32 matrix_bits; @@ -80,36 +85,81 @@ void mtk_ccorr_stop(struct device *dev) writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); } =20 -void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) +static void mtk_ccorr_ctm_set(struct device *dev, struct cmdq_pkt *cmdq_pk= t, + void *ctm, bool ctm_3x4) { struct mtk_disp_ccorr *ccorr =3D dev_get_drvdata(dev); - struct drm_property_blob *blob =3D state->ctm; - struct drm_color_ctm *ctm; - const u64 *input; - uint16_t coeffs[9] =3D { 0 }; - int i; - struct cmdq_pkt *cmdq_pkt =3D NULL; u32 matrix_bits =3D ccorr->data->matrix_bits; + struct drm_color_ctm_3x4 coeffs; + u32 val; + int i; =20 - if (!blob) - return; + drm_color_ctm_to_ctm_3x4(&coeffs, ctm, ctm_3x4); =20 - ctm =3D (struct drm_color_ctm *)blob->data; - input =3D ctm->matrix; + for (i =3D 0; i < ARRAY_SIZE(coeffs.matrix); i++) + coeffs.matrix[i] =3D + drm_color_ctm_s31_32_to_qm_n(coeffs.matrix[i], 2, matrix_bits); =20 - for (i =3D 0; i < ARRAY_SIZE(coeffs); i++) - coeffs[i] =3D drm_color_ctm_s31_32_to_qm_n(input[i], 2, matrix_bits); - - mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], + mtk_ddp_write(cmdq_pkt, coeffs.matrix[0] << 16 | coeffs.matrix[1], &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); - mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], + mtk_ddp_write(cmdq_pkt, coeffs.matrix[2] << 16 | coeffs.matrix[4], &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_1); - mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], + mtk_ddp_write(cmdq_pkt, coeffs.matrix[5] << 16 | coeffs.matrix[6], &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_2); - mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], + mtk_ddp_write(cmdq_pkt, coeffs.matrix[8] << 16 | coeffs.matrix[9], &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3); - mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, + mtk_ddp_write(cmdq_pkt, coeffs.matrix[10] << 16, &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4); + + if (ctm_3x4) { + val =3D CCORR_OFFSET_EN; + val |=3D FIELD_PREP(DISP_CCORR_OFFSET_MASK, coeffs.matrix[3]); + mtk_ddp_write(cmdq_pkt, val, &ccorr->cmdq_reg, + ccorr->regs, DISP_CCORR_OFFSET_0); + val =3D FIELD_PREP(DISP_CCORR_OFFSET_MASK, coeffs.matrix[7]); + mtk_ddp_write(cmdq_pkt, val, &ccorr->cmdq_reg, + ccorr->regs, DISP_CCORR_OFFSET_1); + val =3D FIELD_PREP(DISP_CCORR_OFFSET_MASK, coeffs.matrix[11]); + mtk_ddp_write(cmdq_pkt, val, &ccorr->cmdq_reg, + ccorr->regs, DISP_CCORR_OFFSET_2); + } else { + mtk_ddp_write_mask(cmdq_pkt, 0, &ccorr->cmdq_reg, + ccorr->regs, DISP_CCORR_OFFSET_0, + CCORR_OFFSET_EN); + } + + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, + ccorr->regs, DISP_CCORR_CFG); +} + +void mtk_ccorr_ctm_set_legacy(struct device *dev, struct drm_crtc_state *s= tate) +{ + struct drm_property_blob *blob =3D state->ctm; + struct cmdq_pkt *cmdq_pkt =3D NULL; + struct drm_color_ctm *ctm; + + if (!blob) + return; + + ctm =3D (struct drm_color_ctm *)blob->data; + + mtk_ccorr_ctm_set(dev, cmdq_pkt, ctm, false); +} + +void mtk_ccorr_ctm_set_color_pipeline(struct device *dev, struct drm_color= _ctm_3x4 *ctm) +{ + struct mtk_disp_ccorr *ccorr =3D dev_get_drvdata(dev); + struct cmdq_pkt *cmdq_pkt =3D NULL; + + /* Configure block to be bypassed */ + if (!ctm) { + mtk_ddp_write_mask(cmdq_pkt, CCORR_RELAY_MODE, &ccorr->cmdq_reg, + ccorr->regs, DISP_CCORR_CFG, + CCORR_RELAY_MODE | CCORR_ENGINE_EN); + return; + } + + mtk_ccorr_ctm_set(dev, cmdq_pkt, ctm, true); } =20 static int mtk_disp_ccorr_bind(struct device *dev, struct device *master, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index 679d413bf10be..ac84cf579150f 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -22,7 +22,8 @@ void mtk_aal_gamma_set(struct device *dev, struct drm_crt= c_state *state); void mtk_aal_start(struct device *dev); void mtk_aal_stop(struct device *dev); =20 -void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state); +void mtk_ccorr_ctm_set_legacy(struct device *dev, struct drm_crtc_state *s= tate); +void mtk_ccorr_ctm_set_color_pipeline(struct device *dev, struct drm_color= _ctm_3x4 *ctm); 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Tue, 23 Dec 2025 10:03:23 -0800 (PST) From: Ariel D'Alessandro Date: Tue, 23 Dec 2025 15:01:35 -0300 Subject: [PATCH v3 15/21] drm: Add helper to extract a LUT entry from either 16-bit or 32-bit LUT Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-post-blend-color-pipeline-v3-15-7d969f9a37a0@collabora.com> References: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> In-Reply-To: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Louis Chauvet , Haneen Mohammed , Melissa Wen Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Ariel D'Alessandro X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766512902; l=1871; i=ariel.dalessandro@collabora.com; s=20251223; h=from:subject:message-id; bh=NyijHk7BrD1qg1wbKRwHg1Uug2fibA4RZ0UIzlvViFQ=; b=npmXvD1l++IAnjReNfPZLOzC8duyNX1bPNFwPZHbBm1mqMJHgUvPX4TpvD/F1HRdwxLe+S1TI fmAilhWHF0NC+GFLY7IvFtojfHxcSKgBcSnm3WpPBcpBR2gIF66XpyZ X-Developer-Key: i=ariel.dalessandro@collabora.com; a=ed25519; pk=QZRL9EsSBV3/FhDHi9L/7ZTz2dwa7iyqgl+y1UYaQXQ= X-ZohoMailClient: External Add a common helper to ease extracting a 32-bit LUT entry from either 16-bit or 32-bit LUT entry. This is handy for code that needs to handle both bit widths. Signed-off-by: Ariel D'Alessandro Co-developed-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: N=C3=ADcolas F. R. A. Prado --- include/drm/drm_color_mgmt.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index 51279267ed3fd..3d0117aae342d 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -66,6 +66,33 @@ static inline u32 drm_color_lut32_extract(u32 user_input= , int bit_precision) (1ULL << 32) - 1); } =20 +/** + * drm_color_lut_to_lut32 - Copy LUT entry contents to 32-bit channel colo= r LUT + * + * @dest: The destination 32-bit per channel color LUT entry + * @src: The source array of LUT entries (16-bit or 32-bit depending on @b= its32) + * @index: LUT entry array index + * @bits32: Boolean indicating the source LUT entry bit-witdh + * + * Copy the contents of a LUT entry from the source array, to a 32-bit cha= nnel + * color LUT. The source array of LUT entries can be 16-bit or 32-bit width + * depending on the @bits32 boolean argument. + */ +static inline void drm_color_lut_to_lut32(struct drm_color_lut32 *dest, + void *src, int index, bool bits32) +{ + if (bits32) { + *dest =3D ((struct drm_color_lut32 *)src)[index]; + } else { + struct drm_color_lut *lut =3D + &((struct drm_color_lut *)src)[index]; + dest->red =3D lut->red; + dest->green =3D lut->green; + dest->blue =3D lut->blue; + dest->reserved =3D lut->reserved; + } +} + /** * drm_color_ctm_to_ctm_3x4 - Copy CTM matrix contents to 3x4 dimensions m= atrix * --=20 2.51.0 From nobody Mon Feb 9 08:12:13 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC8D334AB09 for ; Tue, 23 Dec 2025 18:03:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-post-blend-color-pipeline-v3-16-7d969f9a37a0@collabora.com> References: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> In-Reply-To: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Louis Chauvet , Haneen Mohammed , Melissa Wen Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Ariel D'Alessandro X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766512902; l=7442; i=ariel.dalessandro@collabora.com; s=20251223; h=from:subject:message-id; bh=3Rn0eJNbPddwyTHTW3U8YMV9xPhZPXWC8FFqd7vGECc=; b=P6CrP7f1eSCkRckNgrp1pDFRV6y2Vp+63t7DPGC8s+VETpso4XDgCfKtNeG9JkBh1uvc2OFwr 8JAH4rv2IwCBKMtltxdzzFEbAZSgLkiinfLSjCYyjENywfotbp/fryH X-Developer-Key: i=ariel.dalessandro@collabora.com; a=ed25519; pk=QZRL9EsSBV3/FhDHi9L/7ZTz2dwa7iyqgl+y1UYaQXQ= X-ZohoMailClient: External From: "N=C3=ADcolas F. R. A. Prado" Implement the gamma_set_color_pipeline DDP component function to allow configuring the gamma LUT through the CRTC color pipeline API. The color pipeline API uses a 32-bit long, rather than 16-bit long, LUT, so also update the functions to handle both cases. Also make sure to enable or disable the LUT function depending on whether the block should be bypassed or not. Signed-off-by: N=C3=ADcolas F. R. A. Prado Co-developed-by: Ariel D'Alessandro Signed-off-by: Ariel D'Alessandro --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 3 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 +- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 68 +++++++++++++++++++++++----= ---- 3 files changed, 54 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index 69eeb36609584..cf456ab3cf70f 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -327,7 +327,8 @@ static const struct mtk_ddp_comp_funcs ddp_gamma =3D { .clk_enable =3D mtk_gamma_clk_enable, .clk_disable =3D mtk_gamma_clk_disable, .gamma_get_lut_size =3D mtk_gamma_get_lut_size, - .gamma_set =3D mtk_gamma_set, + .gamma_set =3D mtk_gamma_set_legacy, + .gamma_set_color_pipeline =3D mtk_gamma_set_color_pipeline, .config =3D mtk_gamma_config, .start =3D mtk_gamma_start, .stop =3D mtk_gamma_stop, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index ac84cf579150f..7795aa5bc057f 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -58,7 +58,8 @@ void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); unsigned int mtk_gamma_get_lut_size(struct device *dev); -void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); +void mtk_gamma_set_legacy(struct device *dev, struct drm_crtc_state *state= ); +void mtk_gamma_set_color_pipeline(struct device *dev, struct drm_color_lut= 32 *lut); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev); =20 diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 8afd15006df2a..efda0bbb0b09d 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -87,13 +87,17 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return 0; } =20 -static bool mtk_gamma_lut_is_descending(struct drm_color_lut *lut, u32 lut= _size) +static bool mtk_gamma_lut_is_descending(void *lut, bool bits32, u32 lut_si= ze) { u64 first, last; int last_entry =3D lut_size - 1; + struct drm_color_lut32 lut_first, lut_last; =20 - first =3D lut[0].red + lut[0].green + lut[0].blue; - last =3D lut[last_entry].red + lut[last_entry].green + lut[last_entry].bl= ue; + drm_color_lut_to_lut32(&lut_first, lut, 0, bits32); + drm_color_lut_to_lut32(&lut_last, lut, last_entry, bits32); + + first =3D lut_first.red + lut_first.green + lut_first.blue; + last =3D lut_last.red + lut_last.green + lut_last.blue; =20 return !!(first > last); } @@ -113,7 +117,7 @@ static bool mtk_gamma_lut_is_descending(struct drm_colo= r_lut *lut, u32 lut_size) * - 12-bits LUT supported * - 10-its LUT not supported */ -void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) +static void mtk_gamma_set(struct device *dev, void *lut, bool bits32) { struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); void __iomem *lut0_base =3D gamma->regs + DISP_GAMMA_LUT; @@ -121,15 +125,9 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc= _state *state) u32 cfg_val, data_mode, lbank_val, word[2]; u8 lut_bits =3D gamma->data->lut_bits; int cur_bank, num_lut_banks; - struct drm_color_lut *lut; unsigned int i; =20 - /* If there's no gamma lut there's nothing to do here. */ - if (!state->gamma_lut) - return; - num_lut_banks =3D gamma->data->lut_size / gamma->data->lut_bank_size; - lut =3D (struct drm_color_lut *)state->gamma_lut->data; =20 /* Switch to 12 bits data mode if supported */ data_mode =3D FIELD_PREP(DISP_GAMMA_BANK_DATA_MODE, !!(lut_bits =3D=3D 12= )); @@ -145,11 +143,13 @@ void mtk_gamma_set(struct device *dev, struct drm_crt= c_state *state) =20 for (i =3D 0; i < gamma->data->lut_bank_size; i++) { int n =3D cur_bank * gamma->data->lut_bank_size + i; - struct drm_color_lut diff, hwlut; + struct drm_color_lut32 diff, hwlut, lut32; + + drm_color_lut_to_lut32(&lut32, lut, n, bits32); =20 - hwlut.red =3D drm_color_lut_extract(lut[n].red, lut_bits); - hwlut.green =3D drm_color_lut_extract(lut[n].green, lut_bits); - hwlut.blue =3D drm_color_lut_extract(lut[n].blue, lut_bits); + hwlut.red =3D drm_color_lut_extract(lut32.red, lut_bits); + hwlut.green =3D drm_color_lut_extract(lut32.green, lut_bits); + hwlut.blue =3D drm_color_lut_extract(lut32.blue, lut_bits); =20 if (!gamma->data->lut_diff || (i % 2 =3D=3D 0)) { if (lut_bits =3D=3D 12) { @@ -162,13 +162,17 @@ void mtk_gamma_set(struct device *dev, struct drm_crt= c_state *state) word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); } } else { - diff.red =3D lut[n].red - lut[n - 1].red; + struct drm_color_lut32 lut_prev; + + drm_color_lut_to_lut32(&lut_prev, lut, n-1, bits32); + + diff.red =3D lut32.red - lut_prev.red; diff.red =3D drm_color_lut_extract(diff.red, lut_bits); =20 - diff.green =3D lut[n].green - lut[n - 1].green; + diff.green =3D lut32.green - lut_prev.green; diff.green =3D drm_color_lut_extract(diff.green, lut_bits); =20 - diff.blue =3D lut[n].blue - lut[n - 1].blue; + diff.blue =3D lut32.blue - lut_prev.blue; diff.blue =3D drm_color_lut_extract(diff.blue, lut_bits); =20 if (lut_bits =3D=3D 12) { @@ -191,7 +195,7 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_= state *state) =20 if (!gamma->data->has_dither) { /* Descending or Rising LUT */ - if (mtk_gamma_lut_is_descending(lut, gamma->data->lut_size - 1)) + if (mtk_gamma_lut_is_descending(lut, bits32, gamma->data->lut_size - 1)) cfg_val |=3D FIELD_PREP(GAMMA_LUT_TYPE, 1); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-post-blend-color-pipeline-v3-17-7d969f9a37a0@collabora.com> References: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> In-Reply-To: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Louis Chauvet , Haneen Mohammed , Melissa Wen Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Ariel D'Alessandro X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766512902; l=1133; i=ariel.dalessandro@collabora.com; s=20251223; h=from:subject:message-id; bh=8Jlby476xSmK6n5wnsQz9iEV6+65MeonxppBOVK4bOE=; b=sMHOtgI8xpup/GiLFGJKT3Dew/5W6qaT5slahFNalSzeOT78yvXT9yAR3bUqW/flhpwVJ8g7i zm8J4YdstTUDNGRtI1sy4vpemwTib2Vtamnn5AqDpRRmsDb+mKHn5zE X-Developer-Key: i=ariel.dalessandro@collabora.com; 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R. A. Prado" Now that the driver implements CRTC (post-blend) color pipelines, set the driver cap so they can be used from userspace. Signed-off-by: N=C3=ADcolas F. R. A. Prado Co-developed-by: Ariel D'Alessandro Signed-off-by: Ariel D'Alessandro Reviewed-by: Louis Chauvet --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index a94c51a832616..554b310ca11a5 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -613,7 +613,8 @@ static struct drm_gem_object *mtk_gem_prime_import(stru= ct drm_device *dev, } =20 static const struct drm_driver mtk_drm_driver =3D { - .driver_features =3D DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, + .driver_features =3D DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC | + DRIVER_CRTC_COLOR_PIPELINE, =20 .dumb_create =3D mtk_gem_dumb_create, DRM_FBDEV_DMA_DRIVER_OPS, --=20 2.51.0 From nobody Mon Feb 9 08:12:13 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7350F348889 for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-post-blend-color-pipeline-v3-18-7d969f9a37a0@collabora.com> References: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> In-Reply-To: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Louis Chauvet , Haneen Mohammed , Melissa Wen Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Ariel D'Alessandro X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766512902; l=2834; i=ariel.dalessandro@collabora.com; s=20251223; h=from:subject:message-id; bh=KYz5wMMzVLd2SIZeeSoKXiwrpNlBnDQ02lbiiWEro+k=; b=TxDXkdnWnCgHcCuWU/72ICAoXziIPVRr27YV5VQDtSLTm9PhA3UQU05rUsSDEkXnyNifvJIkU I37enLuFXh8CBR6smYEZSSrsGDuipiSs5Vv+oAwLOraxTcUPwd9RWGQ X-Developer-Key: i=ariel.dalessandro@collabora.com; a=ed25519; pk=QZRL9EsSBV3/FhDHi9L/7ZTz2dwa7iyqgl+y1UYaQXQ= X-ZohoMailClient: External From: "N=C3=ADcolas F. R. A. Prado" Rename the existing color pipeline helpers so they contain "plane" in the name to make them clearly distinguishable from the crtc helpers when they're introduced. Signed-off-by: N=C3=ADcolas F. R. A. Prado Co-developed-by: Ariel D'Alessandro Signed-off-by: Ariel D'Alessandro Reviewed-by: Louis Chauvet --- drivers/gpu/drm/vkms/vkms_colorop.c | 7 ++++--- drivers/gpu/drm/vkms/vkms_drv.h | 2 +- drivers/gpu/drm/vkms/vkms_plane.c | 2 +- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/vkms/vkms_colorop.c b/drivers/gpu/drm/vkms/vkm= s_colorop.c index 5c3ffc78aea06..dd6120434690e 100644 --- a/drivers/gpu/drm/vkms/vkms_colorop.c +++ b/drivers/gpu/drm/vkms/vkms_colorop.c @@ -14,7 +14,8 @@ static const u64 supported_tfs =3D =20 #define MAX_COLOR_PIPELINE_OPS 4 =20 -static int vkms_initialize_color_pipeline(struct drm_plane *plane, struct = drm_prop_enum_list *list) +static int vkms_initialize_plane_color_pipeline(struct drm_plane *plane, + struct drm_prop_enum_list *list) { struct drm_colorop *ops[MAX_COLOR_PIPELINE_OPS]; struct drm_device *dev =3D plane->dev; @@ -101,13 +102,13 @@ static int vkms_initialize_color_pipeline(struct drm_= plane *plane, struct drm_pr return ret; } =20 -int vkms_initialize_colorops(struct drm_plane *plane) +int vkms_initialize_plane_colorops(struct drm_plane *plane) { struct drm_prop_enum_list pipeline; int ret; =20 /* Add color pipeline */ - ret =3D vkms_initialize_color_pipeline(plane, &pipeline); + ret =3D vkms_initialize_plane_color_pipeline(plane, &pipeline); if (ret) return ret; =20 diff --git a/drivers/gpu/drm/vkms/vkms_drv.h b/drivers/gpu/drm/vkms/vkms_dr= v.h index 0933e4ce0ff03..bdeb52623f4d6 100644 --- a/drivers/gpu/drm/vkms/vkms_drv.h +++ b/drivers/gpu/drm/vkms/vkms_drv.h @@ -324,6 +324,6 @@ void vkms_writeback_row(struct vkms_writeback_job *wb, = const struct line_buffer int vkms_enable_writeback_connector(struct vkms_device *vkmsdev, struct vk= ms_output *vkms_out); =20 /* Colorops */ -int vkms_initialize_colorops(struct drm_plane *plane); +int vkms_initialize_plane_colorops(struct drm_plane *plane); =20 #endif /* _VKMS_DRV_H_ */ diff --git a/drivers/gpu/drm/vkms/vkms_plane.c b/drivers/gpu/drm/vkms/vkms_= plane.c index 19fe6acad306e..82be1b862c1da 100644 --- a/drivers/gpu/drm/vkms/vkms_plane.c +++ b/drivers/gpu/drm/vkms/vkms_plane.c @@ -247,7 +247,7 @@ struct vkms_plane *vkms_plane_init(struct vkms_device *= vkmsdev, DRM_COLOR_YCBCR_FULL_RANGE); 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Tue, 23 Dec 2025 10:03:49 -0800 (PST) From: Ariel D'Alessandro Date: Tue, 23 Dec 2025 15:01:39 -0300 Subject: [PATCH v3 19/21] drm/vkms: Prepare pre_blend_color_transform() for CRTC color pipelines Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-post-blend-color-pipeline-v3-19-7d969f9a37a0@collabora.com> References: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> In-Reply-To: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Louis Chauvet , Haneen Mohammed , Melissa Wen Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Ariel D'Alessandro X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766512902; l=1957; i=ariel.dalessandro@collabora.com; s=20251223; h=from:subject:message-id; bh=wsJbatjTPlzhi3WptySwhme0VyzXx04ZS+jdYLuA3I8=; b=MY1vFPnWjOA/GH8i8igHj4gI1U4rI4Fhfinif6+7eYhNEFMIhvet9acPb/YojlKVZPVJLm4lT du4sY3O+g54AWvfoib+fj+3NLFIGUHdBOol2UXFyJq9UmKRZJXU4vL5 X-Developer-Key: i=ariel.dalessandro@collabora.com; a=ed25519; pk=QZRL9EsSBV3/FhDHi9L/7ZTz2dwa7iyqgl+y1UYaQXQ= X-ZohoMailClient: External From: "N=C3=ADcolas F. R. A. Prado" As a preparatory step for supporting CRTC (post-blend) color pipelines in VKMS, rename pre_blend_color_transform() to color_transform() and make it take the first colorop instead of a plane state, so it can be shared by both plane (pre-blend) and CRTC (post-blend) color pipeline code paths. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Louis Chauvet Reviewed-by: Ariel D'Alessandro --- drivers/gpu/drm/vkms/vkms_composer.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/vkms/vkms_composer.c b/drivers/gpu/drm/vkms/vk= ms_composer.c index 3cf3f26e0d8ea..d4f87a2aa3359 100644 --- a/drivers/gpu/drm/vkms/vkms_composer.c +++ b/drivers/gpu/drm/vkms/vkms_composer.c @@ -189,13 +189,13 @@ static void apply_colorop(struct pixel_argb_s32 *pixe= l, struct drm_colorop *colo } } =20 -static void pre_blend_color_transform(const struct vkms_plane_state *plane= _state, - struct line_buffer *output_buffer) +static void color_transform(struct drm_colorop *first_colorop, + struct line_buffer *output_buffer) { struct pixel_argb_s32 pixel; =20 for (size_t x =3D 0; x < output_buffer->n_pixels; x++) { - struct drm_colorop *colorop =3D plane_state->base.base.color_pipeline; + struct drm_colorop *colorop =3D first_colorop; =20 /* * Some operations, such as applying a BT709 encoding matrix, @@ -449,7 +449,7 @@ static void blend_line(struct vkms_plane_state *current= _plane, int y, */ current_plane->pixel_read_line(current_plane, src_x_start, src_y_start, d= irection, pixel_count, &stage_buffer->pixels[dst_x_start]); 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=FeRG7njvwbygJrNNYWkjaIRjuu34zYpLBZS+iO4UDdw=; b=hgl2H8+Nf6NPIetCs3kwLhCS6eM8K9IjEAAYUmRXEoiGgItYFiqFeMCVAewK8AxX kMGAQTi8vtxNeO5iz2PP42ayM7vj2R2GLbxQG8eJRgWvaOBOrCs+76fhbhGQy4HQ3E9 jV3oZ1CP4Gy9xeuJgI++C542J1wiI2AISmNYX8mc= Received: by mx.zohomail.com with SMTPS id 1766513036570948.8621873004253; Tue, 23 Dec 2025 10:03:56 -0800 (PST) From: Ariel D'Alessandro Date: Tue, 23 Dec 2025 15:01:40 -0300 Subject: [PATCH v3 20/21] drm/vkms: Introduce support for post-blend color pipeline Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-post-blend-color-pipeline-v3-20-7d969f9a37a0@collabora.com> References: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> In-Reply-To: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Louis Chauvet , Haneen Mohammed , Melissa Wen Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Ariel D'Alessandro X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766512902; l=18618; i=ariel.dalessandro@collabora.com; s=20251223; h=from:subject:message-id; bh=9ihe7gr1oh1yCb5F3S0nmyJrcPjMQJ4FrIjaZY2Ce70=; b=57SJn01QRGOdXLCH5YJVER32sSro3vy/e/C4o/RGn/65CyUd1ts5EVcUD0bRJONsQBpf/XnlI hoOsVeBsUBKAsB+SpJ3tcu3YkH4JkJoZF3CDZbT1qmnb9FD5wKJpy0/ X-Developer-Key: i=ariel.dalessandro@collabora.com; a=ed25519; pk=QZRL9EsSBV3/FhDHi9L/7ZTz2dwa7iyqgl+y1UYaQXQ= X-ZohoMailClient: External From: "N=C3=ADcolas F. R. A. Prado" Introduce a post-blend color pipeline with the same colorop blocks as the pre-blend color pipeline. Signed-off-by: N=C3=ADcolas F. R. A. Prado Co-developed-by: Ariel D'Alessandro Signed-off-by: Ariel D'Alessandro --- drivers/gpu/drm/vkms/tests/vkms_config_test.c | 70 ++++++++++------- drivers/gpu/drm/vkms/vkms_colorop.c | 103 ++++++++++++++++++++++= ++++ drivers/gpu/drm/vkms/vkms_composer.c | 5 +- drivers/gpu/drm/vkms/vkms_config.c | 5 +- drivers/gpu/drm/vkms/vkms_config.h | 29 +++++++- drivers/gpu/drm/vkms/vkms_crtc.c | 6 +- drivers/gpu/drm/vkms/vkms_drv.c | 7 +- drivers/gpu/drm/vkms/vkms_drv.h | 6 +- drivers/gpu/drm/vkms/vkms_output.c | 3 +- 9 files changed, 202 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/vkms/tests/vkms_config_test.c b/drivers/gpu/dr= m/vkms/tests/vkms_config_test.c index 1e4ea1863420f..ec1d84ae508ad 100644 --- a/drivers/gpu/drm/vkms/tests/vkms_config_test.c +++ b/drivers/gpu/drm/vkms/tests/vkms_config_test.c @@ -84,6 +84,7 @@ struct default_config_case { bool enable_writeback; bool enable_overlay; bool enable_plane_pipeline; + bool enable_crtc_pipeline; }; =20 static void vkms_config_test_empty_config(struct kunit *test) @@ -109,22 +110,38 @@ static void vkms_config_test_empty_config(struct kuni= t *test) } =20 static struct default_config_case default_config_cases[] =3D { - { false, false, false, false }, - { true, false, false, false }, - { true, true, false, false }, - { true, false, true, false }, - { false, true, false, false }, - { false, true, true, false }, - { false, false, true, false }, - { true, true, true, false }, - { false, false, false, true }, - { true, false, false, true }, - { true, true, false, true }, - { true, false, true, true }, - { false, true, false, true }, - { false, true, true, true }, - { false, false, true, true }, - { true, true, true, true }, + { false, false, false, false, false }, + { true, false, false, false, false }, + { true, true, false, false, false }, + { true, false, true, false, false }, + { false, true, false, false, false }, + { false, true, true, false, false }, + { false, false, true, false, false }, + { true, true, true, false, false }, + { false, false, false, true, false }, + { true, false, false, true, false }, + { true, true, false, true, false }, + { true, false, true, true, false }, + { false, true, false, true, false }, + { false, true, true, true, false }, + { false, false, true, true, false }, + { true, true, true, true, false }, + { false, false, false, false, true }, + { true, false, false, false, true }, + { true, true, false, false, true }, + { true, false, true, false, true }, + { false, true, false, false, true }, + { false, true, true, false, true }, + { false, false, true, false, true }, + { true, true, true, false, true }, + { false, false, false, true, true }, + { true, false, false, true, true }, + { true, true, false, true, true }, + { true, false, true, true, true }, + { false, true, false, true, true }, + { false, true, true, true, true }, + { false, false, true, true, true }, + { true, true, true, true, true }, }; =20 KUNIT_ARRAY_PARAM(default_config, default_config_cases, NULL); @@ -142,7 +159,8 @@ static void vkms_config_test_default_config(struct kuni= t *test) config =3D vkms_config_default_create(params->enable_cursor, params->enable_writeback, params->enable_overlay, - params->enable_plane_pipeline); + params->enable_plane_pipeline, + params->enable_crtc_pipeline); KUNIT_ASSERT_NOT_ERR_OR_NULL(test, config); =20 /* Planes */ @@ -174,6 +192,8 @@ static void vkms_config_test_default_config(struct kuni= t *test) crtc_cfg =3D get_first_crtc(config); KUNIT_EXPECT_EQ(test, vkms_config_crtc_get_writeback(crtc_cfg), params->enable_writeback); + KUNIT_EXPECT_EQ(test, vkms_config_crtc_get_default_pipeline(crtc_cfg), + params->enable_crtc_pipeline); =20 vkms_config_for_each_plane(config, plane_cfg) { struct vkms_config_crtc *possible_crtc; @@ -381,7 +401,7 @@ static void vkms_config_test_invalid_plane_number(struc= t kunit *test) struct vkms_config_plane *plane_cfg; int n; =20 - config =3D vkms_config_default_create(false, false, false, false); + config =3D vkms_config_default_create(false, false, false, false, false); KUNIT_ASSERT_NOT_ERR_OR_NULL(test, config); =20 /* Invalid: No planes */ @@ -406,7 +426,7 @@ static void vkms_config_test_valid_plane_type(struct ku= nit *test) struct vkms_config_encoder *encoder_cfg; int err; =20 - config =3D vkms_config_default_create(false, false, false, false); + config =3D vkms_config_default_create(false, false, false, false, false); KUNIT_ASSERT_NOT_ERR_OR_NULL(test, config); =20 plane_cfg =3D get_first_plane(config); @@ -487,7 +507,7 @@ static void vkms_config_test_valid_plane_possible_crtcs= (struct kunit *test) struct vkms_config_plane *plane_cfg; struct vkms_config_crtc *crtc_cfg; =20 - config =3D vkms_config_default_create(false, false, false, false); + config =3D vkms_config_default_create(false, false, false, false, false); KUNIT_ASSERT_NOT_ERR_OR_NULL(test, config); =20 plane_cfg =3D get_first_plane(config); @@ -506,7 +526,7 @@ static void vkms_config_test_invalid_crtc_number(struct= kunit *test) struct vkms_config_crtc *crtc_cfg; int n; =20 - config =3D vkms_config_default_create(false, false, false, false); + config =3D vkms_config_default_create(false, false, false, false, false); KUNIT_ASSERT_NOT_ERR_OR_NULL(test, config); =20 /* Invalid: No CRTCs */ @@ -529,7 +549,7 @@ static void vkms_config_test_invalid_encoder_number(str= uct kunit *test) struct vkms_config_encoder *encoder_cfg; int n; =20 - config =3D vkms_config_default_create(false, false, false, false); + config =3D vkms_config_default_create(false, false, false, false, false); KUNIT_ASSERT_NOT_ERR_OR_NULL(test, config); =20 /* Invalid: No encoders */ @@ -554,7 +574,7 @@ static void vkms_config_test_valid_encoder_possible_crt= cs(struct kunit *test) struct vkms_config_encoder *encoder_cfg; int err; =20 - config =3D vkms_config_default_create(false, false, false, false); + config =3D vkms_config_default_create(false, false, false, false, false); KUNIT_ASSERT_NOT_ERR_OR_NULL(test, config); =20 crtc_cfg1 =3D get_first_crtc(config); @@ -600,7 +620,7 @@ static void vkms_config_test_invalid_connector_number(s= truct kunit *test) struct vkms_config_connector *connector_cfg; int n; =20 - config =3D vkms_config_default_create(false, false, false, false); + config =3D vkms_config_default_create(false, false, false, false, false); KUNIT_ASSERT_NOT_ERR_OR_NULL(test, config); =20 /* Invalid: No connectors */ @@ -623,7 +643,7 @@ static void vkms_config_test_valid_connector_possible_e= ncoders(struct kunit *tes struct vkms_config_encoder *encoder_cfg; struct vkms_config_connector *connector_cfg; =20 - config =3D vkms_config_default_create(false, false, false, false); + config =3D vkms_config_default_create(false, false, false, false, false); KUNIT_ASSERT_NOT_ERR_OR_NULL(test, config); =20 encoder_cfg =3D get_first_encoder(config); diff --git a/drivers/gpu/drm/vkms/vkms_colorop.c b/drivers/gpu/drm/vkms/vkm= s_colorop.c index dd6120434690e..6c4a6cb186564 100644 --- a/drivers/gpu/drm/vkms/vkms_colorop.c +++ b/drivers/gpu/drm/vkms/vkms_colorop.c @@ -102,6 +102,91 @@ static int vkms_initialize_plane_color_pipeline(struct= drm_plane *plane, return ret; } =20 +static int vkms_initialize_crtc_color_pipeline(struct drm_crtc *crtc, + struct drm_prop_enum_list *list) +{ + struct drm_colorop *ops[MAX_COLOR_PIPELINE_OPS]; + struct drm_device *dev =3D crtc->dev; + int ret; + int i =3D 0, j =3D 0; + + memset(ops, 0, sizeof(ops)); + + /* 1st op: 1d curve */ + ops[i] =3D kzalloc(sizeof(*ops[i]), GFP_KERNEL); + if (!ops[i]) { + ret =3D -ENOMEM; + goto cleanup; + } + + ret =3D drm_crtc_colorop_curve_1d_init(dev, ops[i], crtc, supported_tfs, + DRM_COLOROP_FLAG_ALLOW_BYPASS); + if (ret) + goto err_colorop_init; + + list->type =3D ops[i]->base.id; + list->name =3D kasprintf(GFP_KERNEL, "Color Pipeline %d", ops[i]->base.id= ); + + i++; + + /* 2nd op: 3x4 matrix */ + ops[i] =3D kzalloc(sizeof(*ops[i]), GFP_KERNEL); + if (!ops[i]) { + ret =3D -ENOMEM; + goto cleanup; + } + + ret =3D drm_crtc_colorop_ctm_3x4_init(dev, ops[i], crtc, DRM_COLOROP_FLAG= _ALLOW_BYPASS); + if (ret) + goto err_colorop_init; + + drm_colorop_set_next_property(ops[i - 1], ops[i]); + + i++; + + /* 3rd op: 3x4 matrix */ + ops[i] =3D kzalloc(sizeof(*ops[i]), GFP_KERNEL); + if (!ops[i]) { + ret =3D -ENOMEM; + goto cleanup; + } + + ret =3D drm_crtc_colorop_ctm_3x4_init(dev, ops[i], crtc, DRM_COLOROP_FLAG= _ALLOW_BYPASS); + if (ret) + goto err_colorop_init; + + drm_colorop_set_next_property(ops[i - 1], ops[i]); + + i++; + + /* 4th op: 1d curve */ + ops[i] =3D kzalloc(sizeof(*ops[i]), GFP_KERNEL); + if (!ops[i]) { + ret =3D -ENOMEM; + goto cleanup; + } + + ret =3D drm_crtc_colorop_curve_1d_init(dev, ops[i], crtc, supported_tfs, + DRM_COLOROP_FLAG_ALLOW_BYPASS); + if (ret) + goto err_colorop_init; + + drm_colorop_set_next_property(ops[i - 1], ops[i]); + + return 0; + +err_colorop_init: + kfree(ops[i]); + +cleanup: + for (j =3D 0; j < i; j++) { + drm_colorop_cleanup(ops[j]); + kfree(ops[j]); + } + + return ret; +} + int vkms_initialize_plane_colorops(struct drm_plane *plane) { struct drm_prop_enum_list pipeline; @@ -119,3 +204,21 @@ int vkms_initialize_plane_colorops(struct drm_plane *p= lane) =20 return 0; } + +int vkms_initialize_crtc_colorops(struct drm_crtc *crtc) +{ + struct drm_prop_enum_list pipeline; + int ret; + + /* Add color pipeline */ + ret =3D vkms_initialize_crtc_color_pipeline(crtc, &pipeline); + if (ret) + return ret; + + /* Create COLOR_PIPELINE property and attach */ + ret =3D drm_crtc_create_color_pipeline_property(crtc, &pipeline, 1); + if (ret) + return ret; + + return 0; +} diff --git a/drivers/gpu/drm/vkms/vkms_composer.c b/drivers/gpu/drm/vkms/vk= ms_composer.c index d4f87a2aa3359..621f008b165a6 100644 --- a/drivers/gpu/drm/vkms/vkms_composer.c +++ b/drivers/gpu/drm/vkms/vkms_composer.c @@ -495,7 +495,10 @@ static void blend(struct vkms_writeback_job *wb, blend_line(plane[i], y, crtc_x_limit, stage_buffer, output_buffer); } =20 - apply_lut(crtc_state, output_buffer); + if (crtc_state->base.color_pipeline_enabled) + color_transform(crtc_state->base.color_pipeline, output_buffer); + else + apply_lut(crtc_state, output_buffer); =20 *crc32 =3D crc32_le(*crc32, (void *)output_buffer->pixels, row_size); =20 diff --git a/drivers/gpu/drm/vkms/vkms_config.c b/drivers/gpu/drm/vkms/vkms= _config.c index 8788df9edb7ca..a65c3638eff4d 100644 --- a/drivers/gpu/drm/vkms/vkms_config.c +++ b/drivers/gpu/drm/vkms/vkms_config.c @@ -34,7 +34,8 @@ EXPORT_SYMBOL_IF_KUNIT(vkms_config_create); struct vkms_config *vkms_config_default_create(bool enable_cursor, bool enable_writeback, bool enable_overlay, - bool enable_plane_pipeline) + bool enable_plane_pipeline, + bool enable_crtc_pipeline) { struct vkms_config *config; struct vkms_config_plane *plane_cfg; @@ -56,6 +57,7 @@ struct vkms_config *vkms_config_default_create(bool enabl= e_cursor, if (IS_ERR(crtc_cfg)) goto err_alloc; vkms_config_crtc_set_writeback(crtc_cfg, enable_writeback); + vkms_config_crtc_set_default_pipeline(crtc_cfg, enable_crtc_pipeline); =20 if (vkms_config_plane_attach_crtc(plane_cfg, crtc_cfg)) goto err_alloc; @@ -454,6 +456,7 @@ struct vkms_config_crtc *vkms_config_create_crtc(struct= vkms_config *config) =20 crtc_cfg->config =3D config; vkms_config_crtc_set_writeback(crtc_cfg, false); + vkms_config_crtc_set_default_pipeline(crtc_cfg, false); =20 list_add_tail(&crtc_cfg->link, &config->crtcs); =20 diff --git a/drivers/gpu/drm/vkms/vkms_config.h b/drivers/gpu/drm/vkms/vkms= _config.h index 8f7f286a4bdd7..e12e4065f01f0 100644 --- a/drivers/gpu/drm/vkms/vkms_config.h +++ b/drivers/gpu/drm/vkms/vkms_config.h @@ -61,6 +61,7 @@ struct vkms_config_plane { * @link: Link to the others CRTCs in vkms_config * @config: The vkms_config this CRTC belongs to * @writeback: If true, a writeback buffer can be attached to the CRTC + * @default_pipeline: If true, CRTC will be created with the default pipel= ine. * @crtc: Internal usage. This pointer should never be considered as valid. * It can be used to store a temporary reference to a VKMS CRTC dur= ing * device creation. This pointer is not managed by the configuratio= n and @@ -71,6 +72,7 @@ struct vkms_config_crtc { struct vkms_config *config; =20 bool writeback; + bool default_pipeline; =20 /* Internal usage */ struct vkms_output *crtc; @@ -205,7 +207,8 @@ struct vkms_config *vkms_config_create(const char *dev_= name); struct vkms_config *vkms_config_default_create(bool enable_cursor, bool enable_writeback, bool enable_overlay, - bool enable_plane_pipeline); + bool enable_plane_pipeline, + bool enable_crtc_pipeline); =20 /** * vkms_config_destroy() - Free a VKMS configuration @@ -314,6 +317,30 @@ vkms_config_plane_set_default_pipeline(struct vkms_con= fig_plane *plane_cfg, plane_cfg->default_pipeline =3D default_pipeline; } =20 +/** + * vkms_config_crtc_get_default_pipeline() - Return if the CRTC will + * be created with the default pipeline + * @crtc_cfg: CRTC to get the information from + */ +static inline bool +vkms_config_crtc_get_default_pipeline(struct vkms_config_crtc *crtc_cfg) +{ + return crtc_cfg->default_pipeline; +} + +/** + * vkms_config_crtc_set_default_pipeline() - Set if the CRTC will + * be created with the default pipeline + * @crtc_cfg: CRTC to configure the pipeline + * @default_pipeline: New default pipeline value + */ +static inline void +vkms_config_crtc_set_default_pipeline(struct vkms_config_crtc *crtc_cfg, + bool default_pipeline) +{ + crtc_cfg->default_pipeline =3D default_pipeline; +} + /** * vkms_config_plane_attach_crtc - Attach a plane to a CRTC * @plane_cfg: Plane to attach diff --git a/drivers/gpu/drm/vkms/vkms_crtc.c b/drivers/gpu/drm/vkms/vkms_c= rtc.c index 9a7db1d510222..60c372c0ce2d8 100644 --- a/drivers/gpu/drm/vkms/vkms_crtc.c +++ b/drivers/gpu/drm/vkms/vkms_crtc.c @@ -10,6 +10,7 @@ #include #include =20 +#include "vkms_config.h" #include "vkms_drv.h" =20 static bool vkms_crtc_handle_vblank_timeout(struct drm_crtc *crtc) @@ -202,7 +203,7 @@ static const struct drm_crtc_helper_funcs vkms_crtc_hel= per_funcs =3D { }; =20 struct vkms_output *vkms_crtc_init(struct drm_device *dev, struct drm_plan= e *primary, - struct drm_plane *cursor) + struct drm_plane *cursor, struct vkms_config_crtc *crtc_cfg) { struct vkms_output *vkms_out; struct drm_crtc *crtc; @@ -228,6 +229,9 @@ struct vkms_output *vkms_crtc_init(struct drm_device *d= ev, struct drm_plane *pri =20 drm_crtc_enable_color_mgmt(crtc, 0, false, VKMS_LUT_SIZE); =20 + if (vkms_config_crtc_get_default_pipeline(crtc_cfg)) + vkms_initialize_crtc_colorops(crtc); + spin_lock_init(&vkms_out->lock); spin_lock_init(&vkms_out->composer_lock); =20 diff --git a/drivers/gpu/drm/vkms/vkms_drv.c b/drivers/gpu/drm/vkms/vkms_dr= v.c index dd1402f437736..39195540fe2b1 100644 --- a/drivers/gpu/drm/vkms/vkms_drv.c +++ b/drivers/gpu/drm/vkms/vkms_drv.c @@ -55,6 +55,10 @@ static bool enable_plane_pipeline; module_param_named(enable_plane_pipeline, enable_plane_pipeline, bool, 044= 4); MODULE_PARM_DESC(enable_plane_pipeline, "Enable/Disable plane pipeline sup= port"); =20 +static bool enable_crtc_pipeline; +module_param_named(enable_crtc_pipeline, enable_crtc_pipeline, bool, 0444); +MODULE_PARM_DESC(enable_crtc_pipeline, "Enable/Disable CRTC pipeline suppo= rt"); + static bool create_default_dev =3D true; module_param_named(create_default_dev, create_default_dev, bool, 0444); MODULE_PARM_DESC(create_default_dev, "Create or not the default VKMS devic= e"); @@ -232,7 +236,8 @@ static int __init vkms_init(void) return 0; =20 config =3D vkms_config_default_create(enable_cursor, enable_writeback, - enable_overlay, enable_plane_pipeline); + enable_overlay, enable_plane_pipeline, + enable_crtc_pipeline); if (IS_ERR(config)) return PTR_ERR(config); =20 diff --git a/drivers/gpu/drm/vkms/vkms_drv.h b/drivers/gpu/drm/vkms/vkms_dr= v.h index bdeb52623f4d6..1688c885f2285 100644 --- a/drivers/gpu/drm/vkms/vkms_drv.h +++ b/drivers/gpu/drm/vkms/vkms_drv.h @@ -229,6 +229,7 @@ struct vkms_output { }; =20 struct vkms_config; +struct vkms_config_crtc; struct vkms_config_plane; =20 /** @@ -287,10 +288,12 @@ void vkms_destroy(struct vkms_config *config); * @crtc: uninitialized CRTC device * @primary: primary plane to attach to the CRTC * @cursor: plane to attach to the CRTC + * @crtc_cfg: CRTC configuration */ struct vkms_output *vkms_crtc_init(struct drm_device *dev, struct drm_plane *primary, - struct drm_plane *cursor); + struct drm_plane *cursor, + struct vkms_config_crtc *crtc_cfg); =20 /** * vkms_output_init() - Initialize all sub-components needed for a VKMS de= vice. @@ -325,5 +328,6 @@ int vkms_enable_writeback_connector(struct vkms_device = *vkmsdev, struct vkms_out =20 /* Colorops */ int vkms_initialize_plane_colorops(struct drm_plane *plane); +int vkms_initialize_crtc_colorops(struct drm_crtc *crtc); =20 #endif /* _VKMS_DRV_H_ */ diff --git a/drivers/gpu/drm/vkms/vkms_output.c b/drivers/gpu/drm/vkms/vkms= _output.c index 86ce07a617f52..a0856ba90ac24 100644 --- a/drivers/gpu/drm/vkms/vkms_output.c +++ b/drivers/gpu/drm/vkms/vkms_output.c @@ -34,7 +34,8 @@ int vkms_output_init(struct vkms_device *vkmsdev) cursor =3D vkms_config_crtc_cursor_plane(vkmsdev->config, crtc_cfg); =20 crtc_cfg->crtc =3D vkms_crtc_init(dev, &primary->plane->base, - cursor ? &cursor->plane->base : NULL); + cursor ? &cursor->plane->base : NULL, + crtc_cfg); if (IS_ERR(crtc_cfg->crtc)) { DRM_ERROR("Failed to allocate CRTC\n"); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-post-blend-color-pipeline-v3-21-7d969f9a37a0@collabora.com> References: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> In-Reply-To: <20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a37a0@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Louis Chauvet , Haneen Mohammed , Melissa Wen Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Ariel D'Alessandro X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766512902; l=1111; i=ariel.dalessandro@collabora.com; s=20251223; h=from:subject:message-id; bh=gQFC766tccP0PdIOKUEQiK11Tirgc3AWqnqe3NzY2Vo=; b=jhCoAhoS0Grzt6YiW0jqVUY3CjSqOVgbkX+1ILgEPeIuZv3KL8AgIQhDVXL4s+BwVJfx/rX58 WfyawBOXlioCmhneTj7YU6dIkWfgqUUZRpgwO7dSKkeV4Jxi++RNdL0 X-Developer-Key: i=ariel.dalessandro@collabora.com; a=ed25519; pk=QZRL9EsSBV3/FhDHi9L/7ZTz2dwa7iyqgl+y1UYaQXQ= X-ZohoMailClient: External From: "N=C3=ADcolas F. R. A. Prado" Now that the driver implements CRTC (post-blend) color pipelines, set the driver cap so they can be used from userspace. Signed-off-by: N=C3=ADcolas F. R. A. Prado Co-developed-by: Ariel D'Alessandro Signed-off-by: Ariel D'Alessandro Reviewed-by: Louis Chauvet --- drivers/gpu/drm/vkms/vkms_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vkms/vkms_drv.c b/drivers/gpu/drm/vkms/vkms_dr= v.c index 39195540fe2b1..62cd36c805e45 100644 --- a/drivers/gpu/drm/vkms/vkms_drv.c +++ b/drivers/gpu/drm/vkms/vkms_drv.c @@ -94,7 +94,8 @@ static void vkms_atomic_commit_tail(struct drm_atomic_sta= te *old_state) } =20 static const struct drm_driver vkms_driver =3D { - .driver_features =3D DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_GEM, + .driver_features =3D DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_GEM | + DRIVER_CRTC_COLOR_PIPELINE, .fops =3D &vkms_driver_fops, DRM_GEM_SHMEM_DRIVER_OPS, DRM_FBDEV_SHMEM_DRIVER_OPS, --=20 2.51.0