From nobody Tue Feb 10 05:17:00 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08A8334C80D for ; Tue, 23 Dec 2025 19:47:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766519248; cv=none; b=Mwf6mwrHgE62CvbHhVJtpqajJCDa0ifRkXM3pbflfA1dUEISQcLGqvqUnclbEefd47hDyx1REkYJM/35c7Ms96xql77UjZ0dIxHWQ2iEUJ0ZTJI2c29ATmu0fZeuA/uZAwzFh8Rh2sdBDv/1fiRbLeGVzuOgzYjIUTk4O3ZqjHg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766519248; c=relaxed/simple; bh=vD870d938nwYIyegPWMdbDmlJ2S2wI475Vgc02Kli+Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hhOFyiD1Ov+jkseLKK0G6qG2wHDp2yTZEUcZCLCgKmy2BR9zIIsXddxS6Yd7eAqkf5cuOo9vQj2prLejMW7K2TIYvxnVfygHkxaP9FX91/7q3skHBImO7bPvQoRkOMdAVJNLkouLEPWOQU6rWsHGhFy/eKNa9ABFNeu39FC6eWY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=aLtCQkC3; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="aLtCQkC3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1766519244; bh=vD870d938nwYIyegPWMdbDmlJ2S2wI475Vgc02Kli+Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=aLtCQkC3a5T2UWir+7wR8cn3YzmtoBembHI8xZ0fPYB2FyK5PSgwhT/3jj5pzRtNB MJyd0hRnE2bdzhOclDxEoamqa9KyiGSjMXWp6dqAw9TItMQpFiBVyuE8B7oXisjwdE pa7Nk4v6epgb4wuvDWeCuT2ISN1igstXhvUZsTYk89n/W3G9+LxMa3P+p9sxdIrAb1 VeqOqHJRx2QapMHfCSqjTMKdflhOL3jCewsd5BaPS4IgHPqcXaskHbLcnN/Pv4X5sJ iYyZPxMRAtWWnzxMSVbVB9/UXEaBSajuuyIysyNtNJVTaRXQmhz2DPbphsqnBXlU9/ CTnTcuF5X/WNw== Received: from [127.0.1.1] (unknown [IPv6:2804:1b1:f803:74:81c8:6a7a:6e11:8f81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id 8E14F17E35DC; Tue, 23 Dec 2025 20:47:18 +0100 (CET) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Tue, 23 Dec 2025 16:44:51 -0300 Subject: [PATCH 10/11] drm/mediatek: ovl: Enable support for R2R Color Space Conversion Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-ovl-pre-blend-colorops-v1-10-0cb99bd0ab33@collabora.com> References: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> In-Reply-To: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, daniels@collabora.com, ariel.dalessandro@collabora.com, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.3 The OVL hardware allows applying a 3x3 matrix transformation for each layer through the 'RGB to RGB Color Space Conversion' (R2R CSC) setting. Implement support for it and expose it as a colorop through the DRM plane color pipeline uAPI. Signed-off-by: N=C3=ADcolas F. R. A. Prado --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 55 +++++++++++++++++++++++++++++= +++- 1 file changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index a70092c792a9..c8a2b1b13035 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include #include @@ -52,6 +53,7 @@ #define OVL_CON_CLRFMT_10_BIT (1) #define DISP_REG_OVL_WCG_CFG1 0x2d8 #define IGAMMA_EN(layer) BIT(0 + 4 * (layer)) +#define CSC_EN(layer) BIT(1 + 4 * (layer)) #define GAMMA_EN(layer) BIT(2 + 4 * (layer)) #define DISP_REG_OVL_WCG_CFG2 0x2dc #define IGAMMA_MASK(layer) GENMASK((layer) * 4 + 1, (layer) * 4) @@ -62,6 +64,7 @@ #define GAMMA_BT709 1 #define GAMMA_BT2020 2 #define GAMMA_HLG 3 +#define DISP_REG_OVL_R2R_PARA(layer) (0x500 + (layer) * 0x40) #define DISP_REG_OVL_ADDR_MT8173 0x0f40 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0= x04) @@ -579,11 +582,44 @@ static void mtk_ovl_apply_igamma(struct mtk_disp_ovl = *ovl, unsigned int idx, IGAMMA_EN(idx)); } =20 +static void mtk_ovl_write_r2r_para(struct mtk_disp_ovl *ovl, unsigned int = idx, + struct drm_color_ctm *ctm, + struct cmdq_pkt *cmdq_pkt) +{ + unsigned int i; + u64 val; + + for (i =3D 0; i < ARRAY_SIZE(ctm->matrix); i++) { + val =3D drm_color_ctm_s31_32_to_qm_n(ctm->matrix[i], 5, 18); + mtk_ddp_write(cmdq_pkt, val, &ovl->cmdq_reg, ovl->regs, + DISP_REG_OVL_R2R_PARA(idx) + i * 4); + } +} + +static void mtk_ovl_apply_r2r_csc(struct mtk_disp_ovl *ovl, unsigned int i= dx, + struct drm_colorop *colorop, + struct cmdq_pkt *cmdq_pkt) +{ + struct drm_color_ctm *ctm; + + if (colorop->state->data && colorop->state->data->data) { + ctm =3D (struct drm_color_ctm *)colorop->state->data->data; + mtk_ovl_write_r2r_para(ovl, idx, ctm, cmdq_pkt); + } + + mtk_ddp_write_mask(cmdq_pkt, colorop->state->bypass ? 0 : CSC_EN(idx), + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_WCG_CFG1, + CSC_EN(idx)); +} + static void mtk_ovl_apply_colorop(struct mtk_disp_ovl *ovl, unsigned int i= dx, struct drm_colorop *colorop, struct cmdq_pkt *cmdq_pkt) { switch (colorop->type) { + case DRM_COLOROP_CTM_3X3: + mtk_ovl_apply_r2r_csc(ovl, idx, colorop, cmdq_pkt); + break; case DRM_COLOROP_1D_CURVE: /* gamma is the last colorop in pipeline */ if (!colorop->next) @@ -602,7 +638,7 @@ static void mtk_ovl_disable_colorops(struct mtk_disp_ov= l *ovl, unsigned int idx, { mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_WCG_CFG1, - IGAMMA_EN(idx) | GAMMA_EN(idx)); + IGAMMA_EN(idx) | CSC_EN(idx) | GAMMA_EN(idx)); =20 /* igamma curve needs to be set to default when igamma is disabled */ mtk_ddp_write_mask(cmdq_pkt, IGAMMA_SCRGB, &ovl->cmdq_reg, ovl->regs, @@ -771,6 +807,23 @@ mtk_ovl_initialize_plane_color_pipeline(struct drm_pla= ne *plane, =20 i++; =20 + /* 2nd op: OVL's R2R Color Space Conversion */ + ops[i] =3D kzalloc(sizeof(*ops[i]), GFP_KERNEL); + if (!ops[i]) { + ret =3D -ENOMEM; + goto err_alloc; + } + + ret =3D drm_plane_colorop_ctm_3x3_init(dev, ops[i], plane, + &mtk_ovl_colorop_funcs, + DRM_COLOROP_FLAG_ALLOW_BYPASS); + if (ret) + goto err_colorop_init; + + drm_colorop_set_next_property(ops[i - 1], ops[i]); + + i++; + /* 3rd op: OVL's Gamma */ ops[i] =3D kzalloc(sizeof(*ops[i]), GFP_KERNEL); if (!ops[i]) { --=20 2.51.0