From nobody Mon Feb 9 06:30:58 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FDFB2E0934 for ; Tue, 23 Dec 2025 19:46:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766519195; cv=none; b=HuXwEhU4O7nJkkzcnd2UvyFQ3VKlXvn7qyaCfU/aa7f9/WneqLtgTb/qCfj2HPaXJTUZPZ0VsMf7sQm3ngYrfhaXWq9cYUm+xp9RMbbNUt2b4kyeLNSTf71vN8K/gyRbxUXw83vgU8hlbYWr8uaaWbEMJKez1TGCo5PAb1BnuA0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766519195; c=relaxed/simple; bh=AspixI/Zehlvp8aaMQOtqUnGyuNV8eKlnuQrhHE2EB8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Hg2CxOCXodpBk2tROxhKdS6uhwc1sSDnYHugGxbf6xYr3wxhPGL/ch+kbEiTV/Y1dDiwgBpliouqO/1oQaCEtUkR7V7C0ovcDPrjtR0Xtdse2/Gi+M+TDKv9t8u09IyMvqXDy6NzWC1cYibja2u9qYX4+JAO8+M/U04yQLEA0fM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=keKOzdTC; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="keKOzdTC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1766519191; bh=AspixI/Zehlvp8aaMQOtqUnGyuNV8eKlnuQrhHE2EB8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=keKOzdTCO3rnHak+ZHukTtXHNIjGooF9SNvH+vphysxH+cFAIRRgGFPDj2fMJ02xO nLxB3CI7hhElaV6KQmkDwcxmBr+o+/eGRW724DXvU6SQfYOkhcy8Y9yq1u3WKy+ZBH tfzE5zUq031jwhz3x6c5YvfeuXIBwXO4Xj+R6kFY6PrartjuHm73ZFQsk166iXPPbk Q2GUoZGRXTS2w5E35HokGmxxoZQX7ezLmmST/f66P5pKE/9U2aO/c/12+anZ2TozmK cLXmhJJivqqONZc4h48QVwd4oYk62pLwJyaZyapqUqIzZeAkySH/20728xc0yntoyf lCCIjXdDBaHcQ== Received: from [127.0.1.1] (unknown [IPv6:2804:1b1:f803:74:81c8:6a7a:6e11:8f81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id A304117E10DC; Tue, 23 Dec 2025 20:46:26 +0100 (CET) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Tue, 23 Dec 2025 16:44:42 -0300 Subject: [PATCH 01/11] drm/mediatek: Introduce DDP plane_colorops_init() hook Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-ovl-pre-blend-colorops-v1-1-0cb99bd0ab33@collabora.com> References: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> In-Reply-To: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, daniels@collabora.com, ariel.dalessandro@collabora.com, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.3 Introduce a plane_colorops_init() hook to allow DDP components to define how to initialize the color pipeline on their planes. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index 99bf1e1015da..3a7393b7f4c9 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -13,6 +13,7 @@ #include =20 #include +#include =20 struct device; struct device_node; @@ -86,6 +87,7 @@ struct mtk_ddp_comp_funcs { const u32 *(*get_formats)(struct device *dev); size_t (*get_num_formats)(struct device *dev); bool (*is_afbc_supported)(struct device *dev); + int (*plane_colorops_init)(struct device *dev, struct drm_plane *plane); void (*connect)(struct device *dev, struct device *mmsys_dev, unsigned in= t next); void (*disconnect)(struct device *dev, struct device *mmsys_dev, unsigned= int next); void (*add)(struct device *dev, struct mtk_mutex *mutex); --=20 2.51.0 From nobody Mon Feb 9 06:30:58 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEC00296BD2 for ; Tue, 23 Dec 2025 19:46:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766519200; cv=none; b=UJFucwkxEVJ8+sLWvxNkgdJXR2jpcLObdX2WGRz3mHbSqEI9Xk1joiSAlZe5GlIVjtNqfP/O0meJIaREyALwAbKM0peEsZY3xcunyikwXSp7gkhEQpxTy8qEdGIGJx/f/3K4ZPvBuOEKnNSuCV+uOygL6BFb0bYpRdiIinixDDs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766519200; c=relaxed/simple; bh=8FoqfaoY+0Hw91SrzejtYpeqb9eQRxsYLDoEUKDQmRg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ldttuD/t9ItuTnR8H5EHsPCPru0iXGYe/sqJWYhdJAj5gy6y/WSHOz1VxjojWahYoef+wnlhEcvmBCZ4RPJ2mGaPwPcfcFZ83GRAuunfBVe8yg+1Ip06ByP5SVY9/5+9FkM111qww5W1B5uDWRPg7hi0N8zij+PO1srcw/KZ39Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=CKwn8j98; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="CKwn8j98" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1766519197; bh=8FoqfaoY+0Hw91SrzejtYpeqb9eQRxsYLDoEUKDQmRg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=CKwn8j98/eXjlM0Ifa8ou8K0lQ+DeRRMAJNQQnj6je8r9dTbq0u97I7W3mxqp3y+M zVK7oMG2LcmwDIKs/q3xadWc5f2FU53m5eilfZgdIQaHmKMgZdiYSPtuxoF2E2oBjG nbSGwJcsWlow9I/ycaxGanCQSOPMTWykXxEK/OvKr+74ZM5attCvrtm0sof8SiHCF/ XIU0PeyjelILXKuTDxx9PPcl2H/7PZBqZ/rOJ3/5z1pBVmMHBtWBf1Dy1QGZ8Ujgbc N3osY6Tu5GlncJIENBAt736XKJyr6gdMTz355lSfHI0E9OoYaYGpSGK0rGfNmrZjMI PE11IV+cbA3+w== Received: from [127.0.1.1] (unknown [IPv6:2804:1b1:f803:74:81c8:6a7a:6e11:8f81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id 4AC1E17E12EB; Tue, 23 Dec 2025 20:46:32 +0100 (CET) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Tue, 23 Dec 2025 16:44:43 -0300 Subject: [PATCH 02/11] drm/mediatek: Initialize colorops when creating plane Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-ovl-pre-blend-colorops-v1-2-0cb99bd0ab33@collabora.com> References: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> In-Reply-To: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, daniels@collabora.com, ariel.dalessandro@collabora.com, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.3 During initialization of a plane, if the DDP component supplying it defines a plane_colorops_init() hook, call it to initialize the color pipeline on the plane. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_crtc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek= /mtk_crtc.c index 22f255c3ddd3..f7db235d986f 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -985,8 +985,10 @@ static int mtk_crtc_init_comp_planes(struct drm_device= *drm_dev, int i, ret; =20 for (i =3D 0; i < num_planes; i++) { + struct drm_plane *plane =3D &mtk_crtc->planes[mtk_crtc->layer_nr]; + ret =3D mtk_plane_init(drm_dev, - &mtk_crtc->planes[mtk_crtc->layer_nr], + plane, BIT(pipe), mtk_crtc_plane_type(mtk_crtc->layer_nr, num_planes), mtk_ddp_comp_supported_rotations(comp), @@ -997,6 +999,12 @@ static int mtk_crtc_init_comp_planes(struct drm_device= *drm_dev, if (ret) return ret; =20 + if (comp->funcs && comp->funcs->plane_colorops_init) { + ret =3D comp->funcs->plane_colorops_init(comp->dev, plane); + if (ret) + return ret; + } + mtk_crtc->layer_nr++; } return 0; --=20 2.51.0 From nobody Mon Feb 9 06:30:58 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4522C34888A for ; Tue, 23 Dec 2025 19:46:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766519207; cv=none; b=S795SxRiAnS8Y1wFUmkyrDQBvAbRWe+rvZr13CimNnVOjsFyF/e6JMymc9bar37NzV+lYwGaiguN2ZAFwwH+I64VoZicgjCv5MPLiSBeSadaly/0zjXAatdLazOK46mWX2mSoGpXIqQjEnCSLFQdnZKRFtdSDhGUd2Ljjv3KvzA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766519207; c=relaxed/simple; bh=wh/khd0MG4TmlC1+SwQHtrkPFJXfgwSIZjK19Qae4No=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ci9lZ+9vOJLt/a2JBWnycC5MnIF2Km6jUNvSJRekm2oXHA95eiQ+rfuu+4GjYh7JIjTsbHwIJqPQqOZVEjMR2aTWa1DwemoUym/dNNDYIZZfTvT318uMSK30CCkmJ55llHsVeN/dYW7CPGFdzSScU4+o2G5uXl/zLk/jc90hPsA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=It0HZ5oO; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="It0HZ5oO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1766519203; bh=wh/khd0MG4TmlC1+SwQHtrkPFJXfgwSIZjK19Qae4No=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=It0HZ5oOwjvJfgmJntjU2VjEHR3wpqdCxoGft86uIydBrC/H+6PC18BP8ONEbcx8j e/noOhNfKee0AVTSJ/kbf9FiUPSFN0gpGdG0TwjnWt205JUmAmirAAzcKa4SQ9BCS4 q7i9khvC1gtFej2twvf8dAShQSfKF2GBcVXVfTUjFE1THCLsrSK/oJn3lFXcf1P72F NoIERAaxk6kRUnIJaAcbM+TDLYajjHfN/O+pcqDVvdbFXg1qLq25gP0+cneMVqbhpb FGuc6CDglgIWalQRx4eBypZ5kGqkNXkSySNwisMk3cjdTmih/AqbM+mUpQCOIjb92l wLlXXAMpqjomw== Received: from [127.0.1.1] (unknown [IPv6:2804:1b1:f803:74:81c8:6a7a:6e11:8f81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id 0817817E1345; Tue, 23 Dec 2025 20:46:37 +0100 (CET) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Tue, 23 Dec 2025 16:44:44 -0300 Subject: [PATCH 03/11] drm/mediatek: ovl: Add supports_plane_colorops flag Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-ovl-pre-blend-colorops-v1-3-0cb99bd0ab33@collabora.com> References: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> In-Reply-To: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, daniels@collabora.com, ariel.dalessandro@collabora.com, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.3 Add a supports_plane_colorops flag to the driver data to allow SoCs that support per-plane color operations to enable support for it in the driver. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Macpaul Lin --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 8e20b45411fc..46238c21b0ac 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -150,6 +150,7 @@ struct mtk_disp_ovl_data { const u32 *formats; size_t num_formats; bool supports_clrfmt_ext; + bool supports_plane_colorops; }; =20 /* --=20 2.51.0 From nobody Mon Feb 9 06:30:58 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE88F199EAD for ; Tue, 23 Dec 2025 19:46:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766519213; cv=none; b=h7carxgfudJgo7M9HaC4oUnxe5qjy63WjgomrDLMX9NiTRHXz8mUP2JBCh78MNvGmOngp89eXeFxFQi60CzC3gfALbC21SZ6CuQyYXnYDZB5Z0Gf7MPXRHnCPgNrMdrI9jnNtcwSoM37hve7tSLkYLdJM4Tw+7ilYBzbzbuLWUk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766519213; c=relaxed/simple; bh=gYnI8T5uMPJ/mmH4wjqwSpKH7oDdWaPT0zX051fZAyE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PGQgsLWKbbK/k3NsFNXmRczPdSeeCWvKe96nwAmYcBC2wNIjN+GfBr6E09a/bKKPVfuUyleb3tACWD5BwlYd8x0sn2gBS/UjybS1jZqXewBFy33YNQaEasLzPNQzE+RfDWlDrW4aA81HzeBYT/XX7RdAWx5+cAREUoBcv/NKF1k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=JoUEImJf; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="JoUEImJf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1766519209; bh=gYnI8T5uMPJ/mmH4wjqwSpKH7oDdWaPT0zX051fZAyE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=JoUEImJfF79JttsO7yI2ZYhVhtn8PkHgh7V3tURXYLmlRoP+O/kQld/5H0kOdcQnr IiJd2Gi1ikc9zupBn2CPlHkmeO55D3FU1QFqBhpi/KgfrwojObM28xc/JTKQ7yATGy ucDXI2I0/0DzueslRI4iRNGdxbfkGJPaxlXPokXAWhrUlpAFpyXtzaml/z5jUWXq4L EuI16PvYkWuZLju5mPPzDO8zY7OceT3Lnryoy2WQSLeA5gSD8DTWhh3ZQUc2U4X8j3 BKgmEiEDSOGbs624JY/v6Gmtn4p6lGAY1Su7Wj0R2qLgtv0qExSd3BYgEMB9//39e4 X/Ehsrpd4z8Nw== Received: from [127.0.1.1] (unknown [IPv6:2804:1b1:f803:74:81c8:6a7a:6e11:8f81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id ECF2B17E150C; Tue, 23 Dec 2025 20:46:43 +0100 (CET) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Tue, 23 Dec 2025 16:44:45 -0300 Subject: [PATCH 04/11] drm/mediatek: ovl: Enable per-plane color operations on MT8195 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-ovl-pre-blend-colorops-v1-4-0cb99bd0ab33@collabora.com> References: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> In-Reply-To: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, daniels@collabora.com, ariel.dalessandro@collabora.com, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.3 MT8195's OVL hardware supports per-plane color operations. Enable support for it in the driver. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Macpaul Lin --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 46238c21b0ac..cfc6a3154f73 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -738,6 +738,7 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver= _data =3D { .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, .supports_afbc =3D true, + .supports_plane_colorops =3D true, .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | BIT(DRM_MODE_BLEND_COVERAGE) | BIT(DRM_MODE_BLEND_PIXEL_NONE), --=20 2.51.0 From nobody Mon Feb 9 06:30:58 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3995349B15 for ; Tue, 23 Dec 2025 19:46:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766519219; cv=none; b=kRMtVQXT61KPxWi9c7uwQWIaYnPO9CyTjYwlvgeGve4EGQvdaeu8GvaPfi68dL33zWG+xvWpFkP2I1CgVjfJ7eoGgx/oURvhqktRDOMWc9o3a7HeHWXXuQwxhyy5h4WOZ3arNpQjfnwHx1ZFfcvN2CTDxbh38rKsYVSQldQOAzE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766519219; c=relaxed/simple; bh=GSvJUVxs8V0DeHgPED5wJ6OeDfsxhUhI5sRmm/TDJXw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OtMaYGGoRcVIrv7cj9IFCpgmV/m9RdFonXnGI1jpXDM4TGtTIt6ey/NoqUyN3Wk7XWFJ7JkuPoX/X7JwyWu+eVfGLzSVve0hEseFhbLHyvSq0n3LWnC2jMLXDeefMSAlrYyB/4cyZ+jDmSgGlk5Q+GAdygYVa5ie8kxMae7fFTY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=FgE4WWJx; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="FgE4WWJx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1766519215; bh=GSvJUVxs8V0DeHgPED5wJ6OeDfsxhUhI5sRmm/TDJXw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=FgE4WWJx0SjrBWAAVdTVP0gnIg3EgFuH9/MebdkJ3+/eR0ZSHdUrHaU11r+uzKqfK 5rISNzDQ1sfbvJunA9G1CaSW4Hyd1cfe8k7nvMOgIRq0e0x3DlRjgb+oF1Ow3MmDci cRKSDvTnjft6GhizVnVUTiITnzEeCRCflsTRoyIkW8f9fz7/NHtJ402+njIdUxckrR DFLYYLq3DGDUScM/P7fS3sdLQ6wHsWxqxv4i8RbkuUctYy1kru715ZmkEOqusdVNEG 4qv/MI5SGDLA3p43KUx0WJxUmvfk63g46k1HwyJPQPr8AVKeh9nRL59PB/P6JMEwAF aQbhSBcf9Pq7g== Received: from [127.0.1.1] (unknown [IPv6:2804:1b1:f803:74:81c8:6a7a:6e11:8f81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id ACFEE17E151B; Tue, 23 Dec 2025 20:46:49 +0100 (CET) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Tue, 23 Dec 2025 16:44:46 -0300 Subject: [PATCH 05/11] drm/mediatek: ovl: Implement support for Inverse Gamma Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-ovl-pre-blend-colorops-v1-5-0cb99bd0ab33@collabora.com> References: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> In-Reply-To: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, daniels@collabora.com, ariel.dalessandro@collabora.com, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.3 The OVL hardware allows selecting between different fixed transfer functions for each layer through the Inverse Gamma setting. Available functions are scRGB and BT.709. Implement support for it and expose it as a colorop through the DRM plane color pipeline uAPI. Signed-off-by: N=C3=ADcolas F. R. A. Prado --- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 + drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 169 ++++++++++++++++++++++++++++= ++++ 2 files changed, 170 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index e0c30c6c7cc8..fde31e3fcc4a 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -115,6 +115,7 @@ void mtk_ovl_disable_vblank(struct device *dev); u32 mtk_ovl_get_blend_modes(struct device *dev); const u32 *mtk_ovl_get_formats(struct device *dev); size_t mtk_ovl_get_num_formats(struct device *dev); +int mtk_ovl_plane_colorops_init(struct device *dev, struct drm_plane *plan= e); bool mtk_ovl_is_afbc_supported(struct device *dev); =20 void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index cfc6a3154f73..4eaa31541ccc 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -4,8 +4,11 @@ */ =20 #include +#include #include #include +#include +#include =20 #include #include @@ -47,6 +50,12 @@ #define OVL_CON_CLRFMT_BIT_DEPTH(depth, n) ((depth) << (4 * (n))) #define OVL_CON_CLRFMT_8_BIT (0) #define OVL_CON_CLRFMT_10_BIT (1) +#define DISP_REG_OVL_WCG_CFG1 0x2d8 +#define IGAMMA_EN(layer) BIT(0 + 4 * (layer)) +#define DISP_REG_OVL_WCG_CFG2 0x2dc +#define IGAMMA_MASK(layer) GENMASK((layer) * 4 + 1, (layer) * 4) +#define IGAMMA_SCRGB 0 +#define IGAMMA_BT709 1 #define DISP_REG_OVL_ADDR_MT8173 0x0f40 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0= x04) @@ -492,6 +501,91 @@ static void mtk_ovl_afbc_layer_config(struct mtk_disp_= ovl *ovl, } } =20 +static int mtk_ovl_colorop_curve_to_reg_val(enum drm_colorop_curve_1d_type= curve) +{ + switch (curve) { + case DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF: + return IGAMMA_SCRGB; + case DRM_COLOROP_1D_CURVE_BT2020_OETF: + return IGAMMA_BT709; + default: + return -EINVAL; + } +} + +static void mtk_ovl_apply_igamma(struct mtk_disp_ovl *ovl, unsigned int id= x, + struct drm_colorop *colorop, + struct cmdq_pkt *cmdq_pkt) +{ + int curve_reg_val; + + if (colorop->state->bypass) { + /* igamma curve needs to be set to default when igamma is disabled */ + curve_reg_val =3D IGAMMA_SCRGB; + } else { + curve_reg_val =3D mtk_ovl_colorop_curve_to_reg_val(colorop->state->curve= _1d_type); + if (curve_reg_val < 0) { + drm_WARN(ovl->crtc->dev, 1, + "Invalid curve 1d type %u\n", + colorop->state->curve_1d_type); + return; + } + } + + mtk_ddp_write_mask(cmdq_pkt, + field_prep(IGAMMA_MASK(idx), curve_reg_val), + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_WCG_CFG2, + IGAMMA_MASK(idx)); + + mtk_ddp_write_mask(cmdq_pkt, + colorop->state->bypass ? 0 : IGAMMA_EN(idx), + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_WCG_CFG1, + IGAMMA_EN(idx)); +} + +static void mtk_ovl_apply_colorop(struct mtk_disp_ovl *ovl, unsigned int i= dx, + struct drm_colorop *colorop, + struct cmdq_pkt *cmdq_pkt) +{ + switch (colorop->type) { + case DRM_COLOROP_1D_CURVE: + mtk_ovl_apply_igamma(ovl, idx, colorop, cmdq_pkt); + break; + default: + drm_WARN(ovl->crtc->dev, 1, "Invalid colorop type %u\n", colorop->type); + break; + } +} + +static void mtk_ovl_disable_colorops(struct mtk_disp_ovl *ovl, unsigned in= t idx, + struct cmdq_pkt *cmdq_pkt) +{ + mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs, + DISP_REG_OVL_WCG_CFG1, + IGAMMA_EN(idx)); + + /* igamma curve needs to be set to default when igamma is disabled */ + mtk_ddp_write_mask(cmdq_pkt, IGAMMA_SCRGB, &ovl->cmdq_reg, ovl->regs, + DISP_REG_OVL_WCG_CFG2, IGAMMA_MASK(idx)); +} + +static void mtk_ovl_apply_colorops(struct mtk_disp_ovl *ovl, unsigned int = idx, + struct mtk_plane_state *state, + struct cmdq_pkt *cmdq_pkt) +{ + if (!ovl->data->supports_plane_colorops) + return; + + if (!state->base.color_pipeline) { + mtk_ovl_disable_colorops(ovl, idx, cmdq_pkt); + return; + } + + for (struct drm_colorop *colorop =3D state->base.color_pipeline; colorop; + colorop =3D colorop->next) + mtk_ovl_apply_colorop(ovl, idx, colorop, cmdq_pkt); +} + void mtk_ovl_layer_config(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt) @@ -513,6 +607,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, return; } =20 + mtk_ovl_apply_colorops(ovl, idx, state, cmdq_pkt); + con =3D mtk_ovl_fmt_convert(ovl, state); if (state->base.fb) { con |=3D state->base.alpha & OVL_CON_ALPHA; @@ -593,6 +689,79 @@ void mtk_ovl_bgclr_in_off(struct device *dev) writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); } =20 +static const struct drm_colorop_funcs mtk_ovl_colorop_funcs =3D { + .destroy =3D drm_colorop_destroy, +}; + +static const u64 igamma_supported_tfs =3D + BIT(DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF) | + BIT(DRM_COLOROP_1D_CURVE_BT2020_OETF); + +#define MAX_COLOR_PIPELINE_OPS 3 + +static int +mtk_ovl_initialize_plane_color_pipeline(struct drm_plane *plane, + struct drm_prop_enum_list *pipeline) +{ + struct drm_colorop *ops[MAX_COLOR_PIPELINE_OPS]; + struct drm_device *dev =3D plane->dev; + int i =3D 0; + int ret; + + memset(ops, 0, sizeof(ops)); + + /* 1st op: OVL's Inverse Gamma */ + ops[i] =3D kzalloc(sizeof(*ops[i]), GFP_KERNEL); + if (!ops[i]) { + ret =3D -ENOMEM; + goto err_alloc; + } + + ret =3D drm_plane_colorop_curve_1d_init(dev, ops[i], plane, + &mtk_ovl_colorop_funcs, + igamma_supported_tfs, + DRM_COLOROP_FLAG_ALLOW_BYPASS); + if (ret) + goto err_colorop_init; + + pipeline->type =3D ops[0]->base.id; + pipeline->name =3D kasprintf(GFP_KERNEL, "Color Pipeline %d", ops[0]->bas= e.id); + + return 0; + +err_colorop_init: + kfree(ops[i]); + +err_alloc: + i--; + for (; i >=3D 0; i--) { + drm_colorop_cleanup(ops[i]); + kfree(ops[i]); + } + + return ret; +} + +int mtk_ovl_plane_colorops_init(struct device *dev, struct drm_plane *plan= e) +{ + struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + struct drm_prop_enum_list pipeline =3D {}; + int ret; + + if (!ovl->data->supports_plane_colorops) + return 0; + + ret =3D mtk_ovl_initialize_plane_color_pipeline(plane, &pipeline); + if (ret) + return ret; + + ret =3D drm_plane_create_color_pipeline_property(plane, &pipeline, 1); + + kfree(pipeline.name); + + return ret; +} + static int mtk_disp_ovl_bind(struct device *dev, struct device *master, void *data) { --=20 2.51.0 From nobody Mon Feb 9 06:30:58 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4563234B678 for ; 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Tue, 23 Dec 2025 20:46:55 +0100 (CET) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Tue, 23 Dec 2025 16:44:47 -0300 Subject: [PATCH 06/11] drm/mediatek: Add plane_colorops_init() DDP hook for OVL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-ovl-pre-blend-colorops-v1-6-0cb99bd0ab33@collabora.com> References: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> In-Reply-To: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, daniels@collabora.com, ariel.dalessandro@collabora.com, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.3 Hook OVL's plane colorops initialization function in DDP to allow its usage by the MediaTek KMS driver. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Macpaul Lin --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index 94b356da6de7..ef906b2aff74 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -331,6 +331,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl =3D { .get_formats =3D mtk_ovl_get_formats, .get_num_formats =3D mtk_ovl_get_num_formats, .is_afbc_supported =3D mtk_ovl_is_afbc_supported, + .plane_colorops_init =3D mtk_ovl_plane_colorops_init, }; =20 static const struct mtk_ddp_comp_funcs ddp_postmask =3D { --=20 2.51.0 From nobody Mon Feb 9 06:30:58 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D957E349AFF for ; Tue, 23 Dec 2025 19:47:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766519229; cv=none; b=X5WgUEnV8AzzYYmBWO3NABFQOQwj7QjZDeeufdtCjmPZ2A0yVTzchYFiRLRzJ1M0i7+eO0jSHCNKkyPRuREIVcmCPVuSg/Asah7OlElc8Hjgyl7y2gI3oDte/9K1cWslk9uXCB5UYy8ard1QJhEK790djBhLPdnV2ElrFZujdog= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766519229; c=relaxed/simple; bh=d65+SB2H0w2cmmN+b2Qd2Ub01bbiCbXtCXzu6iJjU7g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sb3GexIXrVvDa3X6x+ppsLOX5pBqEBfdsR/GcVHQoR9nzjEw8ikcvnU1N3BL+AIBxu2cwu2xJdY0rHC4qxBYKjkiN7E/99JWcjq1gy3kWkbCJoVhnWv0ZG242vpyGm/kq8yzkLCL4zX0kEhmsCbixULIyA3B8lCzFa28si1+Ihg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=MkuWQjTM; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="MkuWQjTM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1766519226; bh=d65+SB2H0w2cmmN+b2Qd2Ub01bbiCbXtCXzu6iJjU7g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MkuWQjTMGWMNMdSoXCRbAoJoRo/EvjuSsMC/g8JBxKi0P2iIfhmY4JI1kLjQbXGVv PVV6xiOr8SwGOlgql5nbAwsydBSAqggmz8vLA/XSjj8QrQJDDWwJwBB/9BtD5AU34K +IcLdMtlotN1KAUaK1uMr6QTNO95d1K3qUG5TAKGfFjUzU0etkn72fCx5bamHiyLQ3 cYPuXDP2wXn1bnO+aBIUMd50GJddmabstAsPzF3ckpedo2F8yiW5MuYqSMIneYeAm6 kBOF90GsJKiu18zCi8qNAwfCRW3VnNHuX7vvwC+C9gvZrTKNNtY3lUZJmCupqgqj7K ZqmKEZmaoQ0cQ== Received: from [127.0.1.1] (unknown [IPv6:2804:1b1:f803:74:81c8:6a7a:6e11:8f81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id 2CA3E17E153F; Tue, 23 Dec 2025 20:47:00 +0100 (CET) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Tue, 23 Dec 2025 16:44:48 -0300 Subject: [PATCH 07/11] drm/colorop: Introduce HLG EOTF Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-ovl-pre-blend-colorops-v1-7-0cb99bd0ab33@collabora.com> References: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> In-Reply-To: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, daniels@collabora.com, ariel.dalessandro@collabora.com, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.3 Introduce definition of a hybrid log-gamma electro-optical transfer function for 1D Curve colorops. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Macpaul Lin --- drivers/gpu/drm/drm_colorop.c | 1 + include/drm/drm_colorop.h | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/drm_colorop.c b/drivers/gpu/drm/drm_colorop.c index fafe45b93ff8..a19e03fb9c7c 100644 --- a/drivers/gpu/drm/drm_colorop.c +++ b/drivers/gpu/drm/drm_colorop.c @@ -79,6 +79,7 @@ static const char * const colorop_curve_1d_type_names[] = =3D { [DRM_COLOROP_1D_CURVE_BT2020_OETF] =3D "BT.2020 OETF", [DRM_COLOROP_1D_CURVE_GAMMA22] =3D "Gamma 2.2", [DRM_COLOROP_1D_CURVE_GAMMA22_INV] =3D "Gamma 2.2 Inverse", + [DRM_COLOROP_1D_CURVE_HLG_EOTF] =3D "HLG", }; =20 static const struct drm_prop_enum_list drm_colorop_lut1d_interpolation_lis= t[] =3D { diff --git a/include/drm/drm_colorop.h b/include/drm/drm_colorop.h index ee6454b08b2d..8ec98521607d 100644 --- a/include/drm/drm_colorop.h +++ b/include/drm/drm_colorop.h @@ -126,6 +126,16 @@ enum drm_colorop_curve_1d_type { * The inverse of &DRM_COLOROP_1D_CURVE_GAMMA22 */ DRM_COLOROP_1D_CURVE_GAMMA22_INV, + + /** + * @DRM_COLOROP_1D_CURVE_HLG_EOTF: + * + * enum string "HLG" + * + * Hybrid log-gamma transfer function. + */ + DRM_COLOROP_1D_CURVE_HLG_EOTF, + /** * @DRM_COLOROP_1D_CURVE_COUNT: * --=20 2.51.0 From nobody Mon Feb 9 06:30:58 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEC6A288522 for ; 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Tue, 23 Dec 2025 20:47:06 +0100 (CET) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Tue, 23 Dec 2025 16:44:49 -0300 Subject: [PATCH 08/11] drm/mediatek: ovl: Implement support for Gamma Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-ovl-pre-blend-colorops-v1-8-0cb99bd0ab33@collabora.com> References: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> In-Reply-To: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, daniels@collabora.com, ariel.dalessandro@collabora.com, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.3 The OVL hardware allows selecting between different fixed transfer functions for each layer through the Gamma setting. Available functions are scRGB, BT.709, BT.2020 and HLG. Implement support for it and expose it as a colorop through the DRM plane color pipeline uAPI. Signed-off-by: N=C3=ADcolas F. R. A. Prado --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 67 +++++++++++++++++++++++++++++= +++- 1 file changed, 65 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 4eaa31541ccc..a70092c792a9 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -52,10 +52,16 @@ #define OVL_CON_CLRFMT_10_BIT (1) #define DISP_REG_OVL_WCG_CFG1 0x2d8 #define IGAMMA_EN(layer) BIT(0 + 4 * (layer)) +#define GAMMA_EN(layer) BIT(2 + 4 * (layer)) #define DISP_REG_OVL_WCG_CFG2 0x2dc #define IGAMMA_MASK(layer) GENMASK((layer) * 4 + 1, (layer) * 4) #define IGAMMA_SCRGB 0 #define IGAMMA_BT709 1 +#define GAMMA_MASK(layer) GENMASK((layer) * 4 + 3, (layer) * 4 + 2) +#define GAMMA_SCRGB 0 +#define GAMMA_BT709 1 +#define GAMMA_BT2020 2 +#define GAMMA_HLG 3 #define DISP_REG_OVL_ADDR_MT8173 0x0f40 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0= x04) @@ -508,11 +514,41 @@ static int mtk_ovl_colorop_curve_to_reg_val(enum drm_= colorop_curve_1d_type curve return IGAMMA_SCRGB; case DRM_COLOROP_1D_CURVE_BT2020_OETF: return IGAMMA_BT709; + case DRM_COLOROP_1D_CURVE_SRGB_EOTF: + return GAMMA_SCRGB; + case DRM_COLOROP_1D_CURVE_BT2020_INV_OETF: + return GAMMA_BT2020; + case DRM_COLOROP_1D_CURVE_HLG_EOTF: + return GAMMA_HLG; default: return -EINVAL; } } =20 +static void mtk_ovl_apply_gamma(struct mtk_disp_ovl *ovl, unsigned int idx, + struct drm_colorop *colorop, + struct cmdq_pkt *cmdq_pkt) +{ + int curve_reg_val; + + curve_reg_val =3D mtk_ovl_colorop_curve_to_reg_val(colorop->state->curve_= 1d_type); + if (curve_reg_val < 0) { + drm_WARN(ovl->crtc->dev, 1, "Invalid curve 1d type %u\n", + colorop->state->curve_1d_type); + return; + } + + mtk_ddp_write_mask(cmdq_pkt, + field_prep(GAMMA_MASK(idx), curve_reg_val), + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_WCG_CFG2, + GAMMA_MASK(idx)); + + mtk_ddp_write_mask(cmdq_pkt, + colorop->state->bypass ? 0 : GAMMA_EN(idx), + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_WCG_CFG1, + GAMMA_EN(idx)); +} + static void mtk_ovl_apply_igamma(struct mtk_disp_ovl *ovl, unsigned int id= x, struct drm_colorop *colorop, struct cmdq_pkt *cmdq_pkt) @@ -549,7 +585,11 @@ static void mtk_ovl_apply_colorop(struct mtk_disp_ovl = *ovl, unsigned int idx, { switch (colorop->type) { case DRM_COLOROP_1D_CURVE: - mtk_ovl_apply_igamma(ovl, idx, colorop, cmdq_pkt); + /* gamma is the last colorop in pipeline */ + if (!colorop->next) + mtk_ovl_apply_gamma(ovl, idx, colorop, cmdq_pkt); + else + mtk_ovl_apply_igamma(ovl, idx, colorop, cmdq_pkt); break; default: drm_WARN(ovl->crtc->dev, 1, "Invalid colorop type %u\n", colorop->type); @@ -562,7 +602,7 @@ static void mtk_ovl_disable_colorops(struct mtk_disp_ov= l *ovl, unsigned int idx, { mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_WCG_CFG1, - IGAMMA_EN(idx)); + IGAMMA_EN(idx) | GAMMA_EN(idx)); =20 /* igamma curve needs to be set to default when igamma is disabled */ mtk_ddp_write_mask(cmdq_pkt, IGAMMA_SCRGB, &ovl->cmdq_reg, ovl->regs, @@ -697,6 +737,11 @@ static const u64 igamma_supported_tfs =3D BIT(DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF) | BIT(DRM_COLOROP_1D_CURVE_BT2020_OETF); =20 +static const u64 gamma_supported_tfs =3D + BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF) | + BIT(DRM_COLOROP_1D_CURVE_BT2020_INV_OETF) | + BIT(DRM_COLOROP_1D_CURVE_HLG_EOTF); + #define MAX_COLOR_PIPELINE_OPS 3 =20 static int @@ -724,6 +769,24 @@ mtk_ovl_initialize_plane_color_pipeline(struct drm_pla= ne *plane, if (ret) goto err_colorop_init; =20 + i++; + + /* 3rd op: OVL's Gamma */ + ops[i] =3D kzalloc(sizeof(*ops[i]), GFP_KERNEL); + if (!ops[i]) { + ret =3D -ENOMEM; + goto err_alloc; + } + + ret =3D drm_plane_colorop_curve_1d_init(dev, ops[i], plane, + &mtk_ovl_colorop_funcs, + gamma_supported_tfs, + DRM_COLOROP_FLAG_ALLOW_BYPASS); + if (ret) + goto err_colorop_init; + + drm_colorop_set_next_property(ops[i - 1], ops[i]); + pipeline->type =3D ops[0]->base.id; pipeline->name =3D kasprintf(GFP_KERNEL, "Color Pipeline %d", ops[0]->bas= e.id); =20 --=20 2.51.0 From nobody Mon Feb 9 06:30:58 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A3CC288522 for ; Tue, 23 Dec 2025 19:47:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Tue, 23 Dec 2025 20:47:12 +0100 (CET) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Tue, 23 Dec 2025 16:44:50 -0300 Subject: [PATCH 09/11] drm/colorop: Introduce 3x3 Matrix Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-ovl-pre-blend-colorops-v1-9-0cb99bd0ab33@collabora.com> References: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> In-Reply-To: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, daniels@collabora.com, ariel.dalessandro@collabora.com, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.3 Introduce a 3x3 Matrix colorop analogous to the 3x4 Matrix colorop, with the difference of not supporting offset coefficients. Signed-off-by: N=C3=ADcolas F. R. A. Prado Acked-by: Pekka Paalanen --- drivers/gpu/drm/drm_atomic.c | 1 + drivers/gpu/drm/drm_atomic_uapi.c | 3 +++ drivers/gpu/drm/drm_colorop.c | 21 +++++++++++++++++++++ include/drm/drm_colorop.h | 3 +++ include/uapi/drm/drm_mode.h | 16 ++++++++++++++++ 5 files changed, 44 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 6d3ea8056b60..bf4a31c02b70 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -802,6 +802,7 @@ static void drm_atomic_colorop_print_state(struct drm_p= rinter *p, drm_printf(p, "\tdata blob id=3D%d\n", state->data ? state->data->base.i= d : 0); break; case DRM_COLOROP_CTM_3X4: + case DRM_COLOROP_CTM_3X3: drm_printf(p, "\tdata blob id=3D%d\n", state->data ? state->data->base.i= d : 0); break; case DRM_COLOROP_MULTIPLIER: diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic= _uapi.c index 7320db4b8489..7a70e894a2ef 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -709,6 +709,9 @@ static int drm_atomic_color_set_data_property(struct dr= m_colorop *colorop, size =3D colorop->size * colorop->size * colorop->size * sizeof(struct drm_color_lut32); break; + case DRM_COLOROP_CTM_3X3: + size =3D sizeof(struct drm_color_ctm); + break; default: /* should never get here */ return -EINVAL; diff --git a/drivers/gpu/drm/drm_colorop.c b/drivers/gpu/drm/drm_colorop.c index a19e03fb9c7c..51c1a0726dfa 100644 --- a/drivers/gpu/drm/drm_colorop.c +++ b/drivers/gpu/drm/drm_colorop.c @@ -68,6 +68,7 @@ static const struct drm_prop_enum_list drm_colorop_type_e= num_list[] =3D { { DRM_COLOROP_CTM_3X4, "3x4 Matrix"}, { DRM_COLOROP_MULTIPLIER, "Multiplier"}, { DRM_COLOROP_3D_LUT, "3D LUT"}, + { DRM_COLOROP_CTM_3X3, "3x3 Matrix"}, }; =20 static const char * const colorop_curve_1d_type_names[] =3D { @@ -377,6 +378,26 @@ int drm_plane_colorop_ctm_3x4_init(struct drm_device *= dev, struct drm_colorop *c } EXPORT_SYMBOL(drm_plane_colorop_ctm_3x4_init); =20 +int drm_plane_colorop_ctm_3x3_init(struct drm_device *dev, struct drm_colo= rop *colorop, + struct drm_plane *plane, const struct drm_colorop_funcs *funcs, + uint32_t flags) +{ + int ret; + + ret =3D drm_plane_colorop_init(dev, colorop, plane, funcs, DRM_COLOROP_CT= M_3X3, flags); + if (ret) + return ret; + + ret =3D drm_colorop_create_data_prop(dev, colorop); + if (ret) + return ret; + + drm_colorop_reset(colorop); + + return 0; +} +EXPORT_SYMBOL(drm_plane_colorop_ctm_3x3_init); + /** * drm_plane_colorop_mult_init - Initialize a DRM_COLOROP_MULTIPLIER * diff --git a/include/drm/drm_colorop.h b/include/drm/drm_colorop.h index 8ec98521607d..ee7fa0eb5dbf 100644 --- a/include/drm/drm_colorop.h +++ b/include/drm/drm_colorop.h @@ -426,6 +426,9 @@ int drm_plane_colorop_curve_1d_lut_init(struct drm_devi= ce *dev, struct drm_color int drm_plane_colorop_ctm_3x4_init(struct drm_device *dev, struct drm_colo= rop *colorop, struct drm_plane *plane, const struct drm_colorop_funcs *funcs, uint32_t flags); +int drm_plane_colorop_ctm_3x3_init(struct drm_device *dev, struct drm_colo= rop *colorop, + struct drm_plane *plane, const struct drm_colorop_funcs *funcs, + uint32_t flags); int drm_plane_colorop_mult_init(struct drm_device *dev, struct drm_colorop= *colorop, struct drm_plane *plane, const struct drm_colorop_funcs *funcs, uint32_t flags); diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index cbbbfc1dfe2b..b894b19eb9f8 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -964,6 +964,22 @@ enum drm_colorop_type { * color =3D lut3d[index] */ DRM_COLOROP_3D_LUT, + + /** + * @DRM_COLOROP_CTM_3X3: + * + * enum string "3x3 Matrix" + * + * A 3x3 matrix. Its values are specified via the + * &drm_color_ctm struct provided via the DATA property. + * + * The DATA blob is a float[9]: + * out matrix in + * | R | | 0 1 2 | | R | + * | G | =3D | 3 4 5 | x | G | + * | B | | 6 7 8 | | B | + */ + DRM_COLOROP_CTM_3X3, }; =20 /** --=20 2.51.0 From nobody Mon Feb 9 06:30:58 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08A8334C80D for ; Tue, 23 Dec 2025 19:47:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766519248; cv=none; b=Mwf6mwrHgE62CvbHhVJtpqajJCDa0ifRkXM3pbflfA1dUEISQcLGqvqUnclbEefd47hDyx1REkYJM/35c7Ms96xql77UjZ0dIxHWQ2iEUJ0ZTJI2c29ATmu0fZeuA/uZAwzFh8Rh2sdBDv/1fiRbLeGVzuOgzYjIUTk4O3ZqjHg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766519248; c=relaxed/simple; bh=vD870d938nwYIyegPWMdbDmlJ2S2wI475Vgc02Kli+Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hhOFyiD1Ov+jkseLKK0G6qG2wHDp2yTZEUcZCLCgKmy2BR9zIIsXddxS6Yd7eAqkf5cuOo9vQj2prLejMW7K2TIYvxnVfygHkxaP9FX91/7q3skHBImO7bPvQoRkOMdAVJNLkouLEPWOQU6rWsHGhFy/eKNa9ABFNeu39FC6eWY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=aLtCQkC3; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="aLtCQkC3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1766519244; bh=vD870d938nwYIyegPWMdbDmlJ2S2wI475Vgc02Kli+Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=aLtCQkC3a5T2UWir+7wR8cn3YzmtoBembHI8xZ0fPYB2FyK5PSgwhT/3jj5pzRtNB MJyd0hRnE2bdzhOclDxEoamqa9KyiGSjMXWp6dqAw9TItMQpFiBVyuE8B7oXisjwdE pa7Nk4v6epgb4wuvDWeCuT2ISN1igstXhvUZsTYk89n/W3G9+LxMa3P+p9sxdIrAb1 VeqOqHJRx2QapMHfCSqjTMKdflhOL3jCewsd5BaPS4IgHPqcXaskHbLcnN/Pv4X5sJ iYyZPxMRAtWWnzxMSVbVB9/UXEaBSajuuyIysyNtNJVTaRXQmhz2DPbphsqnBXlU9/ CTnTcuF5X/WNw== Received: from [127.0.1.1] (unknown [IPv6:2804:1b1:f803:74:81c8:6a7a:6e11:8f81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id 8E14F17E35DC; Tue, 23 Dec 2025 20:47:18 +0100 (CET) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Tue, 23 Dec 2025 16:44:51 -0300 Subject: [PATCH 10/11] drm/mediatek: ovl: Enable support for R2R Color Space Conversion Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-ovl-pre-blend-colorops-v1-10-0cb99bd0ab33@collabora.com> References: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> In-Reply-To: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, daniels@collabora.com, ariel.dalessandro@collabora.com, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.3 The OVL hardware allows applying a 3x3 matrix transformation for each layer through the 'RGB to RGB Color Space Conversion' (R2R CSC) setting. Implement support for it and expose it as a colorop through the DRM plane color pipeline uAPI. Signed-off-by: N=C3=ADcolas F. R. A. Prado --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 55 +++++++++++++++++++++++++++++= +++- 1 file changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index a70092c792a9..c8a2b1b13035 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include #include @@ -52,6 +53,7 @@ #define OVL_CON_CLRFMT_10_BIT (1) #define DISP_REG_OVL_WCG_CFG1 0x2d8 #define IGAMMA_EN(layer) BIT(0 + 4 * (layer)) +#define CSC_EN(layer) BIT(1 + 4 * (layer)) #define GAMMA_EN(layer) BIT(2 + 4 * (layer)) #define DISP_REG_OVL_WCG_CFG2 0x2dc #define IGAMMA_MASK(layer) GENMASK((layer) * 4 + 1, (layer) * 4) @@ -62,6 +64,7 @@ #define GAMMA_BT709 1 #define GAMMA_BT2020 2 #define GAMMA_HLG 3 +#define DISP_REG_OVL_R2R_PARA(layer) (0x500 + (layer) * 0x40) #define DISP_REG_OVL_ADDR_MT8173 0x0f40 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0= x04) @@ -579,11 +582,44 @@ static void mtk_ovl_apply_igamma(struct mtk_disp_ovl = *ovl, unsigned int idx, IGAMMA_EN(idx)); } =20 +static void mtk_ovl_write_r2r_para(struct mtk_disp_ovl *ovl, unsigned int = idx, + struct drm_color_ctm *ctm, + struct cmdq_pkt *cmdq_pkt) +{ + unsigned int i; + u64 val; + + for (i =3D 0; i < ARRAY_SIZE(ctm->matrix); i++) { + val =3D drm_color_ctm_s31_32_to_qm_n(ctm->matrix[i], 5, 18); + mtk_ddp_write(cmdq_pkt, val, &ovl->cmdq_reg, ovl->regs, + DISP_REG_OVL_R2R_PARA(idx) + i * 4); + } +} + +static void mtk_ovl_apply_r2r_csc(struct mtk_disp_ovl *ovl, unsigned int i= dx, + struct drm_colorop *colorop, + struct cmdq_pkt *cmdq_pkt) +{ + struct drm_color_ctm *ctm; + + if (colorop->state->data && colorop->state->data->data) { + ctm =3D (struct drm_color_ctm *)colorop->state->data->data; + mtk_ovl_write_r2r_para(ovl, idx, ctm, cmdq_pkt); + } + + mtk_ddp_write_mask(cmdq_pkt, colorop->state->bypass ? 0 : CSC_EN(idx), + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_WCG_CFG1, + CSC_EN(idx)); +} + static void mtk_ovl_apply_colorop(struct mtk_disp_ovl *ovl, unsigned int i= dx, struct drm_colorop *colorop, struct cmdq_pkt *cmdq_pkt) { switch (colorop->type) { + case DRM_COLOROP_CTM_3X3: + mtk_ovl_apply_r2r_csc(ovl, idx, colorop, cmdq_pkt); + break; case DRM_COLOROP_1D_CURVE: /* gamma is the last colorop in pipeline */ if (!colorop->next) @@ -602,7 +638,7 @@ static void mtk_ovl_disable_colorops(struct mtk_disp_ov= l *ovl, unsigned int idx, { mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_WCG_CFG1, - IGAMMA_EN(idx) | GAMMA_EN(idx)); + IGAMMA_EN(idx) | CSC_EN(idx) | GAMMA_EN(idx)); =20 /* igamma curve needs to be set to default when igamma is disabled */ mtk_ddp_write_mask(cmdq_pkt, IGAMMA_SCRGB, &ovl->cmdq_reg, ovl->regs, @@ -771,6 +807,23 @@ mtk_ovl_initialize_plane_color_pipeline(struct drm_pla= ne *plane, =20 i++; =20 + /* 2nd op: OVL's R2R Color Space Conversion */ + ops[i] =3D kzalloc(sizeof(*ops[i]), GFP_KERNEL); + if (!ops[i]) { + ret =3D -ENOMEM; + goto err_alloc; + } + + ret =3D drm_plane_colorop_ctm_3x3_init(dev, ops[i], plane, + &mtk_ovl_colorop_funcs, + DRM_COLOROP_FLAG_ALLOW_BYPASS); + if (ret) + goto err_colorop_init; + + drm_colorop_set_next_property(ops[i - 1], ops[i]); + + i++; + /* 3rd op: OVL's Gamma */ ops[i] =3D kzalloc(sizeof(*ops[i]), GFP_KERNEL); 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Tue, 23 Dec 2025 20:47:24 +0100 (CET) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Tue, 23 Dec 2025 16:44:52 -0300 Subject: [PATCH 11/11] drm/mediatek: Check 3x3 Matrix colorop has DATA set Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-mtk-ovl-pre-blend-colorops-v1-11-0cb99bd0ab33@collabora.com> References: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> In-Reply-To: <20251223-mtk-ovl-pre-blend-colorops-v1-0-0cb99bd0ab33@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, daniels@collabora.com, ariel.dalessandro@collabora.com, kernel@collabora.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.3 Add an atomic check hook for the CRTC and use it to verify that any 3x3 Matrix colorop, which requires the DATA property to be set, does in fact have it set. Signed-off-by: N=C3=ADcolas F. R. A. Prado --- drivers/gpu/drm/mediatek/mtk_crtc.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek= /mtk_crtc.c index f7db235d986f..1a55d5df6dbe 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -897,6 +897,31 @@ static void mtk_crtc_atomic_flush(struct drm_crtc *crt= c, mtk_crtc_update_config(mtk_crtc, !!mtk_crtc->event); } =20 +static int mtk_crtc_atomic_check(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + struct drm_colorop_state *new_colorop_state; + struct drm_colorop *colorop; + int i; + + for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) { + switch (colorop->type) { + case DRM_COLOROP_CTM_3X3: + if (!new_colorop_state->bypass && !new_colorop_state->data) { + drm_dbg_atomic(crtc->dev, + "Missing required DATA property for COLOROP:%d\n", + colorop->base.id); + return -EINVAL; + } + break; + default: + break; + } + } + + return 0; +} + static const struct drm_crtc_funcs mtk_crtc_funcs =3D { .set_config =3D drm_atomic_helper_set_config, .page_flip =3D drm_atomic_helper_page_flip, @@ -914,6 +939,7 @@ static const struct drm_crtc_helper_funcs mtk_crtc_help= er_funcs =3D { .mode_valid =3D mtk_crtc_mode_valid, .atomic_begin =3D mtk_crtc_atomic_begin, .atomic_flush =3D mtk_crtc_atomic_flush, + .atomic_check =3D mtk_crtc_atomic_check, .atomic_enable =3D mtk_crtc_atomic_enable, .atomic_disable =3D mtk_crtc_atomic_disable, }; --=20 2.51.0