From nobody Mon Feb 9 13:07:35 2026 Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57EFD30E0EC; Tue, 23 Dec 2025 09:11:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=15.184.224.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766481103; cv=none; b=iD6L1W1T0BjslYTn+iC4burA5K3szIvtZGAubPyl6VlPiZIS7i0F9VbGPAiNM94dwpjqcK+QdA6ZVX2Bvmwm1g0xV0uGzNdAPe3K7KW0o0oF1PzEqY0ANwNNrvqjqRg5UOxLK2ot2kRoAZ/EKpwOGJua7ctP6C4o2AsLRtV6LlQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766481103; c=relaxed/simple; bh=zRP5kB8Bg0I+gikI6IUrIjghYJOlbkwuwGj2YrT1/uQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=L+eWfMQ1gmrf0JBPH39aNcGIHutiaBIl5VprKMG01OHwRA70KQOPmR48tvzc+Y5Wu6y8OnRQHdgfgHDJb+LR663MWmuZgujfxeWfSL0W8Vf1oPc7IJ1B87Xyqof6W8mtjF+5qmLnsThGt6lADUo4+9petueMi+6fKpX36NaizKs= ARC-Authentication-Results: i=1; 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Tue, 23 Dec 2025 17:11:17 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 16625877039514221719 EX-QQ-RecipientCnt: 15 From: Troy Mitchell Date: Tue, 23 Dec 2025 17:11:11 +0800 Subject: [PATCH 1/2] dt-bindings: pinctrl: add syscon property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-kx-pinctrl-aib-io-pwr-domain-v1-1-5f1090a487c7@linux.spacemit.com> References: <20251223-kx-pinctrl-aib-io-pwr-domain-v1-0-5f1090a487c7@linux.spacemit.com> In-Reply-To: <20251223-kx-pinctrl-aib-io-pwr-domain-v1-0-5f1090a487c7@linux.spacemit.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Linus Walleij Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Troy Mitchell X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766481072; l=1822; i=troy.mitchell@linux.spacemit.com; s=20250710; h=from:subject:message-id; bh=zRP5kB8Bg0I+gikI6IUrIjghYJOlbkwuwGj2YrT1/uQ=; b=0tXUZiZUb+RN2K+xRaLFxkhamxEESjAbc7gBfBZnoQgXETKe8O0dEMIxF9lWZXZlYpf1HpqJk BDgX8EB9hl6BmyEAwCzlu/1S8yUKyIrpDHvY53DmpMHWeeGDv+IlHvq X-Developer-Key: i=troy.mitchell@linux.spacemit.com; a=ed25519; pk=lQa7BzLrq8DfZnChqmwJ5qQk8fP2USmY/4xZ2/MSsXc= X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpsz:linux.spacemit.com:qybglogicsvrgz:qybglogicsvrgz3a-0 X-QQ-XMAILINFO: MDnRDgydGgijA+Gkzwpx3Rh1GvXTopId7EDaFXze43+6qbQI7xgrUPUd 4keIB5iYKSfFHqCQrnRlXMlOXsqscY/xAnzhJ3ECu07B7GwvHYiyYxNdvf2DDwHeVjnLJZH 5hdnBbIEdvxK6aCfmJdkl1y4nmPA0nmQRTToVqJky8nYfmF88plISFT0f/uEOft8scMrNwA ejQFU0bec96SDSq279tLoPkSBpfiOv4PqYPCZ9z4rKNM9ZFHxxX7DhT3o8qPrMLUfCMWC3O UEQy5CIotnhZrXpgt3DUgUhiiwUKZkOK/85fyX8Qwax0xAWM6DOLOEEZSf9PAdhPHukHU0p 28Wwq/rx3r8EgYaRQhzfTf3M6z/CrhEsDg0U+7jE6zy2Sua85Ss3WXKs7MBsszGT8uG5DZw bgXjINnXtIAqc1V4FOT9Lvt0ut3AitXgQ6sl9Q6Efwf6/UZRROUfWFkctiBaj0Gp2uDO2PI hCwUFwq0+vZtw1MkPRafsy1XJgYJ6kGUECnSQqZoHj1RBkkZIu2l7FN3t/cEDOxmUUdOqcR UZ+FltfYsGj+hR5CdOM/H9jEXt7uPykYDM3QTo6sc5ukof5C9FcDQU3CP2Z3h8QK0iskCAU 6/+Ygm/Kfn2odILcSJBgoPQ3KgsUvXtJtfEyGtEBs/dSJWZW9UCgehP8bYOeDLFvyVyPts4 Ohb2xM77de8tltLEKxVJtol/dUJX2yKwKx0jgXw8xjLOdXvIxJTYIhzDQl3luYCz8oBbsRA HyjpN1hrRM0RMsnJ9kq58yalz2TINDvYZ9cMWTe1S4HqcRXecXTMcfQ9SfKLuQ19WlMCvIq h/zklohEJILgroSkHqAOY8gcLM9jJwqv7bwUfPSOMg7Y7zj5zS6n8J14phEBKzlLVgVyDVn Wvh/Es6RgPxrebWv94zyiq4z/u2bz4b2clwF+K3+vRjPybarozPHNmnHTz0ISaBg1pcRKbq PXJUwm2vv4qw56iZBSPrcnajie+GZazxd1M4D6u2c2kBgGLrqvj4glBe5wlZ6cw6F9VTISx CR+UJv+ec4NFy78V3+54evHNrlMr2K7+hZVtpK86A8m9C/SJOYdKRm20kGFxx+Qn1Zh+Qgg BlJzipYl9zjFFVlbgC8XtnuSDlqsS40yJrKvweO38casEFlrdYCW7AofEj9iVNEAatkL8ta POIqQQ4Bw9k86ixZtqhMkIoUbw== X-QQ-XMRINFO: OD9hHCdaPRBwH5bRRRw8tsiH4UAatJqXfg== X-QQ-RECHKSPAM: 0 In order to access the protected IO power domain registers, a valid unlock sequence must be performed by writing the required keys to the AIB Secure Access Register (ASAR). The ASAR register resides within the APBC register address space. A corresponding syscon property is added to allow the pinctrl driver to access this register. Signed-off-by: Troy Mitchell --- .../devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml | 11 +++++++= ++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.= yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml index c5b0218ad6251f97b1f27089ffff724a7b0f69ae..4dc49c2cc1d52008ad89896ae04= 19091802cd2c4 100644 --- a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml @@ -32,6 +32,15 @@ properties: resets: maxItems: 1 =20 + spacemit,apbc: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to syscon that access the protected regis= ter + - description: offset of access secure registers + description: + A phandle to syscon with byte offset to access the protected register + patternProperties: '-cfg$': type: object @@ -111,6 +120,7 @@ required: - reg - clocks - clock-names + - spacemit,apbc =20 additionalProperties: false =20 @@ -128,6 +138,7 @@ examples: clocks =3D <&syscon_apbc 42>, <&syscon_apbc 94>; clock-names =3D "func", "bus"; + spacemit,apbc =3D <&syscon_apbc 0x50>; =20 uart0_2_cfg: uart0-2-cfg { uart0-2-pins { --=20 2.52.0 From nobody Mon Feb 9 13:07:35 2026 Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE3FE3242B8; Tue, 23 Dec 2025 09:11:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=18.194.254.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766481107; cv=none; b=hIQoop7db3EJaggJQq7+8KLeZHsj3yPoQBHrZLAqGbqbphZXmPIJ3snOUb8jo/QtNV5Phl2AgBcjuU1TaJKNwgA7XD8zlXwMA4QEOxV5sA3ktDikph2QGdM3BKLUcR1a3Y4NDtXdWxQDWmfi4XEkrBd5BfY4zUsv57WAK4qEXs0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766481107; c=relaxed/simple; bh=H8MAD1flgSxo90tf4qKPSiR3GbcLMbZ+riVLpJiUFeU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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b=b25sziMaYkJj6TWS0rS8sEdVnQPfHQI1F3GvwzvnOy/MOof5HxrL5AzYgAwKTXW0E wgp/vnPL8wnA5Lb9xq+w4ns8RgIUrSv2zwMjs6gvXYGL7jzCKNo4pAb1rTQS/jN5jS khB7JdNqDKZWxHzGwuV7NMmFnmMQF3BDkm7YbyZc= X-QQ-mid: zesmtpgz6t1766481084t16904670 X-QQ-Originating-IP: kcO+ntnvqeIk2ReWF769Ryi38sTAnoxbRaBrt9Wf5Cg= Received: from = ( [120.237.158.181]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 23 Dec 2025 17:11:21 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 13884977633580607309 EX-QQ-RecipientCnt: 15 From: Troy Mitchell Date: Tue, 23 Dec 2025 17:11:12 +0800 Subject: [PATCH 2/2] pinctrl: spacemit: support I/O power domain configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-kx-pinctrl-aib-io-pwr-domain-v1-2-5f1090a487c7@linux.spacemit.com> References: <20251223-kx-pinctrl-aib-io-pwr-domain-v1-0-5f1090a487c7@linux.spacemit.com> In-Reply-To: <20251223-kx-pinctrl-aib-io-pwr-domain-v1-0-5f1090a487c7@linux.spacemit.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Linus Walleij Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Troy Mitchell X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766481072; l=9633; i=troy.mitchell@linux.spacemit.com; s=20250710; h=from:subject:message-id; bh=H8MAD1flgSxo90tf4qKPSiR3GbcLMbZ+riVLpJiUFeU=; b=Ryg7x+nRbvlWZcilYWuGa/45Bnr1Zz4dgKQfhGSaY7yKcvi1U/0C8htiYBTG/5qUhhyEILGRn Obe2NsP1zEBAt2meH8kGgwMXi2+xW2HFXSlP6Tbo4xac8NtGYHNolve X-Developer-Key: i=troy.mitchell@linux.spacemit.com; a=ed25519; pk=lQa7BzLrq8DfZnChqmwJ5qQk8fP2USmY/4xZ2/MSsXc= X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpgz:linux.spacemit.com:qybglogicsvrgz:qybglogicsvrgz3a-0 X-QQ-XMAILINFO: M8UYpcaD4/AyS8a3BcSFzGH5h+uKd/n2rApXT1TY9mXtNd18lSE09Pik sFfveubgSWNCOGXbcRsjKvOAnNwNUuqQB6pBn3TPVhDvJ8gn76yVSGP/SJaNnXvI9VV4DoW lKMTo+ZJvOER9mQGN7zE+sBXPJNkB76huFwcJZNrn9GtQGBB5CrKz2mpyktkeVVZp/CnwK7 qOes+Omea0fOZ+jR9IwU7cX0HpJr8GAdWBI/ecX4oi1BBLddwP/+NniTR7WQMAOO5/ycwxX +GfcYAPzxpdRmuh2gHm4ZtOA5N58VB6NONeXEATSIRCVWZbVKEUAqCyPMZ06bubvisFJB1p i0TSZj6MPkwXap0BhlgMBBZtqvhlhAyssEc+nkvCtGUTH76x2Z/yJWQ8VLVTdpkpuU4AHc2 TtrGcwiLWQuImHnwcKNHPxLiuhLlhQ78kVkf6W6xCnpM7qsupaznoY0HyMdFoGBAvZ2xk5D WCNUZ0apwBuraai8MkCwiUwOAiXXYeIkijWqWvFZXUmMCAXD3qMpa+U4wzvM3JMFZhREg+R Q7fh5a4ckiQvL2Y4Dd61URkMRPvs+pdWueVVQiRgxk2OiH7lQRj93RqR3JT2wVAVwvQzzKw ft3Xn3gV0PuVCZrqKaeYOith7PcJc0/iU0S1D9ZDwUq9C8bQVmzPVruIkBO4vaozT8rt85J Ly/0ExEpiQbGWSc9FViGYTTk9kQszXGASB5dLiMycMcI4Tw56FldDo2xS4+u1BdJNs5HpuS g9W8JDGLIXwbNdP8kidxupM+RICwKLapf8JmiqenBAYMIVlpMNBCE/F1LvvPV/+PYWO/zt2 tPh1Zpk3bheVUUacEQsAr6ljVVhWrNptW45UIwp185+fdFjw8ArknUMXvcPZwG1F2h3qXzH kl32xJMDeEsj1az220TRFrGTO8UCbdY3A31zXE7Jao+yyBxRMYeZDrjMUiPgIwx5cBuLWDj n47Mkmo6RlAtsrJsTvpCC/SiF8TpdGL+0eO0g93zmqMQeYF5RW1kVDvOTxPeRBNVuZsxNoi bM3hyn33nkBrqJXDsRX+5KbTKzgY/knfOZo84lOkWgKUa11eWujuH2XZi6h58nRJXI93zRY o3O0H6yUq5gs6YEyWBle7q6pHEHjPu//muFHeNQhn36+h+iJu3RI3Lt3Luwrg0pp7NyHSG2 zhtM10YgoVWCR8Q/Sdu7uucXdg== X-QQ-XMRINFO: MPJ6Tf5t3I/ylTmHUqvI8+Wpn+Gzalws3A== X-QQ-RECHKSPAM: 0 IO domain power control registers are used to configure the operating voltage of dual-voltage GPIO banks. By default, these registers are configured for 3.3V operation. As a result, even when a GPIO bank is externally supplied with 1.8V, the internal logic continues to operate in the 3.3V domain, which may lead to functional failures. This patch adds support for programming the IO domain power control registers, allowing dual-voltage GPIO banks to be explicitly configured for 1.8V operation when required. Care must be taken when configuring these registers. If a GPIO bank is externally supplied with 3.3V while the corresponding IO power domain is configured for 1.8V, external current injection (back-powering) may occur, potentially causing damage to the GPIO pin. Due to these hardware constraints and safety considerations, the IO domain power control registers are implemented as secure registers. Access to these registers requires unlocking via the AIB Secure Access Register (ASAR) in the APBC block before a single read or write operation can be performed. Signed-off-by: Troy Mitchell --- arch/riscv/boot/dts/spacemit/k1.dtsi | 4 +- drivers/pinctrl/spacemit/pinctrl-k1.c | 131 ++++++++++++++++++++++++++++++= +++- 2 files changed, 131 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spa= cemit/k1.dtsi index 7818ca4979b6a7755722919a5958512aa11950ab..23ecb19624f227f3c39de35bf30= 78379f7a2490e 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -565,10 +565,12 @@ i2c8: i2c@d401d800 { =20 pinctrl: pinctrl@d401e000 { compatible =3D "spacemit,k1-pinctrl"; - reg =3D <0x0 0xd401e000 0x0 0x400>; + reg =3D <0x0 0xd401e000 0x0 0x400>, + <0x0 0xd401e800 0x0 0x34>; clocks =3D <&syscon_apbc CLK_AIB>, <&syscon_apbc CLK_AIB_BUS>; clock-names =3D "func", "bus"; + spacemit,apbc =3D <&syscon_apbc 0x50>; }; =20 pwm8: pwm@d4020000 { diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacem= it/pinctrl-k1.c index 8ca247fb8ba0321c02423f9739130e03277d1053..b3ffb32f88a79ebf6b64e62a784= 6df60b92799fe 100644 --- a/drivers/pinctrl/spacemit/pinctrl-k1.c +++ b/drivers/pinctrl/spacemit/pinctrl-k1.c @@ -7,8 +7,10 @@ #include #include #include +#include #include #include +#include #include #include =20 @@ -47,6 +49,25 @@ #define PAD_PULLUP BIT(14) #define PAD_PULL_EN BIT(15) =20 +#define IO_PWR_DOMAIN_GPIO2_Kx 0x0c +#define IO_PWR_DOMAIN_MMC_Kx 0x1c + +#define IO_PWR_DOMAIN_GPIO3_K1 0x10 +#define IO_PWR_DOMAIN_QSPI_K1 0x20 + +#define IO_PWR_DOMAIN_GPIO1_K3 0x04 +#define IO_PWR_DOMAIN_GPIO5_K3 0x10 +#define IO_PWR_DOMAIN_GPIO4_K3 0x20 +#define IO_PWR_DOMAIN_QSPI_K3 0x2c + +#define IO_PWR_DOMAIN_V18EN BIT(2) + +#define APBC_ASFAR 0x00 +#define APBC_ASSAR 0x04 + +#define APBC_ASFAR_AKEY 0xbaba +#define APBC_ASSAR_AKEY 0xeb10 + struct spacemit_pin_drv_strength { u8 val; u32 mA; @@ -78,6 +99,10 @@ struct spacemit_pinctrl { raw_spinlock_t lock; =20 void __iomem *regs; + void __iomem *io_pd_reg; + + struct regmap *regmap_apbc; + u32 regmap_apbc_offset; }; =20 struct spacemit_pinctrl_data { @@ -85,6 +110,7 @@ struct spacemit_pinctrl_data { const struct spacemit_pin *data; u16 npins; unsigned int (*pin_to_offset)(unsigned int pin); + unsigned int (*pin_to_io_pd_offset)(unsigned int pin); const struct spacemit_pinctrl_dconf *dconf; }; =20 @@ -146,6 +172,56 @@ static unsigned int spacemit_k3_pin_to_offset(unsigned= int pin) return offset << 2; } =20 +static unsigned int spacemit_k1_pin_to_io_pd_offset(unsigned int pin) +{ + unsigned int offset =3D 0; + + switch (pin) { + case 47 ... 52: + offset =3D IO_PWR_DOMAIN_GPIO3_K1; + break; + case 75 ... 80: + offset =3D IO_PWR_DOMAIN_GPIO2_Kx; + break; + case 98 ... 103: + offset =3D IO_PWR_DOMAIN_QSPI_K1; + break; + case 104 ... 109: + offset =3D IO_PWR_DOMAIN_MMC_Kx; + break; + } + + return offset; +} + +static unsigned int spacemit_k3_pin_to_io_pd_offset(unsigned int pin) +{ + unsigned int offset =3D 0; + + switch (pin) { + case 0 ... 20: + offset =3D IO_PWR_DOMAIN_GPIO1_K3; + break; + case 21 ... 41: + offset =3D IO_PWR_DOMAIN_GPIO2_Kx; + break; + case 76 ... 98: + offset =3D IO_PWR_DOMAIN_GPIO4_K3; + break; + case 99 ... 127: + offset =3D IO_PWR_DOMAIN_GPIO5_K3; + break; + case 132 ... 137: + offset =3D IO_PWR_DOMAIN_MMC_Kx; + break; + case 138 ... 144: + offset =3D IO_PWR_DOMAIN_QSPI_K3; + break; + } + + return offset; +} + static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *p= ctrl, unsigned int pin) { @@ -365,6 +441,38 @@ static int spacemit_pctrl_check_power(struct pinctrl_d= ev *pctldev, return 0; } =20 +static void spacemit_set_io_pwr_domain(struct spacemit_pinctrl *pctrl, + const struct spacemit_pin *spin, + const enum spacemit_pin_io_type type) +{ + u32 offset =3D pctrl->data->pin_to_io_pd_offset(spin->pin); + u32 val =3D 0; + + /* Other bits are reserved so don't need to save them */ + if (type =3D=3D IO_TYPE_1V8) + val =3D IO_PWR_DOMAIN_V18EN; + + /* + * IO power domain registers are protected and cannot be accessed + * directly. Before performing any read or write to the IO power + * domain registers, an explicit unlock sequence must be issued + * via the AIB Secure Access Register (ASAR). + * + * The unlock sequence allows exactly one subsequent access to the + * IO power domain registers. After that access completes, the ASAR + * keys are automatically cleared, and the registers become locked + * again. + * + * This mechanism ensures that IO power domain configuration is + * performed intentionally, as incorrect voltage settings may + * result in functional failures or hardware damage. + */ + regmap_write(pctrl->regmap_apbc, pctrl->regmap_apbc_offset + APBC_ASFAR, = APBC_ASFAR_AKEY); + regmap_write(pctrl->regmap_apbc, pctrl->regmap_apbc_offset + APBC_ASSAR, = APBC_ASSAR_AKEY); + + writel_relaxed(val, pctrl->io_pd_reg + offset); +} + static int spacemit_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **maps, @@ -572,7 +680,8 @@ static int spacemit_pinconf_get(struct pinctrl_dev *pct= ldev, =20 #define ENABLE_DRV_STRENGTH BIT(1) #define ENABLE_SLEW_RATE BIT(2) -static int spacemit_pinconf_generate_config(const struct spacemit_pin *spi= n, +static int spacemit_pinconf_generate_config(struct spacemit_pinctrl *pctrl, + const struct spacemit_pin *spin, const struct spacemit_pinctrl_dconf *dconf, unsigned long *configs, unsigned int num_configs, @@ -646,6 +755,7 @@ static int spacemit_pinconf_generate_config(const struc= t spacemit_pin *spin, default: return -EINVAL; } + spacemit_set_io_pwr_domain(pctrl, spin, type); } =20 val =3D spacemit_get_driver_strength(type, dconf, drv_strength); @@ -701,7 +811,7 @@ static int spacemit_pinconf_set(struct pinctrl_dev *pct= ldev, const struct spacemit_pin *spin =3D spacemit_get_pin(pctrl, pin); u32 value; =20 - if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf, + if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, configs, num_configs, &value)) return -EINVAL; =20 @@ -724,7 +834,7 @@ static int spacemit_pinconf_group_set(struct pinctrl_de= v *pctldev, return -EINVAL; =20 spin =3D spacemit_get_pin(pctrl, group->grp.pins[0]); - if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf, + if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, configs, num_configs, &value)) return -EINVAL; =20 @@ -795,6 +905,7 @@ static const struct pinconf_ops spacemit_pinconf_ops = =3D { =20 static int spacemit_pinctrl_probe(struct platform_device *pdev) { + struct device_node *np =3D pdev->dev.of_node; struct device *dev =3D &pdev->dev; struct spacemit_pinctrl *pctrl; struct clk *func_clk, *bus_clk; @@ -816,6 +927,18 @@ static int spacemit_pinctrl_probe(struct platform_devi= ce *pdev) if (IS_ERR(pctrl->regs)) return PTR_ERR(pctrl->regs); =20 + pctrl->io_pd_reg =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(pctrl->io_pd_reg)) + return PTR_ERR(pctrl->io_pd_reg); + + pctrl->regmap_apbc =3D + syscon_regmap_lookup_by_phandle_args(np, "spacemit,apbc", 1, + &pctrl->regmap_apbc_offset); + + if (IS_ERR(pctrl->regmap_apbc)) + return dev_err_probe(dev, PTR_ERR(pctrl->regmap_apbc), + "failed to get syscon\n"); + func_clk =3D devm_clk_get_enabled(dev, "func"); if (IS_ERR(func_clk)) return dev_err_probe(dev, PTR_ERR(func_clk), "failed to get func clock\n= "); @@ -1118,6 +1241,7 @@ static const struct spacemit_pinctrl_data k1_pinctrl_= data =3D { .data =3D k1_pin_data, .npins =3D ARRAY_SIZE(k1_pin_desc), .pin_to_offset =3D spacemit_k1_pin_to_offset, + .pin_to_io_pd_offset =3D spacemit_k1_pin_to_io_pd_offset, .dconf =3D &k1_drive_conf, }; =20 @@ -1455,6 +1579,7 @@ static const struct spacemit_pinctrl_data k3_pinctrl_= data =3D { .data =3D k3_pin_data, .npins =3D ARRAY_SIZE(k3_pin_desc), .pin_to_offset =3D spacemit_k3_pin_to_offset, + .pin_to_io_pd_offset =3D spacemit_k3_pin_to_io_pd_offset, .dconf =3D &k3_drive_conf, }; =20 --=20 2.52.0