From nobody Mon Feb 9 02:12:51 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5768532F74D; Tue, 23 Dec 2025 10:02:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766484172; cv=none; b=daJ6wXEPDF4SR4irLUe+pCx3XYDFRk7+CiOD7JmnqH/dRq4YOzPxSl+ebRpsmej4QHjbMorhMzS9vfB8oW5lw62lahyFnqD98qSGxxWA1dM7UJktxOxv/AAU0A7drF96spGSuajMvabOtuR209lJHGml9kRCAtqLsaGQtZn+xTE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766484172; c=relaxed/simple; bh=jHCMrBULvwVzv5JpCqHP1Kn3GqfcRs7OGNudExX2Uo4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PWUecsu2EGXpDN85BJtL3JWZLuy9UyLv2kA4lJOGJ7CwFyqQmbxNq7Kbnf/w61k2gZZtn3MwJn+nxGo8WjcbKu7WI+RRBPQGXtcgZynnhPV+lo+amIZWu7l+yrIF0IPt0kJGsTf9k6JR55yan9RIhuZqIaFzU/w6IZUlQRxFDhM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=l+FnPcgm; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="l+FnPcgm" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id A9E99C1AE1F; Tue, 23 Dec 2025 10:02:21 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id BCC2160716; Tue, 23 Dec 2025 10:02:46 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 46BF410AB09BC; Tue, 23 Dec 2025 11:02:44 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1766484165; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=riB5KJaXNeA6IOitdQ8kr+NsrOyX+9YKQFa5ylL1kOc=; b=l+FnPcgmFXHpECPCxUm1P7xp7rhcecAGBpyoCiMtkSubnvQPfVSh7YDVWyD8AOQuvaLv/G MxXfKSRHXTK3ZOWBhsEmZuqo/M5y8CseoVat61PNHahFizfDC9M0Mjx+Gfwv0z6mdcI5m3 X0q9arPxxgNZgniWw0bWr8B4/ecSGdRbZ3O9f9aTpZWWqTDNLeNjY98PAzoFu8wWPcJ++O geSNQm6pOKbYqczPYYq5bde7SbZdHPXGGedbjty10CzngqNO0Kd7bZw2GDgeCWdYpyUZY5 /nCZpkmAF7m036wc0EIa0h/IcoWCBoEZxEh8mN3i/py1PHjo+GVhzUNzDdh8NA== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Tue, 23 Dec 2025 11:02:25 +0100 Subject: [PATCH v2 10/13] MIPS: Add Mobileye EyeQ6Lplus SoC dtsi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251223-eyeq6lplus-v2-10-cd1fd21d182c@bootlin.com> References: <20251223-eyeq6lplus-v2-0-cd1fd21d182c@bootlin.com> In-Reply-To: <20251223-eyeq6lplus-v2-0-cd1fd21d182c@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Philipp Zabel , Linus Walleij Cc: Thomas Petazzoni , Tawfik Bayouk , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add the device tree include files for the EyeQ6Lplus system on chip from Mobileye. Those files provide the initial support of the SoC: * The I6500 CPU and GIC interrupt controller. * The OLB ("Other Logic Block") providing clocks, resets and pin controls. * One UART. * One GPIO controller. * Two SPI controllers, one in host mode and one in target mode. * One octoSPI flash controller. * Two I2C controllers. Signed-off-by: Beno=C3=AEt Monin --- arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi | 84 +++++++++++ arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi | 169 +++++++++++++++++++= ++++ 2 files changed, 253 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi b/arch/mips/b= oot/dts/mobileye/eyeq6lplus-pins.dtsi new file mode 100644 index 000000000000..5cb0660f46c6 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +&olb { + timer0_pins: timer0-pins { + function =3D "timer0"; + pins =3D "PA0", "PA1"; + }; + timer1_pins: timer1-pins { + function =3D "timer1"; + pins =3D "PA2", "PA3"; + }; + uart_ssi_pins: uart-ssi-pins { + function =3D "uart_ssi"; + pins =3D "PA4", "PA5"; + }; + spi0_pins: spi0-pins { + function =3D "spi0"; + pins =3D "PA6", "PA7", "PA8", "PA9"; + }; + uart0_pins: uart0-pins { + function =3D "uart0"; + pins =3D "PA11", "PA12"; + }; + timer2_pins: timer2-pins { + function =3D "timer2"; + pins =3D "PA13", "PA14"; + }; + timer3_pins: timer3-pins { + function =3D "timer3"; + pins =3D "PA15", "PA16"; + }; + timer_ext0_pins: timer-ext0-pins { + function =3D "timer_ext0"; + pins =3D "PA17", "PA18", "PA19", "PA20"; + }; + timer_ext0_input_a_pins: timer-ext0-input-a-pins { + function =3D "timer_ext0"; + pins =3D "PA17"; + }; + pps0_pins: pps0-pins { + function =3D "timer_ext0"; + pins =3D "PA17"; + }; + timer_ext0_input_b_pins: timer-ext0-input-b-pins { + function =3D "timer_ext0"; + pins =3D "PA18"; + }; + timer_ext0_output_pins: timer-ext0-output-pins { + function =3D "timer_ext0"; + pins =3D "PA19", "PA20"; + }; + spi1_pins: spi1-pins { + function =3D "spi1"; + pins =3D "PA21", "PA22", "PA23", "PA24"; + }; + spi1_reduced_pins: spi1-reduced-pins { + function =3D "spi1"; + pins =3D "PA21", "PA22", "PA23"; + }; + timer_ext1_pins: timer-ext1-pins { + function =3D "timer_ext1"; + pins =3D "PA26", "PA27", "PA28", "PA29"; + }; + timer_ext1_input_a_pins: timer-ext1-input-a-pins { + function =3D "timer_ext1"; + pins =3D "PA26"; + }; + timer_ext1_input_b_pins: timer-ext1-input-b-pins { + function =3D "timer_ext1"; + pins =3D "PA27"; + }; + timer_ext1_output_pins: timer-ext1-output-pins { + function =3D "timer_ext1"; + pins =3D "PA28", "PA29"; + }; + ext_ref_clk_pins: ext-ref-clk-pins { + function =3D "ext_ref_clk"; + pins =3D "PA30"; + }; + mipi_ref_clk_pins: mipi-ref-clk-pins { + function =3D "mipi_ref_clk"; + pins =3D "PA31"; + }; +}; diff --git a/arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi b/arch/mips/boot/d= ts/mobileye/eyeq6lplus.dtsi new file mode 100644 index 000000000000..28131ea558f6 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +/* + * Copyright 2025 Mobileye Vision Technologies Ltd. + */ + +#include + +#include + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + cpu@0 { + device_type =3D "cpu"; + compatible =3D "img,i6500"; + reg =3D <0>; + clocks =3D <&olb EQ6LPC_CPU_OCC>; + }; + }; + + cpu_intc: interrupt-controller { + compatible =3D "mti,cpu-interrupt-controller"; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + + coherency-manager { + compatible =3D "mobileye,eyeq6-cm"; + }; + + xtal: clock-30000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <30000000>; + }; + + soc: soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + olb: system-controller@e8400000 { + compatible =3D "mobileye,eyeq6lplus-olb", "syscon"; + reg =3D <0 0xe8400000 0x0 0x80000>; + #reset-cells =3D <2>; + #clock-cells =3D <1>; + clocks =3D <&xtal>; + clock-names =3D "ref"; + }; + + ospi: spi@e8800000 { + compatible =3D "mobileye,eyeq5-ospi", "cdns,qspi-nor"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0xe8800000 0x0 0x100000>, + <0 0xb0000000 0x0 0x30000000>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x00000000>; + clocks =3D <&olb EQ6LPC_PER_OSPI>; + status =3D "disabled"; + }; + + spi0: spi@eac0d000 { + compatible =3D "snps,dw-apb-ssi"; + reg =3D <0 0xeac0d000 0x0 0x1000>; + clocks =3D <&olb EQ6LPC_PER_SPI>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + resets =3D <&olb 0 0>; + reset-names =3D "spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi1: spi@eac0e000 { + compatible =3D "snps,dw-apb-ssi"; + reg =3D <0 0xeac0e000 0x0 0x1000>; + spi-slave; + clocks =3D <&olb EQ6LPC_PER_SPI>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + resets =3D <&olb 0 1>; + reset-names =3D "spi"; + #address-cells =3D <0>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart0: serial@eac10000 { + compatible =3D "snps,dw-apb-uart"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&olb EQ6LPC_PER_UART>; + clock-frequency =3D <15625000>; + reg =3D <0 0xeac10000 0x0 0x1000>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + resets =3D <&olb 0 2>; + status =3D "disabled"; + }; + + i2c0: i2c@eac11000 { + compatible =3D "mobileye,eyeq6lplus-i2c", "snps,designware-i2c"; + reg =3D <0 0xeac11000 0x0 0x1000>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + clock-frequency =3D <400000>; + clocks =3D <&olb EQ6LPC_PER_I2C_SER>; + resets =3D <&olb 0 3>; + i2c-sda-hold-time-ns =3D <50>; + status =3D "disabled"; + }; + + i2c1: i2c@eac12000 { + compatible =3D "mobileye,eyeq6lplus-i2c", "snps,designware-i2c"; + reg =3D <0 0xeac12000 0x0 0x1000>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + clock-frequency =3D <400000>; + clocks =3D <&olb EQ6LPC_PER_I2C_SER>; + resets =3D <&olb 0 4>; + i2c-sda-hold-time-ns =3D <50>; + status =3D "disabled"; + }; + + gpio: gpio@eac14000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0x0 0xeac14000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + resets =3D <&olb 0 13>; + porta: gpio-port@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <32>; + gpio-ranges =3D <&olb 0 0 32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + }; + + gic: interrupt-controller@f0920000 { + compatible =3D "mti,gic"; + reg =3D <0x0 0xf0920000 0x0 0x20000>; + interrupt-controller; + #interrupt-cells =3D <3>; + interrupt-parent =3D <&cpu_intc>; + timer { + compatible =3D "mti,gic-timer"; + interrupts =3D ; + clocks =3D <&olb EQ6LPC_CPU_OCC>; + }; + }; + }; +}; + +#include "eyeq6lplus-pins.dtsi" --=20 2.52.0