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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4f4ac66a1aasm72500001cf.33.2025.12.22.02.25.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Dec 2025 02:25:20 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, Dmitry Baryshkov Subject: [PATCH v4 08/11] drm/msm/dpu: Add interrupt registers for DPU 13.0.0 Date: Mon, 22 Dec 2025 18:23:57 +0800 Message-Id: <20251222102400.1109-9-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> References: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=SIhPlevH c=1 sm=1 tr=0 ts=69491c91 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=RfJNy9JZAWTFlj1jTG0A:9 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-ORIG-GUID: SzOMsfEz39QQA1c5BVRl94D2ouUctnz8 X-Proofpoint-GUID: SzOMsfEz39QQA1c5BVRl94D2ouUctnz8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA5NCBTYWx0ZWRfXztLEegj7DJ4I /F7KzkiFekEmfCG1sIp3X7zbdtZzXZuHvcQiEVsY+RcDjm4FbRd/UW4eRCz2P7Hv5U6zpqXRmQF YCNlx21bmLRn5+zJSSvgaRRkvqM7dWzfVi88/COUgpZIP1g+Q/6ySrDUJd2AXoh4jzJ0CWHLNzi E3NXBBK9DtgZV2blZ5nEzuTJ+F8RA8Ic4Gtp+vRYVDwEyQjTbhzGih2FKxoff9xahnQrB36jQGb EG6FAvtrD3ldS9VmxrZUxyZW06DrFJDPw222OsVhHWbDGyvTofzrFUIobPqTPH2y10HRTZRokOm xG1bsqqFe85DjsHRQ4vQjx099QVCvIpG02a1HqtAEPAOPvNFucE/nWPEslBhf5/WSgOjg1w/9Ch l4FIxlXuRbMxSsAv5LDDKqSDp5DJou+0ltCuKQhJMZPM0c9CB0I3x6ohlzkqbe0JIJjmp0zbRVP TmJ2YkK1oNE9KRYRKmg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 adultscore=0 phishscore=0 spamscore=0 suspectscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220094 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang DPU version 13.0.0 introduces changes to the interrupt register layout. Update the driver to support these modifications for proper interrupt handling. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov Signed-off-by: Yuanjie Yang --- .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 89 ++++++++++++++++++- 1 file changed, 88 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gp= u/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 49bd77a755aa..5b7cd5241f45 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -40,6 +40,15 @@ #define MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(intf) (MDP_INTF_REV_7xxx_TEAR_O= FF(intf) + 0x004) #define MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(intf) (MDP_INTF_REV_7xxx_TEAR_O= FF(intf) + 0x008) =20 +#define MDP_INTF_REV_13xx_OFF(intf) (0x18d000 + 0x1000 * (intf)) +#define MDP_INTF_REV_13xx_INTR_EN(intf) (MDP_INTF_REV_13xx_OFF(intf) + 0= x1c0) +#define MDP_INTF_REV_13xx_INTR_STATUS(intf) (MDP_INTF_REV_13xx_OFF(intf) = + 0x1c4) +#define MDP_INTF_REV_13xx_INTR_CLEAR(intf) (MDP_INTF_REV_13xx_OFF(intf) += 0x1c8) +#define MDP_INTF_REV_13xx_TEAR_OFF(intf) (0x18d800 + 0x1000 * (intf)) +#define MDP_INTF_REV_13xx_INTR_TEAR_EN(intf) (MDP_INTF_REV_13xx_TEAR_OFF(= intf) + 0x000) +#define MDP_INTF_REV_13xx_INTR_TEAR_STATUS(intf) (MDP_INTF_REV_13xx_TEAR_O= FF(intf) + 0x004) +#define MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(intf) (MDP_INTF_REV_13xx_TEAR_O= FF(intf) + 0x008) + /** * struct dpu_intr_reg - array of DPU register sets * @clr_off: offset to CLEAR reg @@ -199,6 +208,82 @@ static const struct dpu_intr_reg dpu_intr_set_7xxx[] = =3D { }, }; =20 +/* + * dpu_intr_set_13xx - List of DPU interrupt registers for DPU >=3D 13.0 + */ +static const struct dpu_intr_reg dpu_intr_set_13xx[] =3D { + [MDP_SSPP_TOP0_INTR] =3D { + INTR_CLEAR, + INTR_EN, + INTR_STATUS + }, + [MDP_SSPP_TOP0_INTR2] =3D { + INTR2_CLEAR, + INTR2_EN, + INTR2_STATUS + }, + [MDP_SSPP_TOP0_HIST_INTR] =3D { + HIST_INTR_CLEAR, + HIST_INTR_EN, + HIST_INTR_STATUS + }, + [MDP_INTF0_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(0), + MDP_INTF_REV_13xx_INTR_EN(0), + MDP_INTF_REV_13xx_INTR_STATUS(0) + }, + [MDP_INTF1_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(1), + MDP_INTF_REV_13xx_INTR_EN(1), + MDP_INTF_REV_13xx_INTR_STATUS(1) + }, + [MDP_INTF1_TEAR_INTR] =3D { + MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(1), + MDP_INTF_REV_13xx_INTR_TEAR_EN(1), + MDP_INTF_REV_13xx_INTR_TEAR_STATUS(1) + }, + [MDP_INTF2_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(2), + MDP_INTF_REV_13xx_INTR_EN(2), + MDP_INTF_REV_13xx_INTR_STATUS(2) + }, + [MDP_INTF2_TEAR_INTR] =3D { + MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(2), + MDP_INTF_REV_13xx_INTR_TEAR_EN(2), + MDP_INTF_REV_13xx_INTR_TEAR_STATUS(2) + }, + [MDP_INTF3_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(3), + MDP_INTF_REV_13xx_INTR_EN(3), + MDP_INTF_REV_13xx_INTR_STATUS(3) + }, + [MDP_INTF4_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(4), + MDP_INTF_REV_13xx_INTR_EN(4), + MDP_INTF_REV_13xx_INTR_STATUS(4) + }, + [MDP_INTF5_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(5), + MDP_INTF_REV_13xx_INTR_EN(5), + MDP_INTF_REV_13xx_INTR_STATUS(5) + }, + [MDP_INTF6_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(6), + MDP_INTF_REV_13xx_INTR_EN(6), + MDP_INTF_REV_13xx_INTR_STATUS(6) + }, + [MDP_INTF7_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(7), + MDP_INTF_REV_13xx_INTR_EN(7), + MDP_INTF_REV_13xx_INTR_STATUS(7) + }, + [MDP_INTF8_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(8), + MDP_INTF_REV_13xx_INTR_EN(8), + MDP_INTF_REV_13xx_INTR_STATUS(8) + }, +}; + #define DPU_IRQ_MASK(irq_idx) (BIT(DPU_IRQ_BIT(irq_idx))) =20 static inline bool dpu_core_irq_is_valid(unsigned int irq_idx) @@ -507,7 +592,9 @@ struct dpu_hw_intr *dpu_hw_intr_init(struct drm_device = *dev, if (!intr) return ERR_PTR(-ENOMEM); =20 - if (m->mdss_ver->core_major_ver >=3D 7) + if (m->mdss_ver->core_major_ver >=3D 13) + intr->intr_set =3D dpu_intr_set_13xx; + else if (m->mdss_ver->core_major_ver >=3D 7) intr->intr_set =3D dpu_intr_set_7xxx; else intr->intr_set =3D dpu_intr_set_legacy; --=20 2.34.1