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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4f4ac66a1aasm72500001cf.33.2025.12.22.02.24.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Dec 2025 02:24:24 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com Subject: [PATCH v4 01/11] dt-bindings: display/msm: qcom,kaanapali-dpu: Add Kaanapali Date: Mon, 22 Dec 2025 18:23:50 +0800 Message-Id: <20251222102400.1109-2-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> References: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: FH-oPnpLuulGgWoWZGhD7cRuc6BIMpc4 X-Authority-Analysis: v=2.4 cv=cuuWUl4i c=1 sm=1 tr=0 ts=69491c59 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=LEfPF28z9Y6gGZEU5FYA:9 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA5NCBTYWx0ZWRfX5HuYgNPSmFK3 QI7R5NrROn8w6PGCVIIw2uAWmKoJe3i0iM08ovcWNoAEuITxfHzvrcX+izHfl4jN/9u/AEnu8De LA0qivUkjwEgR73A1MBi9sSr/HEvwaq20zPOtQ2ZavuLmnJKy0nC5o/8nPBO4ZL48K3OoooqEjf 41UHkz1R2ohSEdUoEI5QwX2VhS5fCMiJ15PCj37Nuomqk8/9dW938W+nDoRZ5gX2nqtNRcjMviM 7Mt+mdVcaYqqm7dxkqOtalh/sqmSwWhkO+Hgp+QdGhec7d3rfBPzbWT5jN5FWi81FIbYoRjBnnR V8aBZ0ymYMOdePX3RwrvyNrEAyflgUlHUW99M7YqtwUZ4+ePNl3/jzP6ubZFp6jxXGQoe1+TQ5k Gzx/onzoTY63ZiSVYI6GQmUy/4mpOn9WXbAco1GdaaBQU0GKZgdp9oP5Kmo0z27ejhrbS0KiO7R wSpgGwBz1jq4qEmRigg== X-Proofpoint-GUID: FH-oPnpLuulGgWoWZGhD7cRuc6BIMpc4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 priorityscore=1501 spamscore=0 bulkscore=0 suspectscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220094 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang Add DPU version 13.0 for Qualcomm Kaanapali Soc. The Kaanapali DPU and SM8750 have significant differences, including additions and removals of registers, as well as changes in register addresses. Acked-by: Rob Herring (Arm) Signed-off-by: Yuanjie Yang --- .../devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml index fe296e3186d0..e29c4687c3a2 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml @@ -16,6 +16,7 @@ properties: oneOf: - enum: - qcom,glymur-dpu + - qcom,kaanapali-dpu - qcom,sa8775p-dpu - qcom,sm8650-dpu - qcom,sm8750-dpu --=20 2.34.1 From nobody Sun Feb 8 21:05:53 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14EDD331235 for ; Mon, 22 Dec 2025 10:24:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4f4ac66a1aasm72500001cf.33.2025.12.22.02.24.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Dec 2025 02:24:32 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, Krzysztof Kozlowski Subject: [PATCH v4 02/11] dt-bindings: display/msm: dsi-phy-7nm: Add Kaanapali DSI PHY Date: Mon, 22 Dec 2025 18:23:51 +0800 Message-Id: <20251222102400.1109-3-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> References: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: uS_bp98kR5Bs0A1K2EKxlbKiJK0f31v_ X-Authority-Analysis: v=2.4 cv=EvnfbCcA c=1 sm=1 tr=0 ts=69491c61 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=tNVMJPnUsVqa3Ada0T4A:9 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-GUID: uS_bp98kR5Bs0A1K2EKxlbKiJK0f31v_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA5NCBTYWx0ZWRfX6T+E81rBVliG DQ41wW/Gz3IFS2Gh+dkZk/jW94ZjIDPxkmgoTIJ1OmTOu7o7lKHS5Lk0mWhir/58AZ89/vI+BIK /2cjR1ht6qbBCrD+j6KckvnZJsC6D/RkKYHcizheHSYsPRlULw5/195eg8fA7PyQOgG8PkLoWBv kHREmLkR/iuHFdOqV4CSsH6FM2NaR/VS2uESGE4cz2S2O1JyuTw+OrgV2mMyiYOS4ekkWt+oWda oBrxYQAtQmWbAfP4Drhck/jzpinneUM+xEXv5b6vtBkGS0bex4qRyHXcG1OT04MuhbRRa9VeJZc dN5dqryuRk4BlEyGzL4CJAYafI9NjS3Ic5An0xra7zpjGk+f6/kMlxM+c5k3nGYUAE/gUA+UldI geyg38RBaZLiIuPUfSt3rf+YF733FieW0Zhj4Yu43qG0/jUBWsyTXtcePcg74Mj9iwf76Y5jN/9 2VWw+tTuqehRFnI27IQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 phishscore=0 adultscore=0 clxscore=1015 priorityscore=1501 spamscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220094 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang The DSI PHY registers on the Kaanapali platform differ from those on SM8750. So add DSI PHY for Kaanapali to compatible these changes. Acked-by: Krzysztof Kozlowski Signed-off-by: Yuanjie Yang --- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml= b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml index 1ca820a500b7..a6e044eed3df 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -17,6 +17,7 @@ properties: enum: - qcom,dsi-phy-7nm - qcom,dsi-phy-7nm-8150 + - qcom,kaanapali-dsi-phy-3nm - qcom,sa8775p-dsi-phy-5nm - qcom,sar2130p-dsi-phy-5nm - qcom,sc7280-dsi-phy-7nm --=20 2.34.1 From nobody Sun Feb 8 21:05:53 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1B0C31326C for ; Mon, 22 Dec 2025 10:24:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4f4ac66a1aasm72500001cf.33.2025.12.22.02.24.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Dec 2025 02:24:40 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, Krzysztof Kozlowski Subject: [PATCH v4 03/11] dt-bindings: display/msm: dsi-controller-main: Add Kaanapali Date: Mon, 22 Dec 2025 18:23:52 +0800 Message-Id: <20251222102400.1109-4-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> References: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: mtPDIYqNpzPpEzBtA74G6_7ctrAfwCcw X-Authority-Analysis: v=2.4 cv=dPWrWeZb c=1 sm=1 tr=0 ts=69491c69 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=NRHHWUy0EX9jfUzwrTwA:9 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-ORIG-GUID: mtPDIYqNpzPpEzBtA74G6_7ctrAfwCcw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA5NCBTYWx0ZWRfXyiUusffp607s vRBwPm6o5Yf/r+9sfHCc5WcG5Ia0nUbWzfvmyRHpXQ9HKHQusIzx9Pc4qrBChfki60o9s/DzyFU aGEIKdWsZkomv9l/+eqjmsGZ26WEdEDXX1PqoHJ1KuFa3wzVWTqTYFJsoEFzlW628xQQLYS0d98 zB9rRrXXv9QNWAht/Aw+p9RKXKjQ7XlFxeS6+g2mISw4+hN5URlWZUGZtdw0CEPKQfPk7+CCGLq lH08E2YgBleSxXibqFuzSt7FcEv+MxaZtoCEjghwYUAVUOIvUBXJCDcEKvVKxzdBbS2gMuPK12p woOsVQjiz3YMfkiMgTqdVzNfpcvK0qRr0Ht8oqxKxKtO0f3TepsauYIqg6Cym9SIeFgAy9iD3dW 8/JfYxAae+qq2F0BbhPUYyoONeJZ0oUUGyy9nrkBdkQogNB2bMk6ns5UxGetZAdsbJHQytc0Qga LQ3dzItoDUKhmRbnagA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220094 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang The DSI registers on the Kaanapali platform differ from those on SM8750. So add DSI for Kaanapali to compatible these changes. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Yuanjie Yang --- .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-m= ain.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-mai= n.yaml index 4400d4cce072..536ebf331828 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -15,6 +15,7 @@ properties: - items: - enum: - qcom,apq8064-dsi-ctrl + - qcom,kaanapali-dsi-ctrl - qcom,msm8226-dsi-ctrl - qcom,msm8916-dsi-ctrl - qcom,msm8953-dsi-ctrl @@ -369,6 +370,7 @@ allOf: compatible: contains: enum: + - qcom,kaanapali-dsi-ctrl - qcom,sm8750-dsi-ctrl then: properties: --=20 2.34.1 From nobody Sun Feb 8 21:05:53 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02A953321B0 for ; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4f4ac66a1aasm72500001cf.33.2025.12.22.02.24.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Dec 2025 02:24:48 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com Subject: [PATCH v4 04/11] dt-bindings: display/msm: qcom,kaanapali-mdss: Add Kaanapali Date: Mon, 22 Dec 2025 18:23:53 +0800 Message-Id: <20251222102400.1109-5-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> References: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: dwG4wtS5hCWXHZcakx35u9BVI0Qd83vY X-Authority-Analysis: v=2.4 cv=dPWrWeZb c=1 sm=1 tr=0 ts=69491c71 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=ttgK4pBlxCW4zpXUERAA:9 a=uxP6HrT_eTzRwkO_Te1X:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: dwG4wtS5hCWXHZcakx35u9BVI0Qd83vY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA5NCBTYWx0ZWRfX73u6RMNxVGku O3vDy8gcnPwQJDNZyqZabUTcrxgrIk6WVgEXLkqBh/m7AgNhQFVNN5ynobdhqmt0wGe5Z+aM+lT bEjSPbfXOOZOq0yMJmEPpm6+d+2Xvk+QpqKD0oMTS9Ml06tLsvt1CFBQ0Ar8PlgsYb9EYWBbhYA 0D69qw1/LTLwHUea5mWMQ3lr0hFXcXqQKiCELrUVqDrdHjIzA8y09WGDPnGpv98hGADQmGZM8/y cUzSU03ZKwbu3qVNqyShsOUMV2zMgjjb+ZdchKe5V+IhVk5rr+NqjMyz/mpDeGbj1QH6uoi3Xi/ JUdoLp4vyu4Dz39SRV7iU7sSr26W27aHKhar9b/l8XrQhHAeONS6xuVQYG4kO46+7HxGHHk1UrR 0vIYlzsim/p5UZ1s87xdfcVq/sUC3ZH65DEUCXc77DyhzIbIgpErLDkSypcLi4KIYwrxmVZzR6Q kdE6eed2Jqmp94/pj+w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220094 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang Kaanapali introduces DPU 13.0.0 and DSI 2.10. Compared to SM8750, Kaanapali has significant register changes, making it incompatible with SM8750. So add MDSS/MDP display subsystem for Qualcomm Kaanapali. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Signed-off-by: Yuanjie Yang --- .../display/msm/qcom,kaanapali-mdss.yaml | 297 ++++++++++++++++++ 1 file changed, 297 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,kaan= apali-mdss.yaml diff --git a/Documentation/devicetree/bindings/display/msm/qcom,kaanapali-m= dss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mds= s.yaml new file mode 100644 index 000000000000..9f935defd6b1 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mdss.yaml @@ -0,0 +1,297 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,kaanapali-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Kaanapali Display MDSS + +maintainers: + - Yongxing Mou + - Yuanjie Yang + +description: + Kaanapali MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blo= cks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,kaanapali-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + - description: Display AHB SWI + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,kaanapali-dpu + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,kaanapali-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,kaanapali-dsi-phy-3nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@9800000 { + compatible =3D "qcom,kaanapali-mdss"; + reg =3D <0x09800000 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + + clocks =3D <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&disp_cc_mdss_mdp_clk>, + <&disp_cc_mdss_ahb_swi_clk>; + resets =3D <&disp_cc_mdss_core_bcr>; + + power-domains =3D <&mdss_gdsc>; + + iommus =3D <&apps_smmu 0x800 0x2>; + + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@9801000 { + compatible =3D "qcom,kaanapali-dpu"; + reg =3D <0x09801000 0x1c8000>, + <0x09b16000 0x3000>; + reg-names =3D "mdp", + "vbif"; + + interrupts-extended =3D <&mdss 0>; + + clocks =3D <&gcc_disp_hf_axi_clk>, + <&disp_cc_mdss_ahb_clk>, + <&disp_cc_mdss_mdp_lut_clk>, + <&disp_cc_mdss_mdp_clk>, + <&disp_cc_mdss_vsync_clk>; + clock-names =3D "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&disp_cc_mdss_vsync_clk>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + + dpu_intf2_out: endpoint { + remote-endpoint =3D <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-156000000 { + opp-hz =3D /bits/ 64 <156000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + }; + + opp-207000000 { + opp-hz =3D /bits/ 64 <207000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz =3D /bits/ 64 <337000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz =3D /bits/ 64 <417000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz =3D /bits/ 64 <532000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + required-opps =3D <&rpmhpd_opp_nom_l1>; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + }; + }; + + dsi@9ac0000 { + compatible =3D "qcom,kaanapali-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x09ac0000 0x1000>; + reg-names =3D "dsi_ctrl"; + + interrupts-extended =3D <&mdss 4>; + + clocks =3D <&disp_cc_mdss_byte0_clk>, + <&disp_cc_mdss_byte0_intf_clk>, + <&disp_cc_mdss_pclk0_clk>, + <&disp_cc_mdss_esc0_clk>, + <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&disp_cc_esync0_clk>, + <&disp_cc_osc_clk>, + <&disp_cc_mdss_byte0_clk_src>, + <&disp_cc_mdss_pclk0_clk_src>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + remote-endpoint =3D <&panel0_in>; + data-lanes =3D <0 1 2 3>; + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + }; + + opp-250000000 { + opp-hz =3D /bits/ 64 <250000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-312500000 { + opp-hz =3D /bits/ 64 <312500000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@9ac1000 { + compatible =3D "qcom,kaanapali-dsi-phy-3nm"; + reg =3D <0x09ac1000 0x1cc>, + <0x09ac1200 0x80>, + <0x09ac1500 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&disp_cc_mdss_ahb_clk>, + <&rpmhcc RPMH_CXO_CLK>; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4f4ac66a1aasm72500001cf.33.2025.12.22.02.24.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Dec 2025 02:24:56 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com Subject: [PATCH v4 05/11] drm/msm/mdss: Add support for Kaanapali Date: Mon, 22 Dec 2025 18:23:54 +0800 Message-Id: <20251222102400.1109-6-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> References: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: xFkTqVb601CoW0A7KZID7n8cf792_7ic X-Proofpoint-GUID: xFkTqVb601CoW0A7KZID7n8cf792_7ic X-Authority-Analysis: v=2.4 cv=CeEFJbrl c=1 sm=1 tr=0 ts=69491c79 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=hYg4dbXq4j5tZlskCswA:9 a=pJ04lnu7RYOZP9TFuWaZ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA5NCBTYWx0ZWRfX+CpfUjmdHQ2V sfhhJHMFhGpX9O0/Yi5+/tYjuu3WMgOTBQ7Gbw71svvdo6x3GF6G4y+iJNETnDwQN3EHJ44DxmG Xhaxr+QHRkM+Y/7/O7jdE51kBtwHzEeaWZxSXfwi14qFy90U20Uhu2NNbiKyc4fkFFLVFPEqdZ7 P/3D+zxhSpzXkMn9KtDEE0ucB483jXq18HrwW3TRN0rmV1RohPkTm12TwbDFJ9gW4/k0/rDEOgF BRpBwU5UQYGxoIYfYp6hiysvb8MEtwjVjVQNrq4CcqplNH4RexUA9rcXKmaqOXUyJhnfEpk+BNR iICspBEAlqCY+wH1G+eW51LTwDJTmp+rimlXnDtdGT8B9Om68GGb7elssfSEHHsvLPbOtzri8/a 9x19k6JDWpcD5jke/stNNc+jDgiLkGuB1Y6iqPKy9fLmHWI+wZgNFNevxN+7ExpDxRn+9SP3hqg SkQH0dLfQ/LWcu6uNuA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 bulkscore=0 adultscore=0 spamscore=0 clxscore=1015 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220094 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang Add mdss support for the Qualcomm Kaanapali platform. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Signed-off-by: Yuanjie Yang --- drivers/gpu/drm/msm/msm_mdss.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index bf9a33e925ac..7d78d16f8802 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -239,7 +239,11 @@ static void msm_mdss_setup_ubwc_dec_50(struct msm_mdss= *msm_mdss) =20 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); =20 - writel_relaxed(4, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); + if (data->ubwc_dec_version =3D=3D UBWC_6_0) + writel_relaxed(5, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); + else + writel_relaxed(4, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); + writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); } =20 @@ -296,6 +300,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) case UBWC_5_0: msm_mdss_setup_ubwc_dec_50(msm_mdss); break; + case UBWC_6_0: + msm_mdss_setup_ubwc_dec_50(msm_mdss); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4f4ac66a1aasm72500001cf.33.2025.12.22.02.24.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Dec 2025 02:25:04 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, Dmitry Baryshkov Subject: [PATCH v4 06/11] drm/msm/dsi/phy: Add support for Kaanapali Date: Mon, 22 Dec 2025 18:23:55 +0800 Message-Id: <20251222102400.1109-7-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> References: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=SIhPlevH c=1 sm=1 tr=0 ts=69491c81 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=ab5uJhi7KCXt4xzmVoQA:9 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-ORIG-GUID: Fl6Y-F6wTbvlqc41g_-xMkYSf3Fiw3Oh X-Proofpoint-GUID: Fl6Y-F6wTbvlqc41g_-xMkYSf3Fiw3Oh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA5NCBTYWx0ZWRfXwuPV+v2yhYVk tWc4aIK4cs89no3DDo45qMWC4fqJs65yUj/CHes32OQm5dVJw3c6Z4f29VzMSIzmepNdqqZhmln UW+WJM02/5zRPQhk+bnUf2LX8KGB8gUB48VOp6fYL7XoAeh1HM8evjPEWNDmQ7mdIJpwFawV0e6 dEBOdTR+DjixewCwPukytU7iSfoSER+nryMtsCWYP1yl7O4Z3GDh+vrFIZhm9+QFGRhNBXpT2gC HEi4cPScTy83VmyuU2mzCAtavS5qFTUgW6TtR9Khvnk4HxOk/X3uLU9o1LcHXryMqOFdud4PzRJ iGOQCGvKrd/6jAaTG9Ubr/Mc7bbtI+LWh8BUfAJ/VTPYq/zV4iRpltb3JA/TKNNvL/gTKjmk5WE CJ3KzRYYmaAYjcok2D2xx9r59pBXyr8yLaWHNi261PwtwJ0k1XuDj76MTBufXVxLErwKO0hRHK0 mpB25Fku61X+1A/YQMQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 adultscore=0 phishscore=0 spamscore=0 suspectscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220094 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang Add DSI PHY support for the Kaanapali platform, Kaanapali introduce addition of DSI2/DSI2_phy compared to SM8650. However, based on the HPG diagram, only DSI0_phy and DSI1_phy works. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov Signed-off-by: Yuanjie Yang --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 23 +++++++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.c index 4ea681130dba..7937266de1d2 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -577,6 +577,8 @@ static const struct of_device_id dsi_phy_dt_match[] =3D= { .data =3D &dsi_phy_4nm_8650_cfgs }, { .compatible =3D "qcom,sm8750-dsi-phy-3nm", .data =3D &dsi_phy_3nm_8750_cfgs }, + { .compatible =3D "qcom,kaanapali-dsi-phy-3nm", + .data =3D &dsi_phy_3nm_kaanapali_cfgs }, #endif {} }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.h index 3cbf08231492..c01784ca38ed 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -64,6 +64,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_= cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_3nm_kaanapali_cfgs; =20 struct msm_dsi_dphy_timing { u32 clk_zero; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/ms= m/dsi/phy/dsi_phy_7nm.c index c5e1d2016bcc..8cb0db3a9880 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -1504,3 +1504,26 @@ const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs = =3D { .num_dsi_phy =3D 2, .quirks =3D DSI_PHY_7NM_QUIRK_V7_0, }; + +const struct msm_dsi_phy_cfg dsi_phy_3nm_kaanapali_cfgs =3D { + .has_phy_lane =3D true, + .regulator_data =3D dsi_phy_7nm_98000uA_regulators, + .num_regulators =3D ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators), + .ops =3D { + .enable =3D dsi_7nm_phy_enable, + .disable =3D dsi_7nm_phy_disable, + .pll_init =3D dsi_pll_7nm_init, + .save_pll_state =3D dsi_7nm_pll_save_state, + .restore_pll_state =3D dsi_7nm_pll_restore_state, + .set_continuous_clock =3D dsi_7nm_set_continuous_clock, + }, + .min_pll_rate =3D 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate =3D 5000000000UL, +#else + .max_pll_rate =3D ULONG_MAX, +#endif + .io_start =3D { 0x9ac1000, 0x9ac4000 }, + .num_dsi_phy =3D 2, + .quirks =3D DSI_PHY_7NM_QUIRK_V7_0, +}; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4f4ac66a1aasm72500001cf.33.2025.12.22.02.25.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Dec 2025 02:25:12 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, Dmitry Baryshkov Subject: [PATCH v4 07/11] drm/msm/dsi: Add support for Kaanapali Date: Mon, 22 Dec 2025 18:23:56 +0800 Message-Id: <20251222102400.1109-8-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> References: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: Xs08pwUqk0RrzOFvE0ULCOrNuG_tjqbE X-Authority-Analysis: v=2.4 cv=EvnfbCcA c=1 sm=1 tr=0 ts=69491c89 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=EGddA7oXPexY6v9tJfMA:9 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-GUID: Xs08pwUqk0RrzOFvE0ULCOrNuG_tjqbE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA5NCBTYWx0ZWRfX9hiHWrgp45ca 1Hsq0cJNMR8kLAy3+7B5tG66bR6yq8Q5hJjOV5jt0dw8bBhRx8BUMvu2lh+3SMoa2uw8VUJ3qXg VZ6AxefsgBqxmvtog9faoZLaF46y1Xc4zSEQB5MWLDRO/54/c0OzfPnzD7kSDcNVK96fVdLdzcb p50twUPk8DeE8nUq76cqPDWz4kSoaAOLgJXstermp0Atzi6PcMVxz+ZZSwGsKy0XtZCxoVjE2+t S0qpF2Ixonn8pYuvlDbHvqoNJXutiK1wBPEK5PIdphLe8Eu2yHlXyW5hbC2A709DAG4nOnnVVMv 2VNGFEBfs7+pgQR+xk9Pity0k9jkEd07bOpyOYY7PEbDQLkPos00M/RbSVHf+AIBoMdqxMiV8Zg ZFLZhqFwouPvKstriO/XZvM/RkXyFXLvvYZheirQKNDW99vMKSV3wOLj/qqeBLrMmuwgTuwmmSA XhfogUV/w4DevD1sR4A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 phishscore=0 adultscore=0 clxscore=1015 priorityscore=1501 spamscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220094 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang Add DSI Controller version 2.10.0 support for DSI on Qualcomm Kaanapali SoC. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov Signed-off-by: Yuanjie Yang --- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 13 +++++++++++++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/ds= i_cfg.c index fed8e9b67011..bd3c51c350e7 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -205,6 +205,17 @@ static const struct msm_dsi_config sm8650_dsi_cfg =3D { }, }; =20 +static const struct msm_dsi_config kaanapali_dsi_cfg =3D { + .io_offset =3D DSI_6G_REG_SHIFT, + .regulator_data =3D sm8650_dsi_regulators, + .num_regulators =3D ARRAY_SIZE(sm8650_dsi_regulators), + .bus_clk_names =3D dsi_v2_4_clk_names, + .num_bus_clks =3D ARRAY_SIZE(dsi_v2_4_clk_names), + .io_start =3D { + { 0x9ac0000, 0x9ac3000 }, + }, +}; + static const struct regulator_bulk_data sc7280_dsi_regulators[] =3D { { .supply =3D "vdda", .init_load_uA =3D 8350 }, /* 1.2 V */ { .supply =3D "refgen" }, @@ -332,6 +343,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handler= s[] =3D { &sm8650_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_9_0, &sm8650_dsi_cfg, &msm_dsi_6g_v2_9_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_10_0, + &kaanapali_dsi_cfg, &msm_dsi_6g_v2_9_host_ops}, }; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4f4ac66a1aasm72500001cf.33.2025.12.22.02.25.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Dec 2025 02:25:20 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, Dmitry Baryshkov Subject: [PATCH v4 08/11] drm/msm/dpu: Add interrupt registers for DPU 13.0.0 Date: Mon, 22 Dec 2025 18:23:57 +0800 Message-Id: <20251222102400.1109-9-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> References: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=SIhPlevH c=1 sm=1 tr=0 ts=69491c91 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=RfJNy9JZAWTFlj1jTG0A:9 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-ORIG-GUID: SzOMsfEz39QQA1c5BVRl94D2ouUctnz8 X-Proofpoint-GUID: SzOMsfEz39QQA1c5BVRl94D2ouUctnz8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA5NCBTYWx0ZWRfXztLEegj7DJ4I /F7KzkiFekEmfCG1sIp3X7zbdtZzXZuHvcQiEVsY+RcDjm4FbRd/UW4eRCz2P7Hv5U6zpqXRmQF YCNlx21bmLRn5+zJSSvgaRRkvqM7dWzfVi88/COUgpZIP1g+Q/6ySrDUJd2AXoh4jzJ0CWHLNzi E3NXBBK9DtgZV2blZ5nEzuTJ+F8RA8Ic4Gtp+vRYVDwEyQjTbhzGih2FKxoff9xahnQrB36jQGb EG6FAvtrD3ldS9VmxrZUxyZW06DrFJDPw222OsVhHWbDGyvTofzrFUIobPqTPH2y10HRTZRokOm xG1bsqqFe85DjsHRQ4vQjx099QVCvIpG02a1HqtAEPAOPvNFucE/nWPEslBhf5/WSgOjg1w/9Ch l4FIxlXuRbMxSsAv5LDDKqSDp5DJou+0ltCuKQhJMZPM0c9CB0I3x6ohlzkqbe0JIJjmp0zbRVP TmJ2YkK1oNE9KRYRKmg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 adultscore=0 phishscore=0 spamscore=0 suspectscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220094 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang DPU version 13.0.0 introduces changes to the interrupt register layout. Update the driver to support these modifications for proper interrupt handling. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov Signed-off-by: Yuanjie Yang --- .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 89 ++++++++++++++++++- 1 file changed, 88 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gp= u/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 49bd77a755aa..5b7cd5241f45 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -40,6 +40,15 @@ #define MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(intf) (MDP_INTF_REV_7xxx_TEAR_O= FF(intf) + 0x004) #define MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(intf) (MDP_INTF_REV_7xxx_TEAR_O= FF(intf) + 0x008) =20 +#define MDP_INTF_REV_13xx_OFF(intf) (0x18d000 + 0x1000 * (intf)) +#define MDP_INTF_REV_13xx_INTR_EN(intf) (MDP_INTF_REV_13xx_OFF(intf) + 0= x1c0) +#define MDP_INTF_REV_13xx_INTR_STATUS(intf) (MDP_INTF_REV_13xx_OFF(intf) = + 0x1c4) +#define MDP_INTF_REV_13xx_INTR_CLEAR(intf) (MDP_INTF_REV_13xx_OFF(intf) += 0x1c8) +#define MDP_INTF_REV_13xx_TEAR_OFF(intf) (0x18d800 + 0x1000 * (intf)) +#define MDP_INTF_REV_13xx_INTR_TEAR_EN(intf) (MDP_INTF_REV_13xx_TEAR_OFF(= intf) + 0x000) +#define MDP_INTF_REV_13xx_INTR_TEAR_STATUS(intf) (MDP_INTF_REV_13xx_TEAR_O= FF(intf) + 0x004) +#define MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(intf) (MDP_INTF_REV_13xx_TEAR_O= FF(intf) + 0x008) + /** * struct dpu_intr_reg - array of DPU register sets * @clr_off: offset to CLEAR reg @@ -199,6 +208,82 @@ static const struct dpu_intr_reg dpu_intr_set_7xxx[] = =3D { }, }; =20 +/* + * dpu_intr_set_13xx - List of DPU interrupt registers for DPU >=3D 13.0 + */ +static const struct dpu_intr_reg dpu_intr_set_13xx[] =3D { + [MDP_SSPP_TOP0_INTR] =3D { + INTR_CLEAR, + INTR_EN, + INTR_STATUS + }, + [MDP_SSPP_TOP0_INTR2] =3D { + INTR2_CLEAR, + INTR2_EN, + INTR2_STATUS + }, + [MDP_SSPP_TOP0_HIST_INTR] =3D { + HIST_INTR_CLEAR, + HIST_INTR_EN, + HIST_INTR_STATUS + }, + [MDP_INTF0_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(0), + MDP_INTF_REV_13xx_INTR_EN(0), + MDP_INTF_REV_13xx_INTR_STATUS(0) + }, + [MDP_INTF1_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(1), + MDP_INTF_REV_13xx_INTR_EN(1), + MDP_INTF_REV_13xx_INTR_STATUS(1) + }, + [MDP_INTF1_TEAR_INTR] =3D { + MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(1), + MDP_INTF_REV_13xx_INTR_TEAR_EN(1), + MDP_INTF_REV_13xx_INTR_TEAR_STATUS(1) + }, + [MDP_INTF2_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(2), + MDP_INTF_REV_13xx_INTR_EN(2), + MDP_INTF_REV_13xx_INTR_STATUS(2) + }, + [MDP_INTF2_TEAR_INTR] =3D { + MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(2), + MDP_INTF_REV_13xx_INTR_TEAR_EN(2), + MDP_INTF_REV_13xx_INTR_TEAR_STATUS(2) + }, + [MDP_INTF3_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(3), + MDP_INTF_REV_13xx_INTR_EN(3), + MDP_INTF_REV_13xx_INTR_STATUS(3) + }, + [MDP_INTF4_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(4), + MDP_INTF_REV_13xx_INTR_EN(4), + MDP_INTF_REV_13xx_INTR_STATUS(4) + }, + [MDP_INTF5_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(5), + MDP_INTF_REV_13xx_INTR_EN(5), + MDP_INTF_REV_13xx_INTR_STATUS(5) + }, + [MDP_INTF6_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(6), + MDP_INTF_REV_13xx_INTR_EN(6), + MDP_INTF_REV_13xx_INTR_STATUS(6) + }, + [MDP_INTF7_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(7), + MDP_INTF_REV_13xx_INTR_EN(7), + MDP_INTF_REV_13xx_INTR_STATUS(7) + }, + [MDP_INTF8_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(8), + MDP_INTF_REV_13xx_INTR_EN(8), + MDP_INTF_REV_13xx_INTR_STATUS(8) + }, +}; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4f4ac66a1aasm72500001cf.33.2025.12.22.02.25.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Dec 2025 02:25:28 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com Subject: [PATCH v4 09/11] drm/msm/dpu: Refactor SSPP to compatible DPU 13.0.0 Date: Mon, 22 Dec 2025 18:23:58 +0800 Message-Id: <20251222102400.1109-10-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> References: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: TXA2t86AN-LPnZ1E7ic6XSgPg2vQuaGx X-Authority-Analysis: v=2.4 cv=cuuWUl4i c=1 sm=1 tr=0 ts=69491c99 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=BvZMC-lIEGFodKGY4bQA:9 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA5NCBTYWx0ZWRfX5BChLNCTwDIA T+5gVzj8A+MPdb6FtydWNv3RPiZMEW4E/Sy3sWflik/GDpgpFMp28N9tcYiP6/3LjDP0Y4mN4+7 aRkTGx3u9emZpjdShjfbYgXHnKJuo4uOyaO/JniqyppzowF4c7T4a7lnMxrHxgEg45OCoG3CQ3/ 7EOYIP/G/tp/MMZEKOcU3cuUXnWnVgQ43dTdFPMOMUqb0tn755YA/BYH1+rijFKFyh41JHLP28w B06AyjzURG+y63EyoenHhZxOkIYRTnB/jGYhPl0k8pAw4LbWArjy9UuSp/R385LZfnhMupnbCXr n4mOe3Ld3aLOJvO2ESaJdrwpSDvV/aKq8XWp84F3WvLGxV2oqUm1jyzEp/gqjixdoJqaZFr2x53 wQabrH7KI5yTDapl9e/z7pkSrCwlT07qNKOW9ngEG3pK3rbkeaTlL9NWev8KwnwHjIBdAFQu/1c Cz9PbVerr4MrjPAi26w== X-Proofpoint-GUID: TXA2t86AN-LPnZ1E7ic6XSgPg2vQuaGx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 priorityscore=1501 spamscore=0 bulkscore=0 suspectscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220094 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang DPU version 13.0.0 introduces structural changes including register additions, removals, and relocations. Refactor SSPP-related code to be compatible with DPU 13.0.0 modifications. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Signed-off-by: Yuanjie Yang --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 14 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 110 ++++++++++-------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 52 +++++++++ 3 files changed, 130 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 336757103b5a..b03fea1b9cbd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -208,6 +208,18 @@ struct dpu_dsc_blk { u32 len; }; =20 +/** + * struct dpu_sspp_v13_rec_blk - SSPP REC sub-blk information + * @name: string name for debug purposes + * @base: offset of this sub-block relative to the block offset + * @len: register block length of this sub-block + */ +struct dpu_sspp_v13_rec_blk { + char name[DPU_HW_BLK_NAME_LEN]; + u32 base; + u32 len; +}; + /** * enum dpu_qos_lut_usage - define QoS LUT use cases */ @@ -294,6 +306,8 @@ struct dpu_sspp_sub_blks { u32 qseed_ver; struct dpu_scaler_blk scaler_blk; struct dpu_pp_blk csc_blk; + struct dpu_sspp_v13_rec_blk sspp_rec0_blk; + struct dpu_sspp_v13_rec_blk sspp_rec1_blk; =20 const u32 *format_list; u32 num_formats; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.c index 6f1fc790ad6d..197a2c584c73 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -145,11 +145,18 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe) { struct dpu_hw_sspp *ctx =3D pipe->sspp; - u32 mode_mask; =20 if (!ctx) return; =20 + dpu_hw_setup_multirect_impl(pipe, ctx, SSPP_MULTIRECT_OPMODE); +} + +void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe, + struct dpu_hw_sspp *ctx, u32 op_mode_off) +{ + u32 mode_mask; + if (pipe->multirect_index =3D=3D DPU_SSPP_RECT_SOLO) { /** * if rect index is RECT_SOLO, we cannot expect a @@ -158,7 +165,7 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_p= ipe *pipe) */ mode_mask =3D 0; } else { - mode_mask =3D DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE); + mode_mask =3D DPU_REG_READ(&ctx->hw, op_mode_off); mode_mask |=3D pipe->multirect_index; if (pipe->multirect_mode =3D=3D DPU_SSPP_MULTIRECT_TIME_MX) mode_mask |=3D BIT(2); @@ -166,10 +173,10 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw= _pipe *pipe) mode_mask &=3D ~BIT(2); } =20 - DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE, mode_mask); + DPU_REG_WRITE(&ctx->hw, op_mode_off, mode_mask); } =20 -static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx, +void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx, u32 mask, u8 en) { const struct dpu_sspp_sub_blks *sblk =3D ctx->cap->sblk; @@ -189,7 +196,7 @@ static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx, DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode); } =20 -static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, +void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, u32 mask, u8 en) { const struct dpu_sspp_sub_blks *sblk =3D ctx->cap->sblk; @@ -211,10 +218,6 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pip= e *pipe, const struct msm_format *fmt, u32 flags) { struct dpu_hw_sspp *ctx =3D pipe->sspp; - struct dpu_hw_blk_reg_map *c; - u32 chroma_samp, unpack, src_format; - u32 opmode =3D 0; - u32 fast_clear =3D 0; u32 op_mode_off, unpack_pat_off, format_off; =20 if (!ctx || !fmt) @@ -231,6 +234,21 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pip= e *pipe, format_off =3D SSPP_SRC_FORMAT_REC1; } =20 + dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off, + unpack_pat_off, format_off, + SSPP_UBWC_STATIC_CTRL, SSPP_UBWC_ERROR_STATUS); +} + +void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_f= ormat *fmt, + u32 flags, struct dpu_hw_sspp *ctx, u32 op_mode_off, + u32 unpack_pat_off, u32 format_off, u32 ubwc_ctrl_off, + u32 ubwc_err_off) +{ + struct dpu_hw_blk_reg_map *c; + u32 chroma_samp, unpack, src_format; + u32 opmode; + u32 fast_clear; + c =3D &ctx->hw; opmode =3D DPU_REG_READ(c, op_mode_off); opmode &=3D ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD | @@ -279,24 +297,24 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pi= pe *pipe, switch (ctx->ubwc->ubwc_enc_version) { case UBWC_1_0: fast_clear =3D fmt->alpha_enable ? BIT(31) : 0; - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, + DPU_REG_WRITE(c, ubwc_ctrl_off, fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) | BIT(8) | (ctx->ubwc->highest_bank_bit << 4)); break; case UBWC_2_0: fast_clear =3D fmt->alpha_enable ? BIT(31) : 0; - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, + DPU_REG_WRITE(c, ubwc_ctrl_off, fast_clear | (ctx->ubwc->ubwc_swizzle) | (ctx->ubwc->highest_bank_bit << 4)); break; case UBWC_3_0: - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, + DPU_REG_WRITE(c, ubwc_ctrl_off, BIT(30) | (ctx->ubwc->ubwc_swizzle) | (ctx->ubwc->highest_bank_bit << 4)); break; case UBWC_4_0: - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, + DPU_REG_WRITE(c, ubwc_ctrl_off, MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30)); break; } @@ -313,10 +331,10 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pi= pe *pipe, =20 /* update scaler opmode, if appropriate */ if (test_bit(DPU_SSPP_CSC, &ctx->cap->features)) - _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT, + dpu_hw_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT, MSM_FORMAT_IS_YUV(fmt)); else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) - _sspp_setup_csc10_opmode(ctx, + dpu_hw_sspp_setup_csc10_opmode(ctx, VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT, MSM_FORMAT_IS_YUV(fmt)); =20 @@ -325,7 +343,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe= *pipe, DPU_REG_WRITE(c, op_mode_off, opmode); =20 /* clear previous UBWC error */ - DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31)); + DPU_REG_WRITE(c, ubwc_err_off, BIT(31)); } =20 static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx, @@ -385,7 +403,7 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_s= spp *ctx, tot_req_pixels[3]); } =20 -static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, +void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, struct dpu_hw_scaler3_cfg *scaler3_cfg, const struct msm_format *format) { @@ -405,15 +423,11 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pip= e *pipe, struct dpu_sw_pipe_cfg *cfg) { struct dpu_hw_sspp *ctx =3D pipe->sspp; - struct dpu_hw_blk_reg_map *c; - u32 src_size, src_xy, dst_size, dst_xy; u32 src_size_off, src_xy_off, out_size_off, out_xy_off; =20 if (!ctx || !cfg) return; =20 - c =3D &ctx->hw; - if (pipe->multirect_index =3D=3D DPU_SSPP_RECT_SOLO || pipe->multirect_index =3D=3D DPU_SSPP_RECT_0) { src_size_off =3D SSPP_SRC_SIZE; @@ -427,20 +441,8 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe= *pipe, out_xy_off =3D SSPP_OUT_XY_REC1; } =20 - - /* src and dest rect programming */ - src_xy =3D (cfg->src_rect.y1 << 16) | cfg->src_rect.x1; - src_size =3D (drm_rect_height(&cfg->src_rect) << 16) | - drm_rect_width(&cfg->src_rect); - dst_xy =3D (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1; - dst_size =3D (drm_rect_height(&cfg->dst_rect) << 16) | - drm_rect_width(&cfg->dst_rect); - - /* rectangle register programming */ - DPU_REG_WRITE(c, src_size_off, src_size); - DPU_REG_WRITE(c, src_xy_off, src_xy); - DPU_REG_WRITE(c, out_size_off, dst_size); - DPU_REG_WRITE(c, out_xy_off, dst_xy); + dpu_hw_setup_rects_impl(pipe, cfg, ctx, src_size_off, + src_xy_off, out_size_off, out_xy_off); } =20 static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe, @@ -497,7 +499,7 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_= sw_pipe *pipe, DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1, ystride1); } =20 -static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, +void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, const struct dpu_csc_cfg *data) { u32 offset; @@ -519,21 +521,31 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp = *ctx, static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 colo= r) { struct dpu_hw_sspp *ctx =3D pipe->sspp; - struct dpu_hw_fmt_layout cfg; + u32 const_clr_off; =20 if (!ctx) return; =20 + if (pipe->multirect_index =3D=3D DPU_SSPP_RECT_SOLO || + pipe->multirect_index =3D=3D DPU_SSPP_RECT_0) + const_clr_off =3D SSPP_SRC_CONSTANT_COLOR; + else + const_clr_off =3D SSPP_SRC_CONSTANT_COLOR_REC1; + + dpu_hw_setup_solidfill_impl(pipe, color, ctx, const_clr_off); +} + +void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe, + u32 color, struct dpu_hw_sspp *ctx, + u32 const_clr_off) +{ + struct dpu_hw_fmt_layout cfg; + /* cleanup source addresses */ memset(&cfg, 0, sizeof(cfg)); ctx->ops.setup_sourceaddress(pipe, &cfg); =20 - if (pipe->multirect_index =3D=3D DPU_SSPP_RECT_SOLO || - pipe->multirect_index =3D=3D DPU_SSPP_RECT_0) - DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR, color); - else - DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1, - color); + DPU_REG_WRITE(&ctx->hw, const_clr_off, color); } =20 static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx, @@ -547,14 +559,20 @@ static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_s= spp *ctx, cfg); } =20 +void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx, + bool danger_safe_en, u32 ctrl_off) +{ + DPU_REG_WRITE(&ctx->hw, ctrl_off, + danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0); +} + static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx, bool danger_safe_en) { if (!ctx) return; =20 - DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL, - danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0); + dpu_hw_sspp_setup_qos_ctrl_impl(ctx, danger_safe_en, SSPP_QOS_CTRL); } =20 static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe, @@ -609,7 +627,7 @@ static void _setup_layer_ops(struct dpu_hw_sspp *c, c->ops.setup_multirect =3D dpu_hw_sspp_setup_multirect; =20 if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features)) - c->ops.setup_scaler =3D _dpu_hw_sspp_setup_scaler3; + c->ops.setup_scaler =3D dpu_hw_sspp_setup_scaler3; =20 if (test_bit(DPU_SSPP_CDP, &features)) c->ops.setup_cdp =3D dpu_hw_sspp_setup_cdp; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.h index bdac5c04bf79..c6b19cb4d158 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -331,5 +331,57 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device= *dev, int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms = *kms, struct dentry *entry); =20 +void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx, + u32 mask, u8 en); + +void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, + u32 mask, u8 en); + +void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, + struct dpu_hw_scaler3_cfg *scaler3_cfg, + const struct msm_format *format); + +void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, + const struct dpu_csc_cfg *data); + +void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe, + struct dpu_hw_sspp *ctx, + u32 op_mode_off); + +void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_f= ormat *fmt, + u32 flags, struct dpu_hw_sspp *ctx, + u32 op_mode_off, u32 unpack_pat_off, u32 format_off, + u32 ubwc_ctrl_off, u32 ubwc_err_off); + +static inline void dpu_hw_setup_rects_impl(struct dpu_sw_pipe *pipe, struc= t dpu_sw_pipe_cfg *cfg, + struct dpu_hw_sspp *ctx, u32 src_size_off, + u32 src_xy_off, u32 out_size_off, u32 out_xy_off) +{ + struct dpu_hw_blk_reg_map *c; + u32 src_size, src_xy, dst_size, dst_xy; + + c =3D &ctx->hw; + + /* src and dest rect programming */ + src_xy =3D (cfg->src_rect.y1 << 16) | cfg->src_rect.x1; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4f4ac66a1aasm72500001cf.33.2025.12.22.02.25.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Dec 2025 02:25:35 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com Subject: [PATCH v4 10/11] drm/msm/dpu: Add Kaanapali SSPP sub-block support Date: Mon, 22 Dec 2025 18:23:59 +0800 Message-Id: <20251222102400.1109-11-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> References: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=ELgLElZC c=1 sm=1 tr=0 ts=69491ca1 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=IoldKcXwaph4SihcyF8A:9 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA5NCBTYWx0ZWRfX/VnOE/Y90V4r PfuQCe/zi548CgcWL2S0dyuXv6tIwVskHZ5c5bDNvNM0fcbXoygD0/0JZNSyd+0tidFdcGsQ78K hgiKhzV1sS3of85vjA1Doex+YJEXa7rOic7MH9a8tMC00K6mdWcfZQCOo5Df2XnEXe2ZvPc4g35 PyIuwRNYhztJVDGgrkln2EY0jNv3rZ0haPpSBXOCzwQIoU7zniewzohDjWvaWa7hOtWxw2TrAUc fQzjT8WRr11Xn2JJPJTClNEUqsNSSzBt7H9eJ0TYSsfC3J8Zwx80Z3jAitQl0LfC7FMjdqf/saz BcdOsdE1EXn1sJgtKT03tG9uoJU6DcCA6PZoo9OY9WSUgqRLrK4GyRiU7BuEDz1L2Op8zpdkrVX WhfYYaiPSdNBuipRhAfdPQIh9CL6DJ2oq8DYTOnbpJvkFFNxNUQfOLfy6jJlmovoAoe/+NBvNhG ZwPmCt9N0Y+CLa9LXzA== X-Proofpoint-GUID: 0zb3jTPXkmpqsguzsJnEwP-w4lveQ6ko X-Proofpoint-ORIG-GUID: 0zb3jTPXkmpqsguzsJnEwP-w4lveQ6ko X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 spamscore=0 phishscore=0 impostorscore=0 suspectscore=0 adultscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220094 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang Add support for Kaanapali platform SSPP sub-blocks, which introduce structural changes including register additions, removals, and relocations. Add the new common and rectangle blocks, and update register definitions and handling to ensure compatibility with DPU v13.0. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Signed-off-by: Yuanjie Yang --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 13 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 4 + .../gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c | 321 ++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 18 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 17 +- 7 files changed, 371 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 8aa7d07303fb..8b94c5f1cb68 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -86,6 +86,7 @@ msm-display-$(CONFIG_DRM_MSM_DPU) +=3D \ disp/dpu1/dpu_hw_lm.o \ disp/dpu1/dpu_hw_pingpong.o \ disp/dpu1/dpu_hw_sspp.o \ + disp/dpu1/dpu_hw_sspp_v13.o \ disp/dpu1/dpu_hw_dspp.o \ disp/dpu1/dpu_hw_merge3d.o \ disp/dpu1/dpu_hw_top.o \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.c index 197a2c584c73..c6d8d7fb3880 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -248,6 +248,7 @@ void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe,= const struct msm_format u32 chroma_samp, unpack, src_format; u32 opmode; u32 fast_clear; + u8 core_major_ver =3D ctx->mdss_ver->core_major_ver; =20 c =3D &ctx->hw; opmode =3D DPU_REG_READ(c, op_mode_off); @@ -291,9 +292,10 @@ void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe= , const struct msm_format if (MSM_FORMAT_IS_UBWC(fmt)) opmode |=3D MDSS_MDP_OP_BWC_EN; src_format |=3D (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */ - DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, - DPU_FETCH_CONFIG_RESET_VALUE | - ctx->ubwc->highest_bank_bit << 18); + if (core_major_ver < 13) + DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, + DPU_FETCH_CONFIG_RESET_VALUE | + ctx->ubwc->highest_bank_bit << 18); switch (ctx->ubwc->ubwc_enc_version) { case UBWC_1_0: fast_clear =3D fmt->alpha_enable ? BIT(31) : 0; @@ -724,7 +726,10 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device= *dev, =20 hw_pipe->mdss_ver =3D mdss_rev; =20 - _setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev); + if (mdss_rev->core_major_ver >=3D 13) + dpu_hw_sspp_init_v13(hw_pipe, hw_pipe->cap->features, mdss_rev); + else + _setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev); =20 return hw_pipe; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.h index c6b19cb4d158..309af4183ba3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -383,5 +383,9 @@ void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pi= pe, void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx, bool danger_safe_en, u32 ctrl_off); =20 +void dpu_hw_sspp_init_v13(struct dpu_hw_sspp *c, + unsigned long features, + const struct dpu_mdss_version *mdss_rev); + #endif /*_DPU_HW_SSPP_H */ =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c b/drivers/gpu/= drm/msm/disp/dpu1/dpu_hw_sspp_v13.c new file mode 100644 index 000000000000..e78a20b45300 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +#include "dpu_hw_sspp.h" + +/* >=3D v13 DPU */ +/* CMN Registers -> Source Surface Processing Pipe Common SSPP registers */ +/* Name Offset */ +#define SSPP_CMN_CLK_CTRL 0x0 +#define SSPP_CMN_CLK_STATUS 0x4 +#define SSPP_CMN_MULTI_REC_OP_MODE 0x10 +#define SSPP_CMN_ADDR_CONFIG 0x14 +#define SSPP_CMN_CAC_CTRL 0x20 +#define SSPP_CMN_SYS_CACHE_MODE 0x24 +#define SSPP_CMN_QOS_CTRL 0x28 + +#define SSPP_CMN_FILL_LEVEL_SCALE 0x3c +#define SSPP_CMN_FILL_LEVELS 0x40 +#define SSPP_CMN_STATUS 0x44 +#define SSPP_CMN_FETCH_DMA_RD_OTS 0x48 +#define SSPP_CMN_FETCH_DTB_WR_PLANE0 0x4c +#define SSPP_CMN_FETCH_DTB_WR_PLANE1 0x50 +#define SSPP_CMN_FETCH_DTB_WR_PLANE2 0x54 +#define SSPP_CMN_DTB_UNPACK_RD_PLANE0 0x58 +#define SSPP_CMN_DTB_UNPACK_RD_PLANE1 0x5c +#define SSPP_CMN_DTB_UNPACK_RD_PLANE2 0x60 +#define SSPP_CMN_UNPACK_LINE_COUNT 0x64 +#define SSPP_CMN_TPG_CONTROL 0x68 +#define SSPP_CMN_TPG_CONFIG 0x6c +#define SSPP_CMN_TPG_COMPONENT_LIMITS 0x70 +#define SSPP_CMN_TPG_RECTANGLE 0x74 +#define SSPP_CMN_TPG_BLACK_WHITE_PATTERN_FRAMES 0x78 +#define SSPP_CMN_TPG_RGB_MAPPING 0x7c +#define SSPP_CMN_TPG_PATTERN_GEN_INIT_VAL 0x80 + +/*RECRegisterset*/ +/*Name Offset*/ +#define SSPP_REC_SRC_FORMAT 0x0 +#define SSPP_REC_SRC_UNPACK_PATTERN 0x4 +#define SSPP_REC_SRC_OP_MODE 0x8 +#define SSPP_REC_SRC_CONSTANT_COLOR 0xc +#define SSPP_REC_SRC_IMG_SIZE 0x10 +#define SSPP_REC_SRC_SIZE 0x14 +#define SSPP_REC_SRC_XY 0x18 +#define SSPP_REC_OUT_SIZE 0x1c +#define SSPP_REC_OUT_XY 0x20 +#define SSPP_REC_SW_PIX_EXT_LR 0x24 +#define SSPP_REC_SW_PIX_EXT_TB 0x28 +#define SSPP_REC_SRC_SIZE_ODX 0x30 +#define SSPP_REC_SRC_XY_ODX 0x34 +#define SSPP_REC_OUT_SIZE_ODX 0x38 +#define SSPP_REC_OUT_XY_ODX 0x3c +#define SSPP_REC_SW_PIX_EXT_LR_ODX 0x40 +#define SSPP_REC_SW_PIX_EXT_TB_ODX 0x44 +#define SSPP_REC_PRE_DOWN_SCALE 0x48 +#define SSPP_REC_SRC0_ADDR 0x4c +#define SSPP_REC_SRC1_ADDR 0x50 +#define SSPP_REC_SRC2_ADDR 0x54 +#define SSPP_REC_SRC3_ADDR 0x58 +#define SSPP_REC_SRC_YSTRIDE0 0x5c +#define SSPP_REC_SRC_YSTRIDE1 0x60 +#define SSPP_REC_CURRENT_SRC0_ADDR 0x64 +#define SSPP_REC_CURRENT_SRC1_ADDR 0x68 +#define SSPP_REC_CURRENT_SRC2_ADDR 0x6c +#define SSPP_REC_CURRENT_SRC3_ADDR 0x70 +#define SSPP_REC_SRC_ADDR_SW_STATUS 0x74 +#define SSPP_REC_CDP_CNTL 0x78 +#define SSPP_REC_TRAFFIC_SHAPER 0x7c +#define SSPP_REC_TRAFFIC_SHAPER_PREFILL 0x80 +#define SSPP_REC_PD_MEM_ALLOC 0x84 +#define SSPP_REC_QOS_CLAMP 0x88 +#define SSPP_REC_UIDLE_CTRL_VALUE 0x8c +#define SSPP_REC_UBWC_STATIC_CTRL 0x90 +#define SSPP_REC_UBWC_STATIC_CTRL_OVERRIDE 0x94 +#define SSPP_REC_UBWC_STATS_ROI 0x98 +#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI0 0x9c +#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI0 0xa0 +#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI1 0xa4 +#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI1 0xa8 +#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI2 0xac +#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI2 0xb0 +#define SSPP_REC_EXCL_REC_CTRL 0xb4 +#define SSPP_REC_EXCL_REC_SIZE 0xb8 +#define SSPP_REC_EXCL_REC_XY 0xbc +#define SSPP_REC_LINE_INSERTION_CTRL 0xc0 +#define SSPP_REC_LINE_INSERTION_OUT_SIZE 0xc4 +#define SSPP_REC_FETCH_PIPE_ACTIVE 0xc8 +#define SSPP_REC_META_ERROR_STATUS 0xcc +#define SSPP_REC_UBWC_ERROR_STATUS 0xd0 +#define SSPP_REC_FLUSH_CTRL 0xd4 +#define SSPP_REC_INTR_EN 0xd8 +#define SSPP_REC_INTR_STATUS 0xdc +#define SSPP_REC_INTR_CLEAR 0xe0 +#define SSPP_REC_HSYNC_STATUS 0xe4 +#define SSPP_REC_FP16_CONFIG 0x150 +#define SSPP_REC_FP16_CSC_MATRIX_COEFF_R_0 0x154 +#define SSPP_REC_FP16_CSC_MATRIX_COEFF_R_1 0x158 +#define SSPP_REC_FP16_CSC_MATRIX_COEFF_G_0 0x15c +#define SSPP_REC_FP16_CSC_MATRIX_COEFF_G_1 0x160 +#define SSPP_REC_FP16_CSC_MATRIX_COEFF_B_0 0x164 +#define SSPP_REC_FP16_CSC_MATRIX_COEFF_B_1 0x168 +#define SSPP_REC_FP16_CSC_PRE_CLAMP_R 0x16c +#define SSPP_REC_FP16_CSC_PRE_CLAMP_G 0x170 +#define SSPP_REC_FP16_CSC_PRE_CLAMP_B 0x174 +#define SSPP_REC_FP16_CSC_POST_CLAMP 0x178 + +static inline u32 dpu_hw_sspp_calculate_rect_off(enum dpu_sspp_multirect_i= ndex rect_index, + struct dpu_hw_sspp *ctx) +{ + return (rect_index =3D=3D DPU_SSPP_RECT_SOLO || rect_index =3D=3D DPU_SSP= P_RECT_0) ? + ctx->cap->sblk->sspp_rec0_blk.base : ctx->cap->sblk->sspp_rec1_blk.base; +} + +static void dpu_hw_sspp_setup_multirect_v13(struct dpu_sw_pipe *pipe) +{ + struct dpu_hw_sspp *ctx =3D pipe->sspp; + + if (!ctx) + return; + + dpu_hw_setup_multirect_impl(pipe, ctx, SSPP_CMN_MULTI_REC_OP_MODE); +} + +static void dpu_hw_sspp_setup_format_v13(struct dpu_sw_pipe *pipe, + const struct msm_format *fmt, u32 flags) +{ + struct dpu_hw_sspp *ctx =3D pipe->sspp; + u32 op_mode_off, unpack_pat_off, format_off; + u32 ubwc_ctrl_off, ubwc_err_off; + u32 offset; + + if (!ctx || !fmt) + return; + + offset =3D dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx); + + op_mode_off =3D offset + SSPP_REC_SRC_OP_MODE; + unpack_pat_off =3D offset + SSPP_REC_SRC_UNPACK_PATTERN; + format_off =3D offset + SSPP_REC_SRC_FORMAT; + ubwc_ctrl_off =3D offset + SSPP_REC_UBWC_STATIC_CTRL; + ubwc_err_off =3D offset + SSPP_REC_UBWC_ERROR_STATUS; + + dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off, + unpack_pat_off, format_off, ubwc_ctrl_off, ubwc_err_off); +} + +static void dpu_hw_sspp_setup_pe_config_v13(struct dpu_hw_sspp *ctx, + struct dpu_hw_pixel_ext *pe_ext) +{ + struct dpu_hw_blk_reg_map *c; + u8 color; + u32 lr_pe[4], tb_pe[4]; + const u32 bytemask =3D 0xff; + u32 offset =3D ctx->cap->sblk->sspp_rec0_blk.base; + + if (!ctx || !pe_ext) + return; + + c =3D &ctx->hw; + /* program SW pixel extension override for all pipes*/ + for (color =3D 0; color < DPU_MAX_PLANES; color++) { + /* color 2 has the same set of registers as color 1 */ + if (color =3D=3D 2) + continue; + + lr_pe[color] =3D ((pe_ext->right_ftch[color] & bytemask) << 24) | + ((pe_ext->right_rpt[color] & bytemask) << 16) | + ((pe_ext->left_ftch[color] & bytemask) << 8) | + (pe_ext->left_rpt[color] & bytemask); + + tb_pe[color] =3D ((pe_ext->btm_ftch[color] & bytemask) << 24) | + ((pe_ext->btm_rpt[color] & bytemask) << 16) | + ((pe_ext->top_ftch[color] & bytemask) << 8) | + (pe_ext->top_rpt[color] & bytemask); + } + + /* color 0 */ + DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_LR + offset, lr_pe[0]); + DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_TB + offset, tb_pe[0]); + + /* color 1 and color 2 */ + DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_LR_ODX + offset, lr_pe[1]); + DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_TB_ODX + offset, tb_pe[1]); +} + +static void dpu_hw_sspp_setup_rects_v13(struct dpu_sw_pipe *pipe, + struct dpu_sw_pipe_cfg *cfg) +{ + struct dpu_hw_sspp *ctx =3D pipe->sspp; + u32 src_size_off, src_xy_off, out_size_off, out_xy_off; + u32 offset; + + if (!ctx || !cfg) + return; + + offset =3D dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx); + + src_size_off =3D offset + SSPP_REC_SRC_SIZE; + src_xy_off =3D offset + SSPP_REC_SRC_XY; + out_size_off =3D offset + SSPP_REC_OUT_SIZE; + out_xy_off =3D offset + SSPP_REC_OUT_XY; + + dpu_hw_setup_rects_impl(pipe, cfg, ctx, src_size_off, + src_xy_off, out_size_off, out_xy_off); +} + +static void dpu_hw_sspp_setup_sourceaddress_v13(struct dpu_sw_pipe *pipe, + struct dpu_hw_fmt_layout *layout) +{ + struct dpu_hw_sspp *ctx =3D pipe->sspp; + int i; + u32 offset, ystride0, ystride1; + + if (!ctx) + return; + + offset =3D dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx); + + for (i =3D 0; i < ARRAY_SIZE(layout->plane_addr); i++) + DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC0_ADDR + i * 0x4, + layout->plane_addr[i]); + + ystride0 =3D (layout->plane_pitch[0]) | (layout->plane_pitch[2] << 16); + ystride1 =3D (layout->plane_pitch[1]) | (layout->plane_pitch[3] << 16); + + DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC_YSTRIDE0, ystride0); + DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC_YSTRIDE1, ystride1); +} + +static void dpu_hw_sspp_setup_solidfill_v13(struct dpu_sw_pipe *pipe, u32 = color) +{ + struct dpu_hw_sspp *ctx =3D pipe->sspp; + u32 const_clr_off; + u32 offset; + + if (!ctx) + return; + + offset =3D dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx); + const_clr_off =3D offset + SSPP_REC_SRC_CONSTANT_COLOR; + + dpu_hw_setup_solidfill_impl(pipe, color, ctx, const_clr_off); +} + +static void dpu_hw_sspp_setup_qos_lut_v13(struct dpu_hw_sspp *ctx, + struct dpu_hw_qos_cfg *cfg) +{ + if (!ctx || !cfg) + return; + + _dpu_hw_setup_qos_lut_v13(&ctx->hw, cfg); +} + +static void dpu_hw_sspp_setup_qos_ctrl_v13(struct dpu_hw_sspp *ctx, + bool danger_safe_en) +{ + if (!ctx) + return; + + dpu_hw_sspp_setup_qos_ctrl_impl(ctx, danger_safe_en, SSPP_CMN_QOS_CTRL); +} + +static void dpu_hw_sspp_setup_cdp_v13(struct dpu_sw_pipe *pipe, + const struct msm_format *fmt, + bool enable) +{ + struct dpu_hw_sspp *ctx =3D pipe->sspp; + u32 offset =3D 0; + + if (!ctx) + return; + + offset =3D dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx); + dpu_setup_cdp(&ctx->hw, offset + SSPP_REC_CDP_CNTL, fmt, enable); +} + +static bool dpu_hw_sspp_setup_clk_force_ctrl_v13(struct dpu_hw_sspp *ctx, = bool enable) +{ + static const struct dpu_clk_ctrl_reg sspp_clk_ctrl =3D { + .reg_off =3D SSPP_CMN_CLK_CTRL, + .bit_off =3D 0 + }; + + return dpu_hw_clk_force_ctrl(&ctx->hw, &sspp_clk_ctrl, enable); +} + +void dpu_hw_sspp_init_v13(struct dpu_hw_sspp *c, + unsigned long features, const struct dpu_mdss_version *mdss_rev) +{ + c->ops.setup_format =3D dpu_hw_sspp_setup_format_v13; + c->ops.setup_rects =3D dpu_hw_sspp_setup_rects_v13; + c->ops.setup_sourceaddress =3D dpu_hw_sspp_setup_sourceaddress_v13; + c->ops.setup_solidfill =3D dpu_hw_sspp_setup_solidfill_v13; + c->ops.setup_pe =3D dpu_hw_sspp_setup_pe_config_v13; + + if (test_bit(DPU_SSPP_QOS, &features)) { + c->ops.setup_qos_lut =3D dpu_hw_sspp_setup_qos_lut_v13; + c->ops.setup_qos_ctrl =3D dpu_hw_sspp_setup_qos_ctrl_v13; + } + + if (test_bit(DPU_SSPP_CSC, &features) || + test_bit(DPU_SSPP_CSC_10BIT, &features)) + c->ops.setup_csc =3D dpu_hw_sspp_setup_csc; + + if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) || + test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features)) + c->ops.setup_multirect =3D dpu_hw_sspp_setup_multirect_v13; + + if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features)) + c->ops.setup_scaler =3D dpu_hw_sspp_setup_scaler3; + + if (test_bit(DPU_SSPP_CDP, &features)) + c->ops.setup_cdp =3D dpu_hw_sspp_setup_cdp_v13; + + c->ops.setup_clk_force_ctrl =3D dpu_hw_sspp_setup_clk_force_ctrl_v13; +} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_util.c index 486be346d40d..3cf22ec62792 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c @@ -81,6 +81,13 @@ static u32 dpu_hw_util_log_mask =3D DPU_DBG_MASK_NONE; #define QOS_CREQ_LUT_0 0x14 #define QOS_CREQ_LUT_1 0x18 =20 +/* CMN_QOS_LUT */ +#define SSPP_CMN_QOS_CTRL 0x28 +#define SSPP_CMN_DANGER_LUT 0x2c +#define SSPP_CMN_SAFE_LUT 0x30 +#define SSPP_CMN_CREQ_LUT_0 0x34 +#define SSPP_CMN_CREQ_LUT_1 0x38 + /* QOS_QOS_CTRL */ #define QOS_QOS_CTRL_DANGER_SAFE_EN BIT(0) #define QOS_QOS_CTRL_DANGER_VBLANK_MASK GENMASK(5, 4) @@ -475,6 +482,17 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *= c, u32 offset, cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0); } =20 +void _dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c, + const struct dpu_hw_qos_cfg *cfg) +{ + DPU_REG_WRITE(c, SSPP_CMN_DANGER_LUT, cfg->danger_lut); + DPU_REG_WRITE(c, SSPP_CMN_SAFE_LUT, cfg->safe_lut); + DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_0, cfg->creq_lut); + DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_1, cfg->creq_lut >> 32); + DPU_REG_WRITE(c, SSPP_CMN_QOS_CTRL, + cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0); +} + /* * note: Aside from encoders, input_sel should be set to 0x0 by default */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_util.h index 67b08e99335d..1822ac699757 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h @@ -360,6 +360,9 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c= , u32 offset, bool qos_8lvl, const struct dpu_hw_qos_cfg *cfg); =20 +void _dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c, + const struct dpu_hw_qos_cfg *cfg); + void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, u32 misr_ctrl_offset, u8 input_sel); =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_hw_wb.c index 478a091aeccf..006dcc4a0dcc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c @@ -148,6 +148,15 @@ static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *= ctx, cfg); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4f4ac66a1aasm72500001cf.33.2025.12.22.02.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Dec 2025 02:25:44 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, Dmitry Baryshkov Subject: [PATCH v4 11/11] drm/msm/dpu: Add support for Kaanapali DPU Date: Mon, 22 Dec 2025 18:24:00 +0800 Message-Id: <20251222102400.1109-12-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> References: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: khTCIyrxiwP0STCabmQgazUwZxFOjUNn X-Proofpoint-GUID: khTCIyrxiwP0STCabmQgazUwZxFOjUNn X-Authority-Analysis: v=2.4 cv=e9wLiKp/ c=1 sm=1 tr=0 ts=69491ca9 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=iVC9QAuiRl3Xz_40r_EA:9 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA5NCBTYWx0ZWRfX8Uut0VImYgMP 2dvSwnZ+weAQovmeicHHsOSpzNCPYgvw7wV4n5AMrEY+LRra7gXocJBgFSYZbqu5BailENb55nc xucmzQQ5ZHxR9XTEvgb8irjUDm06PP1drspIeISOu1YB9VUmbB4H2sel641Yi4FYsdtC5PHtuH0 yVjWVit38XwAGjUAYtP5FfY3JqG/gErNzSmyuA8UcCg2Q3cw7qPjcRRtW/IAZsWVvXEg3qo6e6C 9S5TkoLsQKkqkcZD0TJhQPHaRngQDBiT+AK7sNhTeAC/Ow3Rx9mUrkwCoFshIQHEEaRu+vqXASA 9tCOJvy4Gdcu/s0/crxETFV/Za16RXOQPWkx2Oeq32U5//JHcRASKpKKKPpKLCx6mDvFAS7EnXh qR9eS54Jtt5f6taGppA8cRYQ5ZKDMyqssxYy8m/UZcdt3H6jRsDraQqg0nLUi1tVd1l5CmGKXYL vO3LDkcAs8kUMHEv9Mg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 clxscore=1015 phishscore=0 adultscore=0 spamscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220094 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang Add support for Display Processing Unit (DPU) version 13.0 on the Kaanapali platform. This version introduces changes to the SSPP sub-block structure. Add common block and rectangle blocks to accommodate these structural modifications for compatibility. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov Signed-off-by: Yuanjie Yang --- .../disp/dpu1/catalog/dpu_13_0_kaanapali.h | 492 ++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 41 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 535 insertions(+) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapal= i.h diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h b/d= rivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h new file mode 100644 index 000000000000..0b20401b04cf --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h @@ -0,0 +1,492 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DPU_13_0_KAANAPALI_H +#define _DPU_13_0_KAANAPALI_H + +static const struct dpu_caps kaanapali_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0xb, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .has_3d_merge =3D true, + .max_linewidth =3D 8192, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_mdp_cfg kaanapali_mdp =3D { + .name =3D "top_0", + .base =3D 0, .len =3D 0x494, + .clk_ctrls =3D { + [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, + }, +}; + +static const struct dpu_ctl_cfg kaanapali_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1f000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x20000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x21000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x22000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name =3D "ctl_4", .id =3D CTL_4, + .base =3D 0x23000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name =3D "ctl_5", .id =3D CTL_5, + .base =3D 0x24000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg kaanapali_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x2b000, .len =3D 0x84, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_5, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_1", .id =3D SSPP_VIG1, + .base =3D 0x34000, .len =3D 0x84, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_5, + .xin_id =3D 4, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_2", .id =3D SSPP_VIG2, + .base =3D 0x3d000, .len =3D 0x84, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_5, + .xin_id =3D 8, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_3", .id =3D SSPP_VIG3, + .base =3D 0x46000, .len =3D 0x84, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_5, + .xin_id =3D 12, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x97000, .len =3D 0x84, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_9", .id =3D SSPP_DMA1, + .base =3D 0xa0000, .len =3D 0x84, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_10", .id =3D SSPP_DMA2, + .base =3D 0xa9000, .len =3D 0x84, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 9, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_11", .id =3D SSPP_DMA3, + .base =3D 0xb2000, .len =3D 0x84, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 13, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_12", .id =3D SSPP_DMA4, + .base =3D 0xbb000, .len =3D 0x84, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 14, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_13", .id =3D SSPP_DMA5, + .base =3D 0xc4000, .len =3D 0x84, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 15, + .type =3D SSPP_TYPE_DMA, + }, +}; + +static const struct dpu_lm_cfg kaanapali_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x103000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_1, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + }, { + .name =3D "lm_1", .id =3D LM_1, + .base =3D 0x10b000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_0, + .pingpong =3D PINGPONG_1, + .dspp =3D DSPP_1, + }, { + .name =3D "lm_2", .id =3D LM_2, + .base =3D 0x113000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_3, + .pingpong =3D PINGPONG_2, + .dspp =3D DSPP_2, + }, { + .name =3D "lm_3", .id =3D LM_3, + .base =3D 0x11b000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_2, + .pingpong =3D PINGPONG_3, + .dspp =3D DSPP_3, + }, { + .name =3D "lm_4", .id =3D LM_4, + .base =3D 0x123000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_5, + .pingpong =3D PINGPONG_4, + }, { + .name =3D "lm_5", .id =3D LM_5, + .base =3D 0x12b000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_4, + .pingpong =3D PINGPONG_5, + }, { + .name =3D "lm_6", .id =3D LM_6, + .base =3D 0x133000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_7, + .pingpong =3D PINGPONG_6, + }, { + .name =3D "lm_7", .id =3D LM_7, + .base =3D 0x13b000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_6, + .pingpong =3D PINGPONG_7, + }, +}; + +static const struct dpu_dspp_cfg kaanapali_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x105000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_1", .id =3D DSPP_1, + .base =3D 0x10d000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_2", .id =3D DSPP_2, + .base =3D 0x115000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_3", .id =3D DSPP_3, + .base =3D 0x11d000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, +}; + +static const struct dpu_pingpong_cfg kaanapali_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x108000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + }, { + .name =3D "pingpong_1", .id =3D PINGPONG_1, + .base =3D 0x110000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + }, { + .name =3D "pingpong_2", .id =3D PINGPONG_2, + .base =3D 0x118000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + }, { + .name =3D "pingpong_3", .id =3D PINGPONG_3, + .base =3D 0x120000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + }, { + .name =3D "pingpong_4", .id =3D PINGPONG_4, + .base =3D 0x128000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + }, { + .name =3D "pingpong_5", .id =3D PINGPONG_5, + .base =3D 0x130000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + }, { + .name =3D "pingpong_6", .id =3D PINGPONG_6, + .base =3D 0x138000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_3, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20), + }, { + .name =3D "pingpong_7", .id =3D PINGPONG_7, + .base =3D 0x140000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_3, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21), + }, { + .name =3D "pingpong_cwb_0", .id =3D PINGPONG_CWB_0, + .base =3D 0x169000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_4, + }, { + .name =3D "pingpong_cwb_1", .id =3D PINGPONG_CWB_1, + .base =3D 0x169400, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_4, + }, { + .name =3D "pingpong_cwb_2", .id =3D PINGPONG_CWB_2, + .base =3D 0x16a000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_5, + }, { + .name =3D "pingpong_cwb_3", .id =3D PINGPONG_CWB_3, + .base =3D 0x16a400, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_5, + }, +}; + +static const struct dpu_merge_3d_cfg kaanapali_merge_3d[] =3D { + { + .name =3D "merge_3d_0", .id =3D MERGE_3D_0, + .base =3D 0x163000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_1", .id =3D MERGE_3D_1, + .base =3D 0x164000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_2", .id =3D MERGE_3D_2, + .base =3D 0x165000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_3", .id =3D MERGE_3D_3, + .base =3D 0x166000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_4", .id =3D MERGE_3D_4, + .base =3D 0x169700, .len =3D 0x1c, + }, { + .name =3D "merge_3d_5", .id =3D MERGE_3D_5, + .base =3D 0x16a700, .len =3D 0x1c, + }, +}; + +/* + * NOTE: Each display compression engine (DCE) contains dual hard + * slice DSC encoders so both share same base address but with + * its own different sub block address. + */ +static const struct dpu_dsc_cfg kaanapali_dsc[] =3D { + { + .name =3D "dce_0_0", .id =3D DSC_0, + .base =3D 0x181000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_0_1", .id =3D DSC_1, + .base =3D 0x181000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_1_0", .id =3D DSC_2, + .base =3D 0x183000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_1_1", .id =3D DSC_3, + .base =3D 0x183000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_2_0", .id =3D DSC_4, + .base =3D 0x185000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_2_1", .id =3D DSC_5, + .base =3D 0x185000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_3_0", .id =3D DSC_6, + .base =3D 0x187000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_3_1", .id =3D DSC_7, + .base =3D 0x187000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, +}; + +static const struct dpu_wb_cfg kaanapali_wb[] =3D { + { + .name =3D "wb_2", .id =3D WB_2, + .base =3D 0x16e000, .len =3D 0x2c8, + .features =3D WB_SDM845_MASK, + .format_list =3D wb2_formats_rgb_yuv, + .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), + .xin_id =3D 6, + .vbif_idx =3D VBIF_RT, + .maxlinewidth =3D 4096, + .intr_wb_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, +}; + +static const struct dpu_cwb_cfg kaanapali_cwb[] =3D { + { + .name =3D "cwb_0", .id =3D CWB_0, + .base =3D 0x169200, .len =3D 0x20, + }, + { + .name =3D "cwb_1", .id =3D CWB_1, + .base =3D 0x169600, .len =3D 0x20, + }, + { + .name =3D "cwb_2", .id =3D CWB_2, + .base =3D 0x16a200, .len =3D 0x20, + }, + { + .name =3D "cwb_3", .id =3D CWB_3, + .base =3D 0x16a600, .len =3D 0x20, + }, +}; + +static const struct dpu_intf_cfg kaanapali_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, + .base =3D 0x18d000, .len =3D 0x4bc, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + }, { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x18e000, .len =3D 0x4bc, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, { + .name =3D "intf_2", .id =3D INTF_2, + .base =3D 0x18f000, .len =3D 0x4bc, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), + }, { + .name =3D "intf_3", .id =3D INTF_3, + .base =3D 0x190000, .len =3D 0x4bc, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + }, +}; + +static const struct dpu_perf_cfg kaanapali_perf_data =3D { + .max_bw_low =3D 21400000, + .max_bw_high =3D 30200000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 800000, + .min_prefill_lines =3D 35, + .danger_lut_tbl =3D {0x0ffff, 0x0ffff, 0x0}, + .safe_lut_tbl =3D {0xff00, 0xff00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(kaanapali_qos_linear), + .entries =3D kaanapali_qos_linear + }, + {.nentry =3D ARRAY_SIZE(kaanapali_qos_macrotile), + .entries =3D kaanapali_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version kaanapali_mdss_ver =3D { + .core_major_ver =3D 13, + .core_minor_ver =3D 0, +}; + +const struct dpu_mdss_cfg dpu_kaanapali_cfg =3D { + .mdss_ver =3D &kaanapali_mdss_ver, + .caps =3D &kaanapali_dpu_caps, + .mdp =3D &kaanapali_mdp, + .cdm =3D &dpu_cdm_13_x, + .ctl_count =3D ARRAY_SIZE(kaanapali_ctl), + .ctl =3D kaanapali_ctl, + .sspp_count =3D ARRAY_SIZE(kaanapali_sspp), + .sspp =3D kaanapali_sspp, + .mixer_count =3D ARRAY_SIZE(kaanapali_lm), + .mixer =3D kaanapali_lm, + .dspp_count =3D ARRAY_SIZE(kaanapali_dspp), + .dspp =3D kaanapali_dspp, + .pingpong_count =3D ARRAY_SIZE(kaanapali_pp), + .pingpong =3D kaanapali_pp, + .dsc_count =3D ARRAY_SIZE(kaanapali_dsc), + .dsc =3D kaanapali_dsc, + .merge_3d_count =3D ARRAY_SIZE(kaanapali_merge_3d), + .merge_3d =3D kaanapali_merge_3d, + .wb_count =3D ARRAY_SIZE(kaanapali_wb), + .wb =3D kaanapali_wb, + .cwb_count =3D ARRAY_SIZE(kaanapali_cwb), + .cwb =3D sm8650_cwb, + .intf_count =3D ARRAY_SIZE(kaanapali_intf), + .intf =3D kaanapali_intf, + .vbif_count =3D ARRAY_SIZE(sm8650_vbif), + .vbif =3D sm8650_vbif, + .perf =3D &kaanapali_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 23bb39b471b7..be3492df8bde 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -241,6 +241,23 @@ static const u32 wb2_formats_rgb_yuv[] =3D { .rotation_cfg =3D NULL, \ } =20 +/* kaanapali SSPP common configuration */ +#define _VIG_SBLK_REC0_REC1(scaler_ver) \ + { \ + .sspp_rec0_blk =3D {.name =3D "sspp_rec0", \ + .base =3D 0x1000, .len =3D 0x180,}, \ + .csc_blk =3D {.name =3D "csc", \ + .base =3D 0x1800, .len =3D 0x100,}, \ + .scaler_blk =3D {.name =3D "scaler", \ + .version =3D scaler_ver, \ + .base =3D 0x2000, .len =3D 0xec,}, \ + .sspp_rec1_blk =3D {.name =3D "sspp_rec1", \ + .base =3D 0x3000, .len =3D 0x180,}, \ + .format_list =3D plane_formats_yuv, \ + .num_formats =3D ARRAY_SIZE(plane_formats_yuv), \ + .rotation_cfg =3D NULL, \ + } + #define _VIG_SBLK_ROT(scaler_ver, rot_cfg) \ { \ .scaler_blk =3D {.name =3D "scaler", \ @@ -329,6 +346,9 @@ static const struct dpu_sspp_sub_blks dpu_vig_sblk_qsee= d3_3_3 =3D static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_4 =3D _VIG_SBLK(SSPP_SCALER_VER(3, 4)); =20 +static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_5 =3D + _VIG_SBLK_REC0_REC1(SSPP_SCALER_VER(3, 5)); + static const struct dpu_sspp_sub_blks dpu_rgb_sblk =3D _RGB_SBLK(); =20 static const struct dpu_sspp_sub_blks dpu_dma_sblk =3D _DMA_SBLK(); @@ -412,6 +432,11 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sb= lk =3D { .len =3D 0x20, .version =3D 0x20000}, }; =20 +static const struct dpu_pingpong_sub_blks kaanapali_pp_sblk =3D { + .dither =3D {.name =3D "dither", .base =3D 0xc0, + .len =3D 0x40, .version =3D 0x30000}, +}; + /************************************************************* * DSC sub blocks config *************************************************************/ @@ -452,6 +477,13 @@ static const struct dpu_cdm_cfg dpu_cdm_5_x =3D { .base =3D 0x79200, }; =20 +static const struct dpu_cdm_cfg dpu_cdm_13_x =3D { + .name =3D "cdm_0", + .id =3D CDM_0, + .len =3D 0x240, + .base =3D 0x19e000, +}; + /************************************************************* * VBIF sub blocks config *************************************************************/ @@ -639,6 +671,10 @@ static const struct dpu_qos_lut_entry sc7180_qos_linea= r[] =3D { {.fl =3D 0, .lut =3D 0x0011222222335777}, }; =20 +static const struct dpu_qos_lut_entry kaanapali_qos_linear[] =3D { + {.fl =3D 0, .lut =3D 0x0011223344556666}, +}; + static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] =3D { {.fl =3D 0, .lut =3D 0x0011223445566777 }, }; @@ -668,6 +704,10 @@ static const struct dpu_qos_lut_entry sc7180_qos_macro= tile[] =3D { {.fl =3D 0, .lut =3D 0x0011223344556677}, }; =20 +static const struct dpu_qos_lut_entry kaanapali_qos_macrotile[] =3D { + {.fl =3D 0, .lut =3D 0x0011223344556666}, +}; + static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] =3D { {.fl =3D 10, .lut =3D 0x0000000344556677}, }; @@ -727,3 +767,4 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_10_0_sm8650.h" #include "catalog/dpu_12_0_sm8750.h" #include "catalog/dpu_12_2_glymur.h" +#include "catalog/dpu_13_0_kaanapali.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index b03fea1b9cbd..83870e84d789 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -764,6 +764,7 @@ struct dpu_mdss_cfg { }; =20 extern const struct dpu_mdss_cfg dpu_glymur_cfg; +extern const struct dpu_mdss_cfg dpu_kaanapali_cfg; extern const struct dpu_mdss_cfg dpu_msm8917_cfg; extern const struct dpu_mdss_cfg dpu_msm8937_cfg; extern const struct dpu_mdss_cfg dpu_msm8953_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index f4c9767c418d..0623f1dbed97 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1506,6 +1506,7 @@ static const struct dev_pm_ops dpu_pm_ops =3D { =20 static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,glymur-dpu", .data =3D &dpu_glymur_cfg, }, + { .compatible =3D "qcom,kaanapali-dpu", .data =3D &dpu_kaanapali_cfg, }, { .compatible =3D "qcom,msm8917-mdp5", .data =3D &dpu_msm8917_cfg, }, { .compatible =3D "qcom,msm8937-mdp5", .data =3D &dpu_msm8937_cfg, }, { .compatible =3D "qcom,msm8953-mdp5", .data =3D &dpu_msm8953_cfg, }, --=20 2.34.1