From nobody Mon Feb 9 07:57:42 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A7E13112B7; Mon, 22 Dec 2025 09:59:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766397589; cv=none; b=URhMK9qQ3tkxke3p5joHKeWJLhDxzl02zziGqvQdKNh3dGnm+y8wAE1dmZaFMey0sDaN5GsdqwSm+yTZRgx8MGkQeXHw7g1vxUTlBVLQXNEfHufT3bJmQZfnx41oHO4ZOs4xGPH2CnQB5FQmgnSexrHNeYH6IAP+SwC5EUxgBwI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766397589; c=relaxed/simple; bh=byqQdkECqUsBNdDd2tkVFPXBMf3Uck104mxVKGDm08M=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=utY/QTr0avmMSOvJvV/JE1+RILvISMhkMrI4w8KkDplc1fGyHhW0ftHOV6TWiW74WaU1fJ+l1+PtMt1A8NlNqdoF8bb2qaDFPxLSdN2NlLwf+mMceoz7mA24xNTM079/e9YGElyhvaRROq2thgea0bNlEXf9b1w1hiDRfRmiYVM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=j5VaDvj0; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="j5VaDvj0" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BM824YH3586371; Mon, 22 Dec 2025 09:59:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= puwrNkeefsGsVdj92cwnxJqsErXN0jD9MjSzI5I3bKc=; b=j5VaDvj00QYNnr9+ 4T+havVA/K9gaBIeNEJPL856bp45epcMgn/Ztgtyg0tdmawsWZr7F/h2hyo0a7jc v3PaCeBME5SmcRBuNlgwp3RqqH/cP7lYJ9Mm5l+OhutbphiXo1lIXrsxBpeziEkp qNH36oVJA1YAL7YRlE5PsbtmsIzBHztpCdZtAGdgAQCvWlyyRX3R77VpEMeTcxnT CNtzj9M1dkCoDIOAuWUW+6LhtwGgZpCUtX+iFBbv9/bkWsgeEBTu/9DUh5Nj5Q+T jya/PHuCgumL2kvxQHAx9qr2nKaOY9NkO9LVwHNi+eBQwV4vqSltXuOFL23OUBh0 zhmXfQ== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b69ahjvcw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 Dec 2025 09:59:40 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5BM9xd1P026352 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 Dec 2025 09:59:39 GMT Received: from hu-nihalkum-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Mon, 22 Dec 2025 01:59:34 -0800 From: Nihal Kumar Gupta To: , , , , , , , , , , CC: , , , , , , "Vladimir Zapolskiy" Subject: [PATCH v8 1/5] dt-bindings: i2c: qcom-cci: Document qcs8300 compatible Date: Mon, 22 Dec 2025 15:29:10 +0530 Message-ID: <20251222095914.1995041-2-quic_nihalkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251222095914.1995041-1-quic_nihalkum@quicinc.com> References: <20251222095914.1995041-1-quic_nihalkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=JuH8bc4C c=1 sm=1 tr=0 ts=6949168c cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=VwQbUJbxAAAA:8 a=s_BFhqDHtHiVpoTEQLAA:9 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 0XI8_uyKexs6rYMBinzI26mm7LBfEVq1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA5MCBTYWx0ZWRfX6NzlH5IZvqEf JgKnjdAklr7bP/Xk+ElocRbfyHVTURbIX6WRJtW5sTvFQTAldzrIsphGEzTIOUVNRKmWPSZp1X0 vLoC+UotB+ZJ0+ZweRCbFONA5p4iDpIu3LSUJYXRZA+w+DLz24yOXWdphftyVsmhqPiGZITtA3H aH0MgP6doNfWk55EyHwxkV9AE+MMJC0eNQyk1ysIi4+lCeJA6KJSUVDmXgKJGQrgTh1FPAC4lkS bVYWIBw/MWpEr/cn3I/FaVEHhwFQEfX/348nhar/7nUVUNtWKmxOIlHu/TvWdpT7kjp4fsLk99D HdIg63nU6ITsfORYicoPsSnFpG7efeLGOulV0JYCRpjpE9s3pUMAEdEagzGNSfZ6y/BuvGdLS7q 1Sn8ZwX7K40wV0CF0Yp0jfqP8gLmZj/xcmfkV+/PgAqvgdvoPkG5XAMWSVmMQ1jJChNUs8zjGoM zxOs/DE+eT1CD4WudJQ== X-Proofpoint-GUID: 0XI8_uyKexs6rYMBinzI26mm7LBfEVq1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 adultscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 suspectscore=0 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220090 Content-Type: text/plain; charset="utf-8" The three instances of CCI found on the QCS8300 are functionally the same as on a number of existing Qualcomm SoCs. Introduce a new SoC-specific compatible string "qcom,qcs8300-cci" with a common fallback. Signed-off-by: Nihal Kumar Gupta Signed-off-by: Vikram Sharma Reviewed-by: Bryan O'Donoghue Acked-by: Rob Herring (Arm) Reviewed-by: Vladimir Zapolskiy --- Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Docu= mentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index a3fe1eea6aec..399a09409e07 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -28,6 +28,7 @@ properties: - enum: - qcom,kaanapali-cci - qcom,qcm2290-cci + - qcom,qcs8300-cci - qcom,sa8775p-cci - qcom,sc7280-cci - qcom,sc8280xp-cci @@ -133,6 +134,7 @@ allOf: enum: - qcom,kaanapali-cci - qcom,qcm2290-cci + - qcom,qcs8300-cci - qcom,sm8750-cci then: properties: --=20 2.34.1 From nobody Mon Feb 9 07:57:42 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B905276058; Mon, 22 Dec 2025 09:59:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766397596; cv=none; b=FFDS0HiBPjEoRvhLHM09D1FBpLzXteXYEzPINZxhO82y/E9AYKDVV+j9wFrFRaR2o02i/V4c21fKB+0mXeBpNqGZ396cOdKF5LRAGPlymiMKzzsm8Y4J1zl5uLD7PbttC3Vz5Szqrl4cSkAHz7l6p+wAx2JfV17o/vI3QqcvVfc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766397596; c=relaxed/simple; bh=PjYwMhgZQqxfRb2fP7RbSjwkJlriO0j8n6mt4HMdv7A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IEb8JAWQ05uQDEC4y+/dtXAeicKFIB7VIGzGhc8l7TtjNKXFA+RHfvppWo4prjYlIL3NuIKumvqFK/qp5LRgldY9b72S5SloEkBAP/gAqYx8WztmjjqG4vlFs//JdyNy8gMxbZp/aT0njIcgNFSbOi4r4RB4MRUBAEzVN148MCM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=k4GsxZ8D; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="k4GsxZ8D" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BM83f7a3823070; Mon, 22 Dec 2025 09:59:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= MmuJgPpOeInHr8xJ+Yp3yfljwMiRXx6yw+bI1KqSnnM=; b=k4GsxZ8Dio110uF9 ckLGDv9SObWu1pvwTn7+V7kC1EOEwjN/zG/lMil2NeRUpVP7W5iVMDlTDf11425N CV8ynZFWQtwb4HDI4dgVOWK75rQ3yMg/dNPb0x+8lhi5oic8HelQ4dGpTV3ISJMu E4+YmmP2DYvU0Q0bq1cT1kQu69zp4a8JPibEe8TiCAGi71A794ps24a8FBNUvUV5 vTuw6J4Lg8G7AUPtpPL7k0DdbP2xjZAklWby7VrFMrgM67HpchhcxP65zj8hrNC7 LAlwbnqP72YyQhxlrGtr1AxHFUIRcvmaHIQeV2SMGXiS3c2dgqdycOQmvX3kAGR+ dEMMmw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b5mrtck8j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 Dec 2025 09:59:46 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5BM9xjec009561 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 Dec 2025 09:59:45 GMT Received: from hu-nihalkum-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Mon, 22 Dec 2025 01:59:39 -0800 From: Nihal Kumar Gupta To: , , , , , , , , , , CC: , , , , , , Ravi Shankar , Vishal Verma , Vladimir Zapolskiy , Konrad Dybcio Subject: [PATCH v8 2/5] arm64: dts: qcom: monaco: Add CCI definitions Date: Mon, 22 Dec 2025 15:29:11 +0530 Message-ID: <20251222095914.1995041-3-quic_nihalkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251222095914.1995041-1-quic_nihalkum@quicinc.com> References: <20251222095914.1995041-1-quic_nihalkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: WSUOzlcCJBO9UBuci-iSLQqLwTa4RrCY X-Proofpoint-GUID: WSUOzlcCJBO9UBuci-iSLQqLwTa4RrCY X-Authority-Analysis: v=2.4 cv=CeEFJbrl c=1 sm=1 tr=0 ts=69491692 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=8cEEmJuSjmb3-IlBk7AA:9 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA5MCBTYWx0ZWRfX36KNOFR+32ZZ rvwEc2mH1YOGA0AOMXlHmZSld7S1Ob4tu+PAa2iuqfoJOOZzTZbUeEnoXJkNTx46mjgGXOSNZUC G2DNuBVu00GSSam3ToreqBmRP00NThtRqc+ASZfXuQgmTxcKJ86NJlw/oy8uMykC9BlettaQ9wM ic3drYIXC3j6QvZRDS/U7pKqxE5EXH21hvWkRUHCLajT4caJzm5Juaid5t/C7R5fnjweVmGRI6c k/s/yVTUOxE9Om9Kp58AqVJT1Khv1EJA5eGwFhcIXbiHMwfccSFyH8jjjy8xucUINH5+yIL4VlX OCd3T642ZAWQXAa5vyPfXzqpy9EYPCsFlMf2MkZAE4ax2fbZ2n3UxJckxLlPPwRgK1GT/5W205j azjhQsGiE+TFsqD3Qh+xX4cibErdNH9aleX5410I2JAKVj+rV9ad7q4ov9GKS84lF8V6ltvViIp OWoR+9+7Hx7I+WE61ww== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 bulkscore=0 adultscore=0 spamscore=0 clxscore=1015 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220090 Content-Type: text/plain; charset="utf-8" Qualcomm QCS8300 SoC contains three Camera Control Interface (CCI). Compared to Lemans, the key difference is in SDA/SCL GPIO assignments and number of CCIs. Signed-off-by: Nihal Kumar Gupta Co-developed-by: Ravi Shankar Signed-off-by: Ravi Shankar Co-developed-by: Vishal Verma Signed-off-by: Vishal Verma Co-developed-by: Suresh Vankadara Signed-off-by: Suresh Vankadara Signed-off-by: Vikram Sharma Reviewed-by: Vladimir Zapolskiy Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/monaco.dtsi | 303 +++++++++++++++++++++++++++ 1 file changed, 303 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qco= m/monaco.dtsi index 774255c3f6fc..4b2d8a449b00 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -4776,6 +4776,117 @@ videocc: clock-controller@abf0000 { #power-domain-cells =3D <1>; }; =20 + cci0: cci@ac13000 { + compatible =3D "qcom,qcs8300-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac13000 0x0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names =3D "cpas_ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci0_0_default &cci0_1_default>; + pinctrl-1 =3D <&cci0_0_sleep &cci0_1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci1: cci@ac14000 { + compatible =3D "qcom,qcs8300-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac14000 0x0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names =3D "cpas_ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci1_0_default &cci1_1_default>; + pinctrl-1 =3D <&cci1_0_sleep &cci1_1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci2: cci@ac15000 { + compatible =3D "qcom,qcs8300-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac15000 0x0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-names =3D "cpas_ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci2_0_default &cci2_1_default>; + pinctrl-1 =3D <&cci2_0_sleep &cci2_1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci2_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci2_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + camss: isp@ac78000 { compatible =3D "qcom,qcs8300-camss"; =20 @@ -5071,6 +5182,198 @@ tlmm: pinctrl@f100000 { #interrupt-cells =3D <2>; wakeup-parent =3D <&pdc>; =20 + cci0_0_default: cci0-0-default-state { + sda-pins { + pins =3D "gpio57"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio58"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci0_0_sleep: cci0-0-sleep-state { + sda-pins { + pins =3D "gpio57"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio58"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci0_1_default: cci0-1-default-state { + sda-pins { + pins =3D "gpio29"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio30"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci0_1_sleep: cci0-1-sleep-state { + sda-pins { + pins =3D "gpio29"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio30"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_0_default: cci1-0-default-state { + sda-pins { + pins =3D "gpio59"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio60"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci1_0_sleep: cci1-0-sleep-state { + sda-pins { + pins =3D "gpio59"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio60"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_1_default: cci1-1-default-state { + sda-pins { + pins =3D "gpio31"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio32"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci1_1_sleep: cci1-1-sleep-state { + sda-pins { + pins =3D "gpio31"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio32"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci2_0_default: cci2-0-default-state { + sda-pins { + pins =3D "gpio61"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio62"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci2_0_sleep: cci2-0-sleep-state { + sda-pins { + pins =3D "gpio61"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio62"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci2_1_default: cci2-1-default-state { + sda-pins { + pins =3D "gpio54"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio55"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci2_1_sleep: cci2-1-sleep-state { + sda-pins { + pins =3D "gpio54"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio55"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + hs0_mi2s_active: hs0-mi2s-active-state { pins =3D "gpio106", "gpio107", "gpio108", "gpio109"; function =3D "hs0_mi2s"; --=20 2.34.1 From nobody Mon Feb 9 07:57:42 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C257830DD1A; Mon, 22 Dec 2025 09:59:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766397601; cv=none; b=StdBbb2Dg4ba4JHNUlfNAmt9LCWBjbf2sXsjrg6zEN7oBcOLPqLVUiBt8kZRrZN9o+qMr+6HhTSMkHr5vwrR50Xt5ypa55mQT0TzwKHdci9Gq66dpFBEjYw+aUf7Qimzmyoah0s2IOli0l4nyQAIW+lv8UdSPTmOHImMxCAoKJw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766397601; c=relaxed/simple; bh=y2zvf8S7gYfp2F8RoVQ0LnOhTBjh2SAx0h0h6ZmEn80=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=alNvGTBmzkkVy9J32+xK2PNqRjX84W91cS00xJNgSWn3Pxn0B87dT48X2cAPNgC7uIdiAAR6i5UupwE5ZFCFN8JX4HouEPXP2wxwHu5vOj2ixBvsb5vCNwIE38HKtsRfFAOl53rlk+N5PFBteGqtKHS9bw76J0ffS4FhfUxf02c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Tbf5Wx4q; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Tbf5Wx4q" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BM8wq8e3962884; Mon, 22 Dec 2025 09:59:52 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= xGuTJwfFN66OKPst8uy87K+lOkYNI7LbJ64dSvoR0Kw=; b=Tbf5Wx4q8i+tOGqq mrOy+WjDtyvqLsJU9b0vqwoupVFRGMgUYD0hLZF941IUDe0rNoxoQPuus4Z+AueJ xiZIm0Yny0xwp/tlSRmIIcaQsVUF1I1bqePFpA9T23hYD+CxcEYxScKKWxRkL5rB pPZRv3+KqBIw/Ic2LO1Wa0o8pRQNzXibpf6XF6yzt/3N25mNTDoug81uLgbprNrz udw6oY5jz0rP4017PHTQnXg/PrZe6JRxJUPtP0KHRedXBYuZ1vNML1cOsSH7zmvu Yz9UvXq8ScFV0KRv/LYXho2nXpENa3IbwLVmQTBrk+VAA9hqvSLhR8lpvh0VXT47 5Ea8MQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b6vk6hab3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 Dec 2025 09:59:52 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5BM9xprY024437 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 Dec 2025 09:59:51 GMT Received: from hu-nihalkum-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Mon, 22 Dec 2025 01:59:45 -0800 From: Nihal Kumar Gupta To: , , , , , , , , , , CC: , , , , , , Konrad Dybcio , Vladimir Zapolskiy Subject: [PATCH v8 3/5] arm64: dts: qcom: monaco: Add camera MCLK pinctrl Date: Mon, 22 Dec 2025 15:29:12 +0530 Message-ID: <20251222095914.1995041-4-quic_nihalkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251222095914.1995041-1-quic_nihalkum@quicinc.com> References: <20251222095914.1995041-1-quic_nihalkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: u7JxKn6oG7ihmhNiFEF6iQAG0JscfQXt X-Authority-Analysis: v=2.4 cv=cuuWUl4i c=1 sm=1 tr=0 ts=69491698 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=tfCBMw9KTM5U2-pTabYA:9 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA5MCBTYWx0ZWRfXzZcGNsGDBru9 L+ejXK53X/awq7ZRy8PTp+NomkcuxJtTyNwauyv+q5CmWpS2Cp9yNl/AFkOmzrM497spfbMF9wl Ovlv6v/D2+HW2bcbsgxw+p9fe/Q58P1wJzSnYmC5M/YKWmrzdnjomeJEMfuYQIF8uFQvvrtGFCG pOzE5pb1tZ6u4JjaYq4kxlDD6Pd5UvUhUEsx+/KEllJyO6RY2PTYoeFOPNTbOLRxTOg//dC66wu dyUo//eVJFrq45jHFh7Ay8fECGKRFosXZihLqdW1AWvAiZPrOqBZUYNN+aepA6nVyfFBZUZgTTY R8YFlR1DM+6OwvMYBuLOm5YehT2wqF7e4525GEjaRbOhRFDc2kTRwIM1k2YIseK8fDMzVRLNhsq susTF7KYGMmFlzvrDwrBrshQqqq5bml/xJiNm3ltlOmUYBPgNperKd0rzs42REJe7bWPj3mInSc bevDUWzc67a2JjWSO1Q== X-Proofpoint-GUID: u7JxKn6oG7ihmhNiFEF6iQAG0JscfQXt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 priorityscore=1501 spamscore=0 bulkscore=0 suspectscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220090 Content-Type: text/plain; charset="utf-8" Define pinctrl definitions to enable camera master clocks on Monaco. Signed-off-by: Nihal Kumar Gupta Signed-off-by: Vikram Sharma Reviewed-by: Konrad Dybcio Reviewed-by: Vladimir Zapolskiy --- arch/arm64/boot/dts/qcom/monaco.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qco= m/monaco.dtsi index 4b2d8a449b00..ace09239d167 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -5182,6 +5182,27 @@ tlmm: pinctrl@f100000 { #interrupt-cells =3D <2>; wakeup-parent =3D <&pdc>; =20 + cam0_default: cam0-default-state { + pins =3D "gpio67"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + + cam1_default: cam1-default-state { + pins =3D "gpio68"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + + cam2_default: cam2-default-state { + pins =3D "gpio69"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + cci0_0_default: cci0-0-default-state { sda-pins { pins =3D "gpio57"; --=20 2.34.1 From nobody Mon Feb 9 07:57:42 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BB9330DD11; Mon, 22 Dec 2025 10:00:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766397608; cv=none; b=eqnMrPbpJgvTvs2K8OuMBREjHanrxgPFLB6heoFc/R4OqId5vsV1uToj4pXMv6Tg7ZGZErYjSQrmzi75l4w7E+Py/+bqQD+4l3My6bNKTF/2xX0vIASwZgCdAclqfnzlgQxhioJ+a9rZvyEPtwUB0ho4RrXO0rVMwjo74bkgP5I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766397608; c=relaxed/simple; bh=GCy3vxjrhphXY3SBRQ6gcvkVo7qezoDUE7N+hbhgnRk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=f8iiQXgbk9DAhDYnuYzvzb0qWEGywk63MA2J4AaaUAthuOxhhYP/uES1zcakoKz1D31bhxlBihqHXAuU9Yq12sYG9LQ7NY7aiH+mQnVTrwt46VINoX0Z69bjgcbBeKIYNSnGkt8tF6NsCP4ycjMTdHl9YYT5R4zGfscfUJ1pvX8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=PGyN+4Og; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="PGyN+4Og" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BM7g4F43898705; Mon, 22 Dec 2025 09:59:58 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= QIXnflSc/RxnEjlyvDAhENUWxwkCvNNXaThEWH3lCrk=; b=PGyN+4Oga63xiCZo 2mJGvoU05fbP0heZY6CSctRDrQIShA1SPQwF3izoiPd+2l/Ahb8+eKWVWWhhiAkp 8q/iulhvFzlAUr6gC5LKQmrw3ITdSm3bSoXcql9SioGqroj5aKnmDYeMjn5JerFk 7H54dd9aoiaiQSNmT+QmW+K4U9dcygyFowtEmqUYvnudyPRcxRBf0I3SDVa7MTrW cSNcVlawzNoAHwjxItRyULiZBN6GhLyPphrP5m7scz/8pib1XxGDYsyZcZgE7PJK Y/ii2Eu4FbeXlObVkPBEHxLn7CAS8ieTBW2MpQ19lBFYhLDBmjBAwRgv1IwJp/5R VMWn6w== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b5mvfmjbv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 Dec 2025 09:59:57 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5BM9xuHl022584 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 Dec 2025 09:59:56 GMT Received: from hu-nihalkum-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Mon, 22 Dec 2025 01:59:51 -0800 From: Nihal Kumar Gupta To: , , , , , , , , , , CC: , , , , , , Konrad Dybcio Subject: [PATCH v8 4/5] arm64: dts: qcom: monaco-evk: Add camera AVDD regulators Date: Mon, 22 Dec 2025 15:29:13 +0530 Message-ID: <20251222095914.1995041-5-quic_nihalkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251222095914.1995041-1-quic_nihalkum@quicinc.com> References: <20251222095914.1995041-1-quic_nihalkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=H8rWAuYi c=1 sm=1 tr=0 ts=6949169d cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=KSpx70hPW1lZ7Xonwr0A:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: VMf_zQyf-87t5wOJtrtIN6Z_7afEobvi X-Proofpoint-GUID: VMf_zQyf-87t5wOJtrtIN6Z_7afEobvi X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA5MCBTYWx0ZWRfX4+ji3xhyrQ7A epfSiyzd14GRBcrc0GSZzslsxVAzxRw91u4JA51+n4rtW+cj4Leh4dLNnCthy/XoWStm4icXPw9 tB0AGkbeF1ipuVifauV2pDRwAxSh6LRIcshtDorTdUY8rS+c9EFF/Tu4zHBEyfpBWcOc82jHBbT HE508Ry2tBDjL6Gxv0rb8nwjONaHWXW4cqYPSfrWnwyBiIdiPpjUeE00FF/wi41BU4PTw84ToGU 1619iS+nx6Mjm5ZV/UweAs5cf10inuHtKLxiUUtQEkUw2jiiBwY2d+HjDi95QvVLfm1yQSLz/ub uwuKK/7ph1ThxLml0nKmSaCQOOMFq58FPgjzhlYdcYqN/extll41NI38yjt84pLj+1taJvAfrU9 wTgPXk8+QCJv19mHtVu9XFMpyICoxZgqEqY8ohlYXfXE7dgczFd0HQOzJWTdoSn+Q3PoavyLZGU 2ai7ATsYyoPSOcQ9xxQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 bulkscore=0 spamscore=0 adultscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220090 Content-Type: text/plain; charset="utf-8" Define three fixed regulators for camera AVDD rails, each gpio-controlled with corresponding pinctrl definitions. Signed-off-by: Nihal Kumar Gupta Signed-off-by: Vikram Sharma Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 51 +++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/= qcom/monaco-evk.dts index bb35893da73d..003c24d08c71 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -76,6 +76,36 @@ platform { }; }; }; + + vreg_cam0_2p8: vreg-cam0-2p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_cam0_2p8"; + startup-delay-us =3D <10000>; + enable-active-high; + gpio =3D <&tlmm 73 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&cam0_avdd_2v8_en_default>; + pinctrl-names =3D "default"; + }; + + vreg_cam1_2p8: vreg-cam1-2p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_cam1_2p8"; + startup-delay-us =3D <10000>; + enable-active-high; + gpio =3D <&tlmm 74 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&cam1_avdd_2v8_en_default>; + pinctrl-names =3D "default"; + }; + + vreg_cam2_2p8: vreg-cam2-2p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_cam2_2p8"; + startup-delay-us =3D <10000>; + enable-active-high; + gpio =3D <&tlmm 75 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&cam2_avdd_2v8_en_default>; + pinctrl-names =3D "default"; + }; }; =20 &apps_rsc { @@ -458,6 +488,27 @@ qup_i2c1_default: qup-i2c1-state { bias-pull-up; }; =20 + cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state { + pins =3D "gpio73"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + cam1_avdd_2v8_en_default: cam1-avdd-2v8-en-state { + pins =3D "gpio74"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + cam2_avdd_2v8_en_default: cam2-avdd-2v8-en-state { + pins =3D "gpio75"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + qup_i2c15_default: qup-i2c15-state { pins =3D "gpio91", "gpio92"; function =3D "qup1_se7"; --=20 2.34.1 From nobody Mon Feb 9 07:57:42 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB65430DD1A; Mon, 22 Dec 2025 10:00:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766397615; cv=none; b=AbouyyYzBRmfUASk+ZQcnEJa+wFhHy6cjjgFxzPB+9qI56TeZrQNpUVAsgwDfrL0Vhwl6pFEWMI8A84L68b85iZ0R4uBS7XxRO5wrZMbYicPnEuqbrrFtLXsDCElczO8x9ezkufO2svadaxORcfnZxQA25OgvvX9bxW0Yspg5ME= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766397615; c=relaxed/simple; bh=Cz3nyorbx/6nHeP3KH78ms1oC3DTt7rz5FBTkFNgMAo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=k6/BEQ3/zoUPPKNJlKGQf9eeCtsiPNBT9akEYUQtIRGZl4wQCFM63S6Lh8nF4l864dgpIoRGeptmdJ9+sQJp8l9twjsUgcDAAwAurwKeO8+yk9f+4SL/stzp9uUSvuPnOS220mCJAwRhXjqdhbqj0/Wiq6fiNnk63iISfAk27Tk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=SuJtGtDT; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="SuJtGtDT" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BM7Yvjm3762876; Mon, 22 Dec 2025 10:00:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= p58K4XZOqz0oNtNa5uRPf+AR9hdFFuWFEc5K2o4vlmM=; b=SuJtGtDTQgOfgmgt Od5ysDhJRimyfYPSTbVIoVGzumlw2MfHG/05fRSKnpiaGryJK1BZtFpGxw9u/cw9 gVe7oi1LPxGSj00w+ydsvZpQp+qlRdVrPHxgn1jiwcladats3Q7psGQXAEh9VYMq UQC0iJuf2yeimDYiXddJORlvOCt5fkl43j6th+CWwpLKxW/jdXI/wGJrbqkIgzKm b67DcnOiKEg0qdCFwsoLLKhzqd0G6NYUHKKiablzGvbxgv26a2BjzjSacTP4Dl60 u6uWhV63Af72xnrm4cV9x77t7NIfikxeEstlRKdP9588TWf6XK67OUrGdl0R0QgD zSl4MQ== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b5mru4jur-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 Dec 2025 10:00:04 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5BMA02ts011294 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 Dec 2025 10:00:03 GMT Received: from hu-nihalkum-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Mon, 22 Dec 2025 01:59:56 -0800 From: Nihal Kumar Gupta To: , , , , , , , , , , CC: , , , , , , Ravi Shankar , Vishal Verma , Vladimir Zapolskiy Subject: [PATCH v8 5/5] arm64: dts: qcom: monaco-evk-camera: Add DT overlay Date: Mon, 22 Dec 2025 15:29:14 +0530 Message-ID: <20251222095914.1995041-6-quic_nihalkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251222095914.1995041-1-quic_nihalkum@quicinc.com> References: <20251222095914.1995041-1-quic_nihalkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA5MCBTYWx0ZWRfXygVga24SYgwJ +gBz9anhGc44tFrd6no4mcivtlmrutINROZWjelxBezYqSxg1g/GPrFBiPgiK0C/kDrXPJVK/1Z BdxrgDLLcjMZ4pAk3mL2iOlxly2Wy0Pre8PjyJjeQ8hUElfOFhTIQdqjPHP/MDzLE9GNjzJYu4s S8xPupQB6amrshh7sQxXtmIE8ySB32S1pvXHjHzS7fJSqTXO10MJddgT5fDH5fVna+EvnJV32iI nreFrNN8YZgupcEWOODeGsqfgMfSlcYLigkBmSRbIp6y5Ns/c+beq6AN0vSgGMtz9QzmR2wXGS/ yBu+sVE30VZeLk0eoIBfbnakjKB6bfZxOSEdrui5oupUndSLszov6y9sTG0plFXfyB19uAnYaKy oDslBQdzALenQwykArVS01E0LAidf9gpD9elwPjsv11sDIPnuv6lUI8D/68+cgmYN9Kl0yrGB/U ohNw+9MAyRVtwUnby1A== X-Authority-Analysis: v=2.4 cv=VMnQXtPX c=1 sm=1 tr=0 ts=694916a4 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=8jGGn9Z0z0XTtIQmd1MA:9 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: dXfqHyJxh4-odQKNpFrY19Wku_c5FNji X-Proofpoint-GUID: dXfqHyJxh4-odQKNpFrY19Wku_c5FNji X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220090 Content-Type: text/plain; charset="utf-8" Monaco EVK board does not include a camera sensor in its default hardware configuration. Introducing a device tree overlay to support optional integration of the IMX577 sensor via CSIPHY1. Camera reset is handled through an I2C expander, and power is enabled via TLMM GPIO74. An example media-ctl pipeline for the imx577 is: media-ctl --reset media-ctl -V '"imx577 3-001a":0[fmt:SRGGB10/4056x3040 field:none]' media-ctl -V '"msm_csiphy1":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]' media-ctl -l '"msm_csiphy1":1->"msm_csid0":0[1]' media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]' yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video1 Signed-off-by: Nihal Kumar Gupta Co-developed-by: Ravi Shankar Signed-off-by: Ravi Shankar Co-developed-by: Vishal Verma Signed-off-by: Vishal Verma Signed-off-by: Vikram Sharma Reviewed-by: Vladimir Zapolskiy Reviewed-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/Makefile | 4 ++ .../dts/qcom/monaco-evk-camera-imx577.dtso | 66 +++++++++++++++++++ 2 files changed, 70 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 76cf0115a00a..5cf72bdff0b6 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -40,6 +40,10 @@ lemans-evk-camera-dtbs :=3D lemans-evk.dtb lemans-evk-ca= mera.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-camera-csi1-imx577.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-camera.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk.dtb + +monaco-evk-camera-imx577-dtbs :=3D monaco-evk.dtb monaco-evk-camera-imx577= .dtbo +dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk-camera-imx577.dtb + dtb-$(CONFIG_ARCH_QCOM) +=3D msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso b/arch/= arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso new file mode 100644 index 000000000000..0d5ccd020e6e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&camss { + vdda-phy-supply =3D <&vreg_l4a>; + vdda-pll-supply =3D <&vreg_l5a>; + + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + + csiphy1_ep: endpoint { + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&imx577_ep1>; + }; + }; + }; +}; + +&cci1 { + pinctrl-0 =3D <&cci1_0_default>; + pinctrl-1 =3D <&cci1_0_sleep>; + + status =3D "okay"; +}; + +&cci1_i2c0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + camera@1a { + compatible =3D "sony,imx577"; + reg =3D <0x1a>; + + reset-gpios =3D <&expander2 1 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&cam1_default>; + pinctrl-names =3D "default"; + + clocks =3D <&camcc CAM_CC_MCLK1_CLK>; + assigned-clocks =3D <&camcc CAM_CC_MCLK1_CLK>; + assigned-clock-rates =3D <24000000>; + + avdd-supply =3D <&vreg_cam1_2p8>; + + port { + imx577_ep1: endpoint { + link-frequencies =3D /bits/ 64 <600000000>; + data-lanes =3D <1 2 3 4>; + remote-endpoint =3D <&csiphy1_ep>; + }; + }; + }; +}; --=20 2.34.1