From nobody Sat Feb 7 18:21:21 2026 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9093C30DEC6 for ; Mon, 22 Dec 2025 09:37:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766396251; cv=none; b=msiZZmKuJyQFzqjPR5Mg+qlOXFM0s2tvIIES9Jw5dMB23hIvRGSowT2FO6PVFf0FJO+8uysZ94LCbEl3Z4uvLBIiSNeg/H+9tr7amShrfTMnrFCJwF+bRNaV3Q1BrThPNL4fAbmdclJ8NuyMLIw0+7O78ZX8zSnY+niz3rUxdVk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766396251; c=relaxed/simple; bh=c1+ZAMdzh02vWjeiTFaMbNLB9tl3xJthxXA9iBlQ6NI=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=QSCR0bgJ++hzF+bG3W8wytlNI4YR/alPTKLLILU9tijU6TljoIW77d7QhPuIhSXIkPT8dAVmP6AIPoML3kWvOvBC1tNX54QYgUUe+Sdp20EZ+GAYBbzdCOxNvJINlQQk7mFdgppyNxx/I+mH9Q+2Ty1K8dMakvbrMIsadcq48pw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com; spf=pass smtp.mailfrom=bytedance.com; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b=MwDvHCMj; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bytedance.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b="MwDvHCMj" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-2a0b4320665so57697555ad.1 for ; Mon, 22 Dec 2025 01:37:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance.com; s=google; t=1766396249; x=1767001049; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=e+eYOQ9Z1GWGVQPVaVWjHQDJybI+c8ckkcfPVYmzYak=; b=MwDvHCMjChZkRJuerRcUwVfqsZsw3DJ14clm33uY7JcfrzvkuLCCaJDB6W3dZzwSbs kecr9jj4oMu+Su9La/wghpnWU3X0zmuA1i4stXG8iwFkBbLrSnUU5i6ITSOSg4vBGQth KkljutFBB/DYGTB7tMOHJ4SNfnJwpHkJ4NnipDlKrPCAMaZRqBipXsUwp1fq5Hd/t75T YiZDHEr4b4Unp0T38VtzJbftfi7XXZ+/HXAtSO6lvOskc7cDu1dBhdawS3X6hPp9IU4H sA9qAgtoN/T6mVRmXTnJ/QrLrO16bqWcHyuy5bH91KM6D9AdkmuHI8+rzJO+kvBCQrE3 atSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766396249; x=1767001049; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=e+eYOQ9Z1GWGVQPVaVWjHQDJybI+c8ckkcfPVYmzYak=; b=eN1w606JmeYjPAMTW2317AzBjr91FiN9r7Vx3dTU3jA1HnA+B81IvDiUCEe8IeVtmU BZn8qxHHAvxRWW7bKRzw8ACFl6xmBKUz3q+DzxejzyhmWrCtGN83z++qnn1N3nNc+Dg6 9f8Om+HRugrdPWXXcsBTsSxjj0ThN+4S+ooiwapoGbA+QXSfQAVlWqDhctalkQYbHvb+ gdmKYYgLo23OfeSgNXiD7DwCt5UQyDOP9mZbty66rgmqhfZN/JhcsXuxlnA3+nmpn4rB 24crrSFfphJCcdolrDjpVwpDw1Xm/w7H03KkfykuFHZS6hdPGdOK/qghkCdOPFRNwrOW jYzg== X-Forwarded-Encrypted: i=1; AJvYcCXPGYnr6ob1N0sRF21g6IavsO/Qy2JCSo6FCVpLlOdZ04jQKC80iGuM5OXL2s06DSX57uDdNW4W+dRi8lc=@vger.kernel.org X-Gm-Message-State: AOJu0Ywz+PDGK4YZmHd5/KA4clDaM+ylmY5B1Zd8LhpoWOPW7hpo7Its qGvaPE9esqn9It2t9DwXolhkkFpY0nAeDrDslsheaRV1Ba9oyGq3WYO4WF4zIwEkQpQ= X-Gm-Gg: AY/fxX7LNqdtns+V5/r2eUr65OwBhOy0SfbHVw/Gl7bGlJmfLYZeXqR8gM8hCeWNSha uZt6GJqMgpdn5Ma4pDkJHJVwEUCb4cEpbIVAatAYQ6FgKy17Li4n6SI/0jdL7sACOF4QOoaG9Hm Uoh/vwgzhjyoG8LG7c9n1ql8gv4SRHMMU0dbjdjsLemSYS+MGpTSwbAumw0KiecjBfavzuLiMzB B/N2vhGV48OfxLrs9D7YdiVLDNOlKhewbklcLBM9y04De1XC8gfp69xq63FQ8D4KDp/aYWH8eP/ tXAJvKeJQ0DujoSoxa5wF9ISCOXTmY59aelH6apag/tJScqGOOiR3v7EEQttz1CdwsPKbwKd6yO 6TKxEDuxeL8TspIT+ETiHV+GJ3YxO2A4Ska+Bw+an002/pjMmcVjhV/55rcbib6bXk+loCXrAO7 WPxKfEoHBy7agWdbd57ouxrifj4X/3jcItz2QwWigiL8ExvunEpSdu X-Google-Smtp-Source: AGHT+IHbAevZrh677mrcs/s1RBp0r3uPnm7MKiIYh2aKgk+Y2T5BWPJU1+fmAHdSaxWnaMOTu2Gp8g== X-Received: by 2002:a17:902:f607:b0:2a1:4c31:335 with SMTP id d9443c01a7336-2a2f2717b88mr102674405ad.26.1766396248789; Mon, 22 Dec 2025 01:37:28 -0800 (PST) Received: from J9GPGXL7NT.bytedance.net ([139.177.225.255]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a2f3d5d20dsm92611765ad.67.2025.12.22.01.37.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 22 Dec 2025 01:37:28 -0800 (PST) From: Xu Lu To: anup@brainfault.org, atish.patra@linux.dev, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tglx@linutronix.de Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Xu Lu Subject: [PATCH v4] irqchip/riscv-imsic: Adjust the number of available guest irq files Date: Mon, 22 Dec 2025 17:37:18 +0800 Message-ID: <20251222093718.26223-1-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, KVM assumes the minimum of implemented HGEIE bits and "BIT(gc->guest_index_bits) - 1" as the number of guest files available across all CPUs. This will not work when CPUs have different number of guest files because KVM may incorrectly allocate a guest file on a CPU with fewer guest files. To address above, during initialization, we calculate the number of available guest interrupt files according to MMIO resources and constrain the number of guest interrupt files that can be allocated by KVM. Signed-off-by: Xu Lu Acked-by: Thomas Gleixner Reviewed-by: Anup Patel --- arch/riscv/kvm/aia.c | 2 +- drivers/irqchip/irq-riscv-imsic-state.c | 12 +++++++++++- include/linux/irqchip/riscv-imsic.h | 3 +++ 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kvm/aia.c b/arch/riscv/kvm/aia.c index dad3181856600..cac3c2b51d724 100644 --- a/arch/riscv/kvm/aia.c +++ b/arch/riscv/kvm/aia.c @@ -630,7 +630,7 @@ int kvm_riscv_aia_init(void) */ if (gc) kvm_riscv_aia_nr_hgei =3D min((ulong)kvm_riscv_aia_nr_hgei, - BIT(gc->guest_index_bits) - 1); + gc->nr_guest_files); else kvm_riscv_aia_nr_hgei =3D 0; =20 diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-= riscv-imsic-state.c index dc95ad856d80a..cccca38983577 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -794,7 +794,7 @@ static int __init imsic_parse_fwnode(struct fwnode_hand= le *fwnode, =20 int __init imsic_setup_state(struct fwnode_handle *fwnode, void *opaque) { - u32 i, j, index, nr_parent_irqs, nr_mmios, nr_handlers =3D 0; + u32 i, j, index, nr_parent_irqs, nr_mmios, nr_guest_files, nr_handlers = =3D 0; struct imsic_global_config *global; struct imsic_local_config *local; void __iomem **mmios_va =3D NULL; @@ -888,6 +888,7 @@ int __init imsic_setup_state(struct fwnode_handle *fwno= de, void *opaque) } =20 /* Configure handlers for target CPUs */ + global->nr_guest_files =3D BIT(global->guest_index_bits) - 1; for (i =3D 0; i < nr_parent_irqs; i++) { rc =3D imsic_get_parent_hartid(fwnode, i, &hartid); if (rc) { @@ -928,6 +929,15 @@ int __init imsic_setup_state(struct fwnode_handle *fwn= ode, void *opaque) local->msi_pa =3D mmios[index].start + reloff; local->msi_va =3D mmios_va[index] + reloff; =20 + /* + * KVM uses global->nr_guest_files to determine the available guest + * interrupt files on each CPU. Take the minimum number of guest + * interrupt files across all CPUs to avoid KVM incorrectly allocatling + * an unexisted or unmapped guest interrupt file on some CPUs. + */ + nr_guest_files =3D (resource_size(&mmios[index]) - reloff) / IMSIC_MMIO_= PAGE_SZ - 1; + global->nr_guest_files =3D min(global->nr_guest_files, nr_guest_files); + nr_handlers++; } =20 diff --git a/include/linux/irqchip/riscv-imsic.h b/include/linux/irqchip/ri= scv-imsic.h index 7494952c55187..43aed52385008 100644 --- a/include/linux/irqchip/riscv-imsic.h +++ b/include/linux/irqchip/riscv-imsic.h @@ -69,6 +69,9 @@ struct imsic_global_config { /* Number of guest interrupt identities */ u32 nr_guest_ids; =20 + /* Number of guest interrupt files per core */ + u32 nr_guest_files; + /* Per-CPU IMSIC addresses */ struct imsic_local_config __percpu *local; }; --=20 2.20.1