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a=ed25519-sha256; t=1766439100; l=12015; i=royluo@google.com; s=20251120; h=from:subject:message-id; bh=4F8th9oiO4Fos/DSqnEC4PqQSsqscHiBSPgqt6e5PKs=; b=2sNuYq8/97+Of1fH1trQDuzxi27+RhQY4Vf20TLlQc0ViPZaJH7d4gCQMPQ61YYzyYCEaNwne Z3AZKdu4Rl/D4plc5tbg+g88KGTOLl2pJf4Lq64K5Co2XrEXJorz+dF X-Mailer: b4 0.14.2 Message-ID: <20251222-phyb4-v9-2-82c0b671b070@google.com> Subject: [PATCH v9 2/2] phy: Add Google Tensor SoC USB PHY driver From: Roy Luo To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , "=?utf-8?q?Andr=C3=A9_Draszik?=" , Tudor Ambarus , Philipp Zabel , Neil Armstrong Cc: Badhri Jagan Sridharan , Doug Anderson , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Joy Chakraborty , Naveen Kumar , Roy Luo Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Support the USB PHY found on Google Tensor G5 (Laguna). This particular USB PHY supports both high-speed and super-speed operations, and is integrated with the SNPS DWC3 controller that's also on the SoC. This initial patch specifically adds functionality for high-speed. Co-developed-by: Joy Chakraborty Signed-off-by: Joy Chakraborty Co-developed-by: Naveen Kumar Signed-off-by: Naveen Kumar Signed-off-by: Roy Luo --- MAINTAINERS | 1 + drivers/phy/Kconfig | 10 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-google-usb.c | 295 +++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 307 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8a2e94be2f5c5e6e7315bb7bec385798dbd52493..afd0d7484ffe5fa652798c9b3c8= 6ae6d83302382 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10725,6 +10725,7 @@ F: Documentation/devicetree/bindings/phy/google,lga= -usb-phy.yaml F: Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.= yaml F: arch/arm64/boot/dts/exynos/google/ F: drivers/clk/samsung/clk-gs101.c +F: drivers/phy/phy-google-usb.c F: drivers/soc/samsung/gs101-pmu.c F: drivers/phy/samsung/phy-gs101-ufs.c F: include/dt-bindings/clock/google,gs101* diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 678dd0452f0aa0597773433f04d2a9ba77474d2a..5a642e04caeeea9d40ac5837676= 22cff2ef5e80c 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -101,6 +101,16 @@ config PHY_NXP_PTN3222 schemes. It supports all three USB 2.0 data rates: Low Speed, Full Speed and High Speed. =20 +config PHY_GOOGLE_USB + tristate "Google Tensor SoC USB PHY driver" + select GENERIC_PHY + help + Enable support for the USB PHY on Google Tensor SoCs, starting with + the G5 generation (Laguna). This driver provides the PHY interfaces + to interact with the SNPS eUSB2 and USB 3.2/DisplayPort Combo PHY, + both of which are integrated with the DWC3 USB DRD controller. + This driver currently supports USB high-speed. + source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index bfb27fb5a494283d7fd05dd670ebd1b12df8b1a1..aeaaaf988554a24bb572d8b34b5= 4638a6a3aed73 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SNPS_EUSB2) +=3D phy-snps-eusb2.o obj-$(CONFIG_USB_LGM_PHY) +=3D phy-lgm-usb.o obj-$(CONFIG_PHY_AIROHA_PCIE) +=3D phy-airoha-pcie.o obj-$(CONFIG_PHY_NXP_PTN3222) +=3D phy-nxp-ptn3222.o +obj-$(CONFIG_PHY_GOOGLE_USB) +=3D phy-google-usb.o obj-y +=3D allwinner/ \ amlogic/ \ broadcom/ \ diff --git a/drivers/phy/phy-google-usb.c b/drivers/phy/phy-google-usb.c new file mode 100644 index 0000000000000000000000000000000000000000..97e345fdab9b3679e7a76f6957a= e3814ef3420e8 --- /dev/null +++ b/drivers/phy/phy-google-usb.c @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * phy-google-usb.c - Google USB PHY driver + * + * Copyright (C) 2025, Google LLC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define USBCS_USB2PHY_CFG19_OFFSET 0x0 +#define USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV GENMASK(19, 8) + +#define USBCS_USB2PHY_CFG21_OFFSET 0x8 +#define USBCS_USB2PHY_CFG21_PHY_ENABLE BIT(12) +#define USBCS_USB2PHY_CFG21_REF_FREQ_SEL GENMASK(15, 13) +#define USBCS_USB2PHY_CFG21_PHY_TX_DIG_BYPASS_SEL BIT(19) + +#define USBCS_PHY_CFG1_OFFSET 0x28 +#define USBCS_PHY_CFG1_SYS_VBUSVALID BIT(17) + +enum google_usb_phy_id { + GOOGLE_USB2_PHY, + GOOGLE_USB_PHY_NUM, +}; + +struct google_usb_phy_instance { + int index; + struct phy *phy; + int num_clks; + struct clk_bulk_data *clks; + int num_rsts; + struct reset_control_bulk_data *rsts; +}; + +struct google_usb_phy { + struct device *dev; + struct regmap *usb_cfg_regmap; + unsigned int usb2_cfg_offset; + void __iomem *usbdp_top_base; + struct google_usb_phy_instance insts[GOOGLE_USB_PHY_NUM]; + /* + * Protect phy registers from concurrent access, specifically via + * google_usb_set_orientation callback. + */ + struct mutex phy_mutex; + struct typec_switch_dev *sw; + enum typec_orientation orientation; +}; + +static inline struct google_usb_phy *to_google_usb_phy(struct google_usb_p= hy_instance *inst) +{ + return container_of(inst, struct google_usb_phy, insts[inst->index]); +} + +static void set_vbus_valid(struct google_usb_phy *gphy) +{ + u32 reg; + + if (gphy->orientation =3D=3D TYPEC_ORIENTATION_NONE) { + reg =3D readl(gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET); + reg &=3D ~USBCS_PHY_CFG1_SYS_VBUSVALID; + writel(reg, gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET); + } else { + reg =3D readl(gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET); + reg |=3D USBCS_PHY_CFG1_SYS_VBUSVALID; + writel(reg, gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET); + } +} + +static int google_usb_set_orientation(struct typec_switch_dev *sw, + enum typec_orientation orientation) +{ + struct google_usb_phy *gphy =3D typec_switch_get_drvdata(sw); + + dev_dbg(gphy->dev, "set orientation %d\n", orientation); + + gphy->orientation =3D orientation; + + if (pm_runtime_suspended(gphy->dev)) + return 0; + + guard(mutex)(&gphy->phy_mutex); + + set_vbus_valid(gphy); + + return 0; +} + +static int google_usb2_phy_init(struct phy *_phy) +{ + struct google_usb_phy_instance *inst =3D phy_get_drvdata(_phy); + struct google_usb_phy *gphy =3D to_google_usb_phy(inst); + u32 reg; + int ret =3D 0; + + dev_dbg(gphy->dev, "initializing usb2 phy\n"); + + guard(mutex)(&gphy->phy_mutex); + + regmap_read(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_C= FG21_OFFSET, ®); + reg &=3D ~USBCS_USB2PHY_CFG21_PHY_TX_DIG_BYPASS_SEL; + reg &=3D ~USBCS_USB2PHY_CFG21_REF_FREQ_SEL; + reg |=3D FIELD_PREP(USBCS_USB2PHY_CFG21_REF_FREQ_SEL, 0); + regmap_write(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_= CFG21_OFFSET, reg); + + regmap_read(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_C= FG19_OFFSET, ®); + reg &=3D ~USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV; + reg |=3D FIELD_PREP(USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV, 368); + regmap_write(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_= CFG19_OFFSET, reg); + + set_vbus_valid(gphy); + + ret =3D clk_bulk_prepare_enable(inst->num_clks, inst->clks); + if (ret) + return ret; + + ret =3D reset_control_bulk_deassert(inst->num_rsts, inst->rsts); + if (ret) { + clk_bulk_disable_unprepare(inst->num_clks, inst->clks); + return ret; + } + + regmap_read(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_C= FG21_OFFSET, ®); + reg |=3D USBCS_USB2PHY_CFG21_PHY_ENABLE; + regmap_write(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_= CFG21_OFFSET, reg); + + return ret; +} + +static int google_usb2_phy_exit(struct phy *_phy) +{ + struct google_usb_phy_instance *inst =3D phy_get_drvdata(_phy); + struct google_usb_phy *gphy =3D to_google_usb_phy(inst); + u32 reg; + + dev_dbg(gphy->dev, "exiting usb2 phy\n"); + + guard(mutex)(&gphy->phy_mutex); + + regmap_read(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_C= FG21_OFFSET, ®); + reg &=3D ~USBCS_USB2PHY_CFG21_PHY_ENABLE; + regmap_write(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_= CFG21_OFFSET, reg); + + reset_control_bulk_assert(inst->num_rsts, inst->rsts); + clk_bulk_disable_unprepare(inst->num_clks, inst->clks); + + return 0; +} + +static const struct phy_ops google_usb2_phy_ops =3D { + .init =3D google_usb2_phy_init, + .exit =3D google_usb2_phy_exit, +}; + +static struct phy *google_usb_phy_xlate(struct device *dev, + const struct of_phandle_args *args) +{ + struct google_usb_phy *gphy =3D dev_get_drvdata(dev); + + if (args->args[0] >=3D GOOGLE_USB_PHY_NUM) { + dev_err(dev, "invalid PHY index requested from DT\n"); + return ERR_PTR(-ENODEV); + } + return gphy->insts[args->args[0]].phy; +} + +static int google_usb_phy_probe(struct platform_device *pdev) +{ + struct typec_switch_desc sw_desc =3D { }; + struct google_usb_phy_instance *inst; + struct phy_provider *phy_provider; + struct device *dev =3D &pdev->dev; + struct google_usb_phy *gphy; + struct phy *phy; + u32 args[1]; + int ret; + + gphy =3D devm_kzalloc(dev, sizeof(*gphy), GFP_KERNEL); + if (!gphy) + return -ENOMEM; + + dev_set_drvdata(dev, gphy); + gphy->dev =3D dev; + + ret =3D devm_mutex_init(dev, &gphy->phy_mutex); + if (ret) + return ret; + + gphy->usb_cfg_regmap =3D + syscon_regmap_lookup_by_phandle_args(dev->of_node, + "google,usb-cfg-csr", + ARRAY_SIZE(args), args); + if (IS_ERR(gphy->usb_cfg_regmap)) { + return dev_err_probe(dev, PTR_ERR(gphy->usb_cfg_regmap), + "invalid usb cfg csr\n"); + } + + gphy->usb2_cfg_offset =3D args[0]; + + gphy->usbdp_top_base =3D devm_platform_ioremap_resource_byname(pdev, + "usbdp_top"); + if (IS_ERR(gphy->usbdp_top_base)) + return dev_err_probe(dev, PTR_ERR(gphy->usbdp_top_base), + "invalid usbdp top\n"); + + inst =3D &gphy->insts[GOOGLE_USB2_PHY]; + inst->index =3D GOOGLE_USB2_PHY; + phy =3D devm_phy_create(dev, NULL, &google_usb2_phy_ops); + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), + "failed to create usb2 phy instance\n"); + inst->phy =3D phy; + phy_set_drvdata(phy, inst); + + inst->num_clks =3D 2; + inst->clks =3D devm_kcalloc(dev, inst->num_clks, sizeof(*inst->clks), GFP= _KERNEL); + if (!inst->clks) + return -ENOMEM; + inst->clks[0].id =3D "usb2"; + inst->clks[1].id =3D "usb2_apb"; + ret =3D devm_clk_bulk_get(dev, inst->num_clks, inst->clks); + if (ret) + return dev_err_probe(dev, ret, "failed to get u2 phy clks\n"); + + inst->num_rsts =3D 2; + inst->rsts =3D devm_kcalloc(dev, inst->num_rsts, sizeof(*inst->rsts), GFP= _KERNEL); + if (!inst->rsts) + return -ENOMEM; + inst->rsts[0].id =3D "usb2"; + inst->rsts[1].id =3D "usb2_apb"; + ret =3D devm_reset_control_bulk_get_exclusive(dev, inst->num_rsts, inst->= rsts); + if (ret) + return dev_err_probe(dev, ret, "failed to get u2 phy resets\n"); + + phy_provider =3D devm_of_phy_provider_register(dev, google_usb_phy_xlate); + if (IS_ERR(phy_provider)) + return dev_err_probe(dev, PTR_ERR(phy_provider), + "failed to register phy provider\n"); + + pm_runtime_enable(dev); + + sw_desc.fwnode =3D dev_fwnode(dev); + sw_desc.drvdata =3D gphy; + sw_desc.name =3D fwnode_get_name(dev_fwnode(dev)); + sw_desc.set =3D google_usb_set_orientation; + + gphy->sw =3D typec_switch_register(dev, &sw_desc); + if (IS_ERR(gphy->sw)) + return dev_err_probe(dev, PTR_ERR(gphy->sw), + "failed to register typec switch\n"); + + return 0; +} + +static void google_usb_phy_remove(struct platform_device *pdev) +{ + struct google_usb_phy *gphy =3D dev_get_drvdata(&pdev->dev); + + typec_switch_unregister(gphy->sw); + pm_runtime_disable(&pdev->dev); +} + +static const struct of_device_id google_usb_phy_of_match[] =3D { + { + .compatible =3D "google,lga-usb-phy", + }, + { } +}; +MODULE_DEVICE_TABLE(of, google_usb_phy_of_match); + +static struct platform_driver google_usb_phy =3D { + .probe =3D google_usb_phy_probe, + .remove =3D google_usb_phy_remove, + .driver =3D { + .name =3D "google-usb-phy", + .of_match_table =3D google_usb_phy_of_match, + } +}; + +module_platform_driver(google_usb_phy); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Google USB phy driver"); --=20 2.52.0.358.g0dd7633a29-goog