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Mon, 22 Dec 2025 07:15:00 -0800 (PST) From: James Clark Date: Mon, 22 Dec 2025 15:14:38 +0000 Subject: [PATCH v4 13/14] perf cs-etm: Don't hard code config attribute when configuring the event Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251222-james-perf-config-bits-v4-13-0608438186fc@linaro.org> References: <20251222-james-perf-config-bits-v4-0-0608438186fc@linaro.org> In-Reply-To: <20251222-james-perf-config-bits-v4-0-0608438186fc@linaro.org> To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Suzuki K Poulose , Mike Leach , John Garry , Will Deacon , Leo Yan Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, James Clark X-Mailer: b4 0.14.0 These instances of hard coded config attributes are used for configuring and validating the event options. Use the config attribute that's published by the driver by replacing the open coded operations with evsel__get_config_val() and evsel__set_config_if_unset(). Reviewed-by: Ian Rogers Signed-off-by: James Clark --- tools/perf/arch/arm/util/cs-etm.c | 56 +++++++++++++++++++----------------= ---- 1 file changed, 27 insertions(+), 29 deletions(-) diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/c= s-etm.c index 12b28562c2f3..dc3f4e86b075 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -103,13 +103,14 @@ static int cs_etm_validate_context_id(struct perf_pmu= *cs_etm_pmu, struct evsel struct perf_cpu cpu) { int err; - __u64 val; - u64 contextid =3D evsel->core.attr.config & - (perf_pmu__format_bits(cs_etm_pmu, "contextid") | - perf_pmu__format_bits(cs_etm_pmu, "contextid1") | - perf_pmu__format_bits(cs_etm_pmu, "contextid2")); + u64 ctxt, ctxt1, ctxt2; + __u64 trcidr2; =20 - if (!contextid) + evsel__get_config_val(evsel, "contextid", &ctxt); + evsel__get_config_val(evsel, "contextid1", &ctxt1); + evsel__get_config_val(evsel, "contextid2", &ctxt2); + + if (!ctxt && !ctxt1 && !ctxt2) return 0; =20 /* Not supported in etmv3 */ @@ -120,12 +121,11 @@ static int cs_etm_validate_context_id(struct perf_pmu= *cs_etm_pmu, struct evsel } =20 /* Get a handle on TRCIDR2 */ - err =3D cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR2= ], &val); + err =3D cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR2= ], &trcidr2); if (err) return err; =20 - if (contextid & - perf_pmu__format_bits(cs_etm_pmu, "contextid1")) { + if (ctxt1) { /* * TRCIDR2.CIDSIZE, bit [9-5], indicates whether contextID * tracing is supported: @@ -133,15 +133,14 @@ static int cs_etm_validate_context_id(struct perf_pmu= *cs_etm_pmu, struct evsel * 0b00100 Maximum of 32-bit Context ID size. * All other values are reserved. */ - if (BMVAL(val, 5, 9) !=3D 0x4) { + if (BMVAL(trcidr2, 5, 9) !=3D 0x4) { pr_err("%s: CONTEXTIDR_EL1 isn't supported, disable with %s/contextid1= =3D0/\n", CORESIGHT_ETM_PMU_NAME, CORESIGHT_ETM_PMU_NAME); return -EINVAL; } } =20 - if (contextid & - perf_pmu__format_bits(cs_etm_pmu, "contextid2")) { + if (ctxt2) { /* * TRCIDR2.VMIDOPT[30:29] !=3D 0 and * TRCIDR2.VMIDSIZE[14:10] =3D=3D 0b00100 (32bit virtual contextid) @@ -149,7 +148,7 @@ static int cs_etm_validate_context_id(struct perf_pmu *= cs_etm_pmu, struct evsel * virtual context id is < 32bit. * Any value of VMIDSIZE >=3D 4 (i.e, > 32bit) is fine for us. */ - if (!BMVAL(val, 29, 30) || BMVAL(val, 10, 14) < 4) { + if (!BMVAL(trcidr2, 29, 30) || BMVAL(trcidr2, 10, 14) < 4) { pr_err("%s: CONTEXTIDR_EL2 isn't supported, disable with %s/contextid2= =3D0/\n", CORESIGHT_ETM_PMU_NAME, CORESIGHT_ETM_PMU_NAME); return -EINVAL; @@ -163,10 +162,11 @@ static int cs_etm_validate_timestamp(struct perf_pmu = *cs_etm_pmu, struct evsel * struct perf_cpu cpu) { int err; - __u64 val; + u64 val; + __u64 trcidr0; =20 - if (!(evsel->core.attr.config & - perf_pmu__format_bits(cs_etm_pmu, "timestamp"))) + evsel__get_config_val(evsel, "timestamp", &val); + if (!val) return 0; =20 if (cs_etm_get_version(cs_etm_pmu, cpu) =3D=3D CS_ETMV3) { @@ -176,7 +176,7 @@ static int cs_etm_validate_timestamp(struct perf_pmu *c= s_etm_pmu, struct evsel * } =20 /* Get a handle on TRCIRD0 */ - err =3D cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0= ], &val); + err =3D cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0= ], &trcidr0); if (err) return err; =20 @@ -187,10 +187,9 @@ static int cs_etm_validate_timestamp(struct perf_pmu *= cs_etm_pmu, struct evsel * * 0b00110 Implementation supports a maximum timestamp of 48bits. * 0b01000 Implementation supports a maximum timestamp of 64bits. */ - val &=3D GENMASK(28, 24); - if (!val) { + trcidr0 &=3D GENMASK(28, 24); + if (!trcidr0) return -EINVAL; - } =20 return 0; } @@ -273,16 +272,19 @@ static int cs_etm_parse_snapshot_options(struct auxtr= ace_record *itr, return 0; } =20 +/* + * If the sink name format "@sink_name" is used, lookup the sink by name t= o convert to + * "sinkid=3Dsink_hash" format. If the user has already manually provided = a hash then + * "sinkid" isn't overwritten. If neither are provided then the driver wil= l pick the best + * sink. + */ static int cs_etm_set_sink_attr(struct perf_pmu *pmu, struct evsel *evsel) { char msg[BUFSIZ], path[PATH_MAX], *sink; struct evsel_config_term *term; - int ret =3D -EINVAL; u32 hash; - - if (evsel->core.attr.config2 & GENMASK(31, 0)) - return 0; + int ret; =20 list_for_each_entry(term, &evsel->config_terms, list) { if (term->type !=3D EVSEL__CONFIG_TERM_DRV_CFG) @@ -305,14 +307,10 @@ static int cs_etm_set_sink_attr(struct perf_pmu *pmu, return ret; } =20 - evsel->core.attr.config2 |=3D hash; + evsel__set_config_if_unset(evsel, "sinkid", hash); return 0; } =20 - /* - * No sink was provided on the command line - allow the CoreSight - * system to look for a default - */ return 0; } =20 --=20 2.34.1