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[34.76.221.62]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4324eaa4749sm23071258f8f.37.2025.12.22.08.30.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Dec 2025 08:30:36 -0800 (PST) From: Tudor Ambarus Date: Mon, 22 Dec 2025 16:30:09 +0000 Subject: [PATCH v4 5/5] arm64: dts: exynos: gs101: add OTP node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251222-gs101-chipid-v4-5-aa8e20ce7bb3@linaro.org> References: <20251222-gs101-chipid-v4-0-aa8e20ce7bb3@linaro.org> In-Reply-To: <20251222-gs101-chipid-v4-0-aa8e20ce7bb3@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Srinivas Kandagatla Cc: Krzysztof Kozlowski , semen.protsenko@linaro.org, willmcvicker@google.com, kernel-team@android.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766421032; l=992; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=gIK455PpaZxVuvfXEfRmg3pjfE8OD78NBBkTr9I0h8k=; b=Q9f7t/RCDmUJ75u/2IeLiK62QNaGafJ83CtoJmOgrtY4/ERxZXfJ3qSw/mnSIdVKgntbdJN2k VlgZHF4bS6DBaN5xNMz0xRTYlAR8/L3MPQHerwTH77W0JbgdWIwFRme X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add the OTP controller node. Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index 9b38c2248016aa65293c0abf9ccaf20857d89693..e078344c9e3e558aa5d58845d0f= a2849832b857b 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -571,6 +571,14 @@ soc: soc@0 { #size-cells =3D <1>; ranges =3D <0x0 0x0 0x0 0x40000000>; =20 + efuse@10000000 { + compatible =3D "google,gs101-otp"; + reg =3D <0x10000000 0xf084>; + clocks =3D <&cmu_misc CLK_GOUT_MISC_OTP_CON_TOP_PCLK>; + clock-names =3D "pclk"; + interrupts =3D ; + }; + cmu_misc: clock-controller@10010000 { compatible =3D "google,gs101-cmu-misc"; reg =3D <0x10010000 0x10000>; --=20 2.52.0.322.g1dd061c0dc-goog