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From: Marijn Suijten <marijn.suijten@somainline.org>
Date: Mon, 22 Dec 2025 00:32:13 +0100
Subject: [PATCH v2 07/11] drm/panel: Add panel driver for Samsung SOFEF03-M
 DDIC
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Message-Id: <20251222-drm-panels-sony-v2-7-82a87465d163@somainline.org>
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To: Neil Armstrong <neil.armstrong@linaro.org>,
 Sam Ravnborg <sam@ravnborg.org>, David Airlie <airlied@gmail.com>,
 Rob Herring <robh+dt@kernel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
 Conor Dooley <conor+dt@kernel.org>, Andy Gross <agross@kernel.org>,
 Bjorn Andersson <andersson@kernel.org>,
 Jessica Zhang <jesszhan0024@gmail.com>,
 Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
 Maxime Ripard <mripard@kernel.org>, Thomas Zimmermann <tzimmermann@suse.de>,
 Simona Vetter <simona@ffwll.ch>, Casey Connolly <casey.connolly@linaro.org>,
 Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,
 Simona Vetter <simona.vetter@ffwll.ch>
Cc: ~postmarketos/upstreaming@lists.sr.ht,
 AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>,
 Martin Botka <martin.botka@somainline.org>,
 Jami Kettunen <jami.kettunen@somainline.org>,
 dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
 devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
 Abhinav Kumar <quic_abhinavk@quicinc.com>,
 Kuogee Hsieh <quic_khsieh@quicinc.com>,
 Jessica Zhang <quic_jesszhan@quicinc.com>,
 AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
 Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
 Marijn Suijten <marijn.suijten@somainline.org>,
 Konrad Dybcio <konradybcio@kernel.org>, Dmitry Baryshkov <lumag@kernel.org>,
 Konrad Dybcio <konradybcio@kernel.org>
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The SOFEF03-M Display-Driver-IC is paired with a amb609vp01 panel on
the Sony Xperia 5 II and amb609vp04 panel on the Sony Xperia 5 III. It
requires Display Stream Compression 1.1 which allows the panels to run
at 120Hz, even though a 60Hz mode is available too.

Downstream porch values are retained; despite not being used in
command-mode they are useful to artificially bump the clock values to
account for "transfer overhead" while that calculation is still missing
from the MSM DSI host driver.

Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
---
 MAINTAINERS                                   |   1 +
 drivers/gpu/drm/panel/Kconfig                 |  16 ++
 drivers/gpu/drm/panel/Makefile                |   1 +
 drivers/gpu/drm/panel/panel-samsung-sofef03.c | 373 ++++++++++++++++++++++=
++++
 4 files changed, 391 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index e48dd7f5a115..28135743ca0c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8204,6 +8204,7 @@ DRM DRIVER FOR SAMSUNG SOFEF03 DDIC
 M:	Marijn Suijten <marijn.suijten@somainline.org>
 S:	Maintained
 F:	Documentation/devicetree/bindings/display/panel/samsung,sofef03-m.yaml
+F:	drivers/gpu/drm/panel/panel-samsung-sofef03.c
=20
 DRM DRIVER FOR SHARP MEMORY LCD
 M:	Alex Lanzano <lanzano.alex@gmail.com>
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 2f06b48dfb89..1f148bc5b068 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -953,6 +953,22 @@ config DRM_PANEL_SAMSUNG_SOFEF01
=20
 	  This Display-IC features a fixed 1080x2520@60 mode.
=20
+config DRM_PANEL_SAMSUNG_SOFEF03
+	tristate "Samsung SOFEF03-M DSI cmd mode panels"
+	depends on GPIOLIB
+	depends on OF
+	depends on DRM_MIPI_DSI
+	depends on BACKLIGHT_CLASS_DEVICE
+	select DRM_DISPLAY_DSC_HELPER
+	select DRM_DISPLAY_HELPER
+	help
+	  Say Y or M here if you want to enable support for the Samsung 6.1" AMOL=
ED
+	  DSI command mode panel found in the Sony Xperia 5 II and Sony Xperia 5 =
III
+	  smartphones (both amb609vp01 panel).
+
+	  This Display-IC uses Display Stream Compression 1.1 and features a
+	  1080x2520@60 and 1080x2520@120 mode.
+
 config DRM_PANEL_SEIKO_43WVF1G
 	tristate "Seiko 43WVF1G panel"
 	depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index cbd9ef23b8d8..a9636f5f433a 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -95,6 +95,7 @@ obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0) +=3D panel-samsun=
g-s6e8aa0.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E8AA5X01_AMS561RA01) +=3D panel-samsung-s=
6e8aa5x01-ams561ra01.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_SOFEF00) +=3D panel-samsung-sofef00.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_SOFEF01) +=3D panel-samsung-sofef01.o
+obj-$(CONFIG_DRM_PANEL_SAMSUNG_SOFEF03) +=3D panel-samsung-sofef03.o
 obj-$(CONFIG_DRM_PANEL_SEIKO_43WVF1G) +=3D panel-seiko-43wvf1g.o
 obj-$(CONFIG_DRM_PANEL_SHARP_LQ079L1SX01) +=3D panel-sharp-lq079l1sx01.o
 obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) +=3D panel-sharp-lq101r1sx01.o
diff --git a/drivers/gpu/drm/panel/panel-samsung-sofef03.c b/drivers/gpu/dr=
m/panel/panel-samsung-sofef03.c
new file mode 100644
index 000000000000..f9399aab0623
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-samsung-sofef03.c
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022 Konrad Dybcio <konrad.dybcio@linaro.org>
+ * Copyright (c) 2023 Marijn Suijten <marijn.suijten@somainline.org>
+ *
+ * Based on the following Sony downstream DTS command sequences:
+ * - Xperia 5 II (edo pdx206): https://github.com/sonyxperiadev/kernel-cop=
yleft-dts/blob/58.2.A.10.xxx/somc/dsi-panel-sofef03_m-fhd_plus.dtsi
+ *  - Xperia 5 III (sagami pdx214): https://github.com/sonyxperiadev/kerne=
l-copyleft-dts/blob/61.2.A.0.xxx/somc/dsi-panel-sofef03_m-amb609vp01-fhd_pl=
us.dtsi
+ */
+
+#include <linux/backlight.h>
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/regulator/consumer.h>
+
+#include <video/mipi_display.h>
+
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_modes.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/display/drm_dsc.h>
+#include <drm/display/drm_dsc_helper.h>
+
+#define WRITE_CONTROL_DISPLAY_BACKLIGHT BIT(5)
+
+/*
+ * TODO: This should be communicated via the mode when .prepare
+ * receives atomic commit info
+ */
+static const bool enable_120hz =3D true;
+
+struct samsung_sofef03_m {
+	struct drm_panel panel;
+	struct mipi_dsi_device *dsi;
+	struct drm_dsc_config dsc;
+	struct regulator *vddio, *vci;
+	struct gpio_desc *reset_gpio;
+};
+
+static inline struct samsung_sofef03_m *
+to_samsung_sofef03_m(struct drm_panel *panel)
+{
+	return container_of(panel, struct samsung_sofef03_m, panel);
+}
+
+static void samsung_sofef03_m_reset(struct samsung_sofef03_m *ctx)
+{
+	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+	usleep_range(10000, 11000);
+	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+	usleep_range(10000, 11000);
+	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+	usleep_range(10000, 11000);
+}
+
+static int samsung_sofef03_m_program(struct samsung_sofef03_m *ctx)
+{
+	struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D ctx->dsi };
+
+	dsi_ctx.dsi->mode_flags |=3D MIPI_DSI_MODE_LPM;
+
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9d, 0x01);
+
+	mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+	mipi_dsi_msleep(&dsi_ctx, 10);
+
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x5a, 0x5a);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x09);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd5, 0x00, 0x00, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xa5, 0xa5);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x5a, 0x5a);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x08);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xee, 0x00, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xa5, 0xa5);
+
+	mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+	mipi_dsi_dcs_set_column_address_multi(&dsi_ctx, 0, 1080 - 1);
+	mipi_dsi_dcs_set_page_address_multi(&dsi_ctx, 0, 2520 - 1);
+
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x5a, 0x5a);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xdf, 0x83);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xa5, 0xa5);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x5a, 0x5a);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe6, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xa5, 0xa5);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x5a, 0x5a);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x02);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xec, 0x02, 0x00, 0x1c, 0x1c);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x0c);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xec, 0x01, 0x19);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xa5, 0xa5);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY,
+				     WRITE_CONTROL_DISPLAY_BACKLIGHT);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x5a, 0x5a);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc2, 0x2d, 0x27);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xa5, 0xa5);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x5a, 0x5a);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, enable_120hz ? 0x10 : 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xa5, 0xa5);
+	mipi_dsi_msleep(&dsi_ctx, 110);
+
+	return dsi_ctx.accum_err;
+}
+
+static int samsung_sofef03_m_prepare(struct drm_panel *panel)
+{
+	struct samsung_sofef03_m *ctx =3D to_samsung_sofef03_m(panel);
+	struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D ctx->dsi };
+	struct drm_dsc_picture_parameter_set pps;
+	struct device *dev =3D &ctx->dsi->dev;
+	int ret;
+
+	ret =3D regulator_enable(ctx->vddio);
+	if (ret < 0) {
+		dev_err(dev, "Failed to enable vddio regulator: %d\n", ret);
+		return ret;
+	}
+
+	ret =3D regulator_enable(ctx->vci);
+	if (ret < 0) {
+		dev_err(dev, "Failed to enable vci regulator: %d\n", ret);
+		regulator_disable(ctx->vddio);
+		return ret;
+	}
+
+	samsung_sofef03_m_reset(ctx);
+
+	ret =3D samsung_sofef03_m_program(ctx);
+	if (ret < 0) {
+		dev_err(dev, "Failed to send on command sequence: %d\n", ret);
+		goto fail;
+	}
+
+	drm_dsc_pps_payload_pack(&pps, &ctx->dsc);
+
+	mipi_dsi_picture_parameter_set_multi(&dsi_ctx, &pps);
+	mipi_dsi_compression_mode_multi(&dsi_ctx, true);
+	mipi_dsi_msleep(&dsi_ctx, 28);
+
+	ret =3D dsi_ctx.accum_err;
+
+	if (ret < 0)
+		goto fail;
+
+	return 0;
+
+fail:
+	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+	regulator_disable(ctx->vci);
+	regulator_disable(ctx->vddio);
+	return ret;
+}
+
+static int samsung_sofef03_m_enable(struct drm_panel *panel)
+{
+	struct samsung_sofef03_m *ctx =3D to_samsung_sofef03_m(panel);
+	struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D ctx->dsi };
+
+	mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+
+	return dsi_ctx.accum_err;
+}
+
+static int samsung_sofef03_m_disable(struct drm_panel *panel)
+{
+	struct samsung_sofef03_m *ctx =3D to_samsung_sofef03_m(panel);
+	struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D ctx->dsi };
+
+	mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
+	mipi_dsi_msleep(&dsi_ctx, 20);
+
+	return dsi_ctx.accum_err;
+}
+
+static int samsung_sofef03_m_unprepare(struct drm_panel *panel)
+{
+	struct samsung_sofef03_m *ctx =3D to_samsung_sofef03_m(panel);
+	struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D ctx->dsi };
+
+	mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
+	mipi_dsi_msleep(&dsi_ctx, 100);
+
+	ctx->dsi->mode_flags &=3D ~MIPI_DSI_MODE_LPM;
+
+	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+	regulator_disable(ctx->vci);
+	regulator_disable(ctx->vddio);
+
+	return dsi_ctx.accum_err;
+}
+
+/*
+ * TODO: These porch values are unused for command-mode panels, but curren=
tly
+ * used to artificially bump the clocks to account for transfer overhead.
+ */
+static const struct drm_display_mode samsung_sofef03_m_60hz_mode =3D {
+	.clock =3D (1080 + 156 + 8 + 8) * (2520 + 2393 + 8 + 8) * 60 / 1000,
+	.hdisplay =3D 1080,
+	.hsync_start =3D 1080 + 156,
+	.hsync_end =3D 1080 + 156 + 8,
+	.htotal =3D 1080 + 156 + 8 + 8,
+	.vdisplay =3D 2520,
+	.vsync_start =3D 2520 + 2393,
+	.vsync_end =3D 2520 + 2393 + 8,
+	.vtotal =3D 2520 + 2393 + 8 + 8,
+	.width_mm =3D 61,
+	.height_mm =3D 142,
+	.type =3D DRM_MODE_TYPE_DRIVER,
+};
+
+static const struct drm_display_mode samsung_sofef03_m_120hz_mode =3D {
+	.clock =3D (1080 + 56 + 8 + 8) * (2520 + 499 + 8 + 8) * 120 / 1000,
+	.hdisplay =3D 1080,
+	.hsync_start =3D 1080 + 56,
+	.hsync_end =3D 1080 + 56 + 8,
+	.htotal =3D 1080 + 56 + 8 + 8,
+	.vdisplay =3D 2520,
+	.vsync_start =3D 2520 + 499,
+	.vsync_end =3D 2520 + 499 + 8,
+	.vtotal =3D 2520 + 499 + 8 + 8,
+	.width_mm =3D 61,
+	.height_mm =3D 142,
+	.type =3D DRM_MODE_TYPE_DRIVER,
+};
+
+static int samsung_sofef03_m_get_modes(struct drm_panel *panel,
+				       struct drm_connector *connector)
+{
+	if (enable_120hz)
+		return drm_connector_helper_get_modes_fixed(
+			connector, &samsung_sofef03_m_120hz_mode);
+	else
+		return drm_connector_helper_get_modes_fixed(
+			connector, &samsung_sofef03_m_60hz_mode);
+}
+
+static const struct drm_panel_funcs samsung_sofef03_m_panel_funcs =3D {
+	.prepare =3D samsung_sofef03_m_prepare,
+	.enable =3D samsung_sofef03_m_enable,
+	.disable =3D samsung_sofef03_m_disable,
+	.unprepare =3D samsung_sofef03_m_unprepare,
+	.get_modes =3D samsung_sofef03_m_get_modes,
+};
+
+static int samsung_sofef03_m_bl_update_status(struct backlight_device *bl)
+{
+	struct mipi_dsi_device *dsi =3D bl_get_data(bl);
+	u16 brightness =3D backlight_get_brightness(bl);
+
+	/* HACK: Setting anything below 0x100 makes the panel go black */
+	if (brightness !=3D 0 && brightness < 256)
+		brightness =3D 256;
+
+	return mipi_dsi_dcs_set_display_brightness_large(dsi, brightness);
+}
+
+static const struct backlight_ops samsung_sofef03_m_bl_ops =3D {
+	.update_status =3D samsung_sofef03_m_bl_update_status,
+};
+
+static int samsung_sofef03_m_probe(struct mipi_dsi_device *dsi)
+{
+	const struct backlight_properties props =3D {
+		.type =3D BACKLIGHT_RAW,
+		.brightness =3D 256,
+		.max_brightness =3D 1023,
+	};
+	struct device *dev =3D &dsi->dev;
+	struct samsung_sofef03_m *ctx;
+	int ret;
+
+	ctx =3D devm_drm_panel_alloc(dev, struct samsung_sofef03_m, panel,
+				   &samsung_sofef03_m_panel_funcs,
+				   DRM_MODE_CONNECTOR_DSI);
+	if (IS_ERR(ctx))
+		return PTR_ERR(ctx);
+
+	ctx->vddio =3D devm_regulator_get(dev, "vddio");
+	if (IS_ERR(ctx->vddio))
+		return dev_err_probe(dev, PTR_ERR(ctx->vddio),
+				     "Failed to get vddio regulator\n");
+
+	ctx->vci =3D devm_regulator_get(dev, "vci");
+	if (IS_ERR(ctx->vci))
+		return dev_err_probe(dev, PTR_ERR(ctx->vci),
+				     "Failed to get vci regulator\n");
+
+	ctx->reset_gpio =3D devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
+	if (IS_ERR(ctx->reset_gpio))
+		return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio),
+				     "Failed to get reset-gpios\n");
+
+	ctx->dsi =3D dsi;
+	mipi_dsi_set_drvdata(dsi, ctx);
+
+	dsi->lanes =3D 4;
+	dsi->format =3D MIPI_DSI_FMT_RGB888;
+	dsi->mode_flags =3D MIPI_DSI_CLOCK_NON_CONTINUOUS;
+
+	ctx->panel.prepare_prev_first =3D true;
+
+	ctx->panel.backlight =3D devm_backlight_device_register(
+		dev, dev_name(dev), dev, dsi,
+		&samsung_sofef03_m_bl_ops,
+		&props);
+	if (IS_ERR(ctx->panel.backlight))
+		return dev_err_probe(dev, PTR_ERR(ctx->panel.backlight),
+				     "Failed to create backlight\n");
+
+	drm_panel_add(&ctx->panel);
+
+	/* This panel only supports DSC; unconditionally enable it */
+	dsi->dsc =3D &ctx->dsc;
+
+	ctx->dsc.dsc_version_major =3D 1;
+	ctx->dsc.dsc_version_minor =3D 1;
+
+	ctx->dsc.slice_height =3D 30;
+	ctx->dsc.slice_width =3D 540;
+	ctx->dsc.slice_count =3D 2;
+	ctx->dsc.bits_per_component =3D 8;
+	ctx->dsc.bits_per_pixel =3D 8 << 4; /* 4 fractional bits */
+	ctx->dsc.block_pred_enable =3D true;
+
+	ret =3D mipi_dsi_attach(dsi);
+	if (ret < 0) {
+		dev_err(dev, "Failed to attach to DSI host: %d\n", ret);
+		drm_panel_remove(&ctx->panel);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void samsung_sofef03_m_remove(struct mipi_dsi_device *dsi)
+{
+	struct samsung_sofef03_m *ctx =3D mipi_dsi_get_drvdata(dsi);
+	int ret;
+
+	ret =3D mipi_dsi_detach(dsi);
+	if (ret < 0)
+		dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret);
+
+	drm_panel_remove(&ctx->panel);
+}
+
+static const struct of_device_id samsung_sofef03_m_of_match[] =3D {
+	/* Sony Xperia 5 II */
+	{ .compatible =3D "samsung,sofef03-m-amb609vp01" },
+	/* Sony Xperia 5 III */
+	{ .compatible =3D "samsung,sofef03-m-amb609vp04" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, samsung_sofef03_m_of_match);
+
+static struct mipi_dsi_driver samsung_sofef03_m_driver =3D {
+	.probe =3D samsung_sofef03_m_probe,
+	.remove =3D samsung_sofef03_m_remove,
+	.driver =3D {
+		.name =3D "panel-samsung-sofef03-m",
+		.of_match_table =3D samsung_sofef03_m_of_match,
+	},
+};
+module_mipi_dsi_driver(samsung_sofef03_m_driver);
+
+MODULE_AUTHOR("Konrad Dybcio <konrad.dybcio@linaro.org>");
+MODULE_AUTHOR("Marijn Suijten <marijn.suijten@somainline.org>");
+MODULE_DESCRIPTION("DRM panel driver for Samsung SOFEF03-M Display-Driver-=
IC panels");
+MODULE_LICENSE("GPL");

--=20
2.52.0