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Mon, 22 Dec 2025 02:22:26 -0800 (PST) From: Peter Griffin Date: Mon, 22 Dec 2025 10:22:13 +0000 Subject: [PATCH v7 2/4] arm64: dts: exynos: gs101: add samsung,sysreg property to CMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251222-automatic-clocks-v7-2-fec86fa89874@linaro.org> References: <20251222-automatic-clocks-v7-0-fec86fa89874@linaro.org> In-Reply-To: <20251222-automatic-clocks-v7-0-fec86fa89874@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Sam Protsenko , Sylwester Nawrocki , Chanwoo Choi Cc: Will McVicker , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, kernel-team@android.com, Peter Griffin , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA With the exception of cmu_top, each CMU has a corresponding sysreg bank that contains the BUSCOMPONENT_DRCG_EN and optional MEMCLK registers. The BUSCOMPONENT_DRCG_EN register enables dynamic root clock gating of bus components and MEMCLK gates the sram clock. Now the clock driver supports automatic clock mode, provide the samsung,sysreg property so the driver can enable dynamic root clock gating of bus components and gate sram clock. Note without the property specified the driver simply falls back to previous behaviour of not configuring these registers so it is not an ABI break. Signed-off-by: Peter Griffin --- Changes in v4: - Update commit message (Peter) --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index 9b38c2248016aa65293c0abf9ccaf20857d89693..2e25eeb0c2590b99ef98c7bdac3= caa0c34161706 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -578,6 +578,7 @@ cmu_misc: clock-controller@10010000 { clocks =3D <&cmu_top CLK_DOUT_CMU_MISC_BUS>, <&cmu_top CLK_DOUT_CMU_MISC_SSS>; clock-names =3D "bus", "sss"; + samsung,sysreg =3D <&sysreg_misc>; }; =20 sysreg_misc: syscon@10030000 { @@ -671,6 +672,7 @@ cmu_peric0: clock-controller@10800000 { <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; clock-names =3D "oscclk", "bus", "ip"; + samsung,sysreg =3D <&sysreg_peric0>; }; =20 sysreg_peric0: syscon@10820000 { @@ -1217,6 +1219,7 @@ cmu_peric1: clock-controller@10c00000 { <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; clock-names =3D "oscclk", "bus", "ip"; + samsung,sysreg =3D <&sysreg_peric1>; }; =20 sysreg_peric1: syscon@10c20000 { @@ -1575,6 +1578,7 @@ cmu_hsi0: clock-controller@11000000 { <&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>; clock-names =3D "oscclk", "bus", "dpgtc", "usb31drd", "usbdpdbg"; + samsung,sysreg =3D <&sysreg_hsi0>; }; =20 sysreg_hsi0: syscon@11020000 { @@ -1646,6 +1650,7 @@ cmu_hsi2: clock-controller@14400000 { <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>, <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>; clock-names =3D "oscclk", "bus", "pcie", "ufs", "mmc"; + samsung,sysreg =3D <&sysreg_hsi2>; }; =20 sysreg_hsi2: syscon@14420000 { @@ -1706,6 +1711,7 @@ cmu_apm: clock-controller@17400000 { =20 clocks =3D <&ext_24_5m>; clock-names =3D "oscclk"; + samsung,sysreg =3D <&sysreg_apm>; }; =20 sysreg_apm: syscon@17420000 { --=20 2.52.0.351.gbe84eed79e-goog