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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7ff7e892926sm9070130b3a.66.2025.12.21.22.02.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Dec 2025 22:02:56 -0800 (PST) From: Jie Gan Date: Mon, 22 Dec 2025 14:02:21 +0800 Subject: [PATCH v6 1/4] coresight: tpda: add sysfs nodes for tpda cross-trigger configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251222-add_sysfs_nodes_to_configure_tpda-v6-1-b27143d45c86@oss.qualcomm.com> References: <20251222-add_sysfs_nodes_to_configure_tpda-v6-0-b27143d45c86@oss.qualcomm.com> In-Reply-To: <20251222-add_sysfs_nodes_to_configure_tpda-v6-0-b27143d45c86@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Tingwei Zhang Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jie Gan , Tao Zhang X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766383369; l=10025; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=5iJlQIoDWyy/yMLiYfQHee+qPvXguqsKK6vOAMkX94A=; b=eMynoqargOk5K7grTg75zh8VPvPDVcdZbDW1eA9kSBmGEfuO6koY2ChL2iPfOZoJsIJbTrdaD Znvg8J3wCGlDP93cBr0DRChPyEnNFSOFyRe6G/bysiz/vR0OdxHH8Ik X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA1MiBTYWx0ZWRfX1spVkCBAwQZF Z0Ds0RdoJ23IbKx+6oBLT4hma/4QCdCL4P3J/Uk1fHQgS+p28pIyOuCTeFu0Sfw5eUrjo6rcUvU UQql4EsAqxDO2zReqX2aiWnBy5DxG6I9tayhjnRBJuBVYh99+hC6q/IAa4+pis80wFZm3r0jhDK IYfzmD96wpa49OCd+xePbmgNG61Q6G7VMUEDsW6zU844KlLNP5dsckeEQiaUvZPdWAAZcCB29Ts tV0GOnSYArO1mH0qEPn552xzL5V33zmv9sInoKOASDHlQaXvVfM7pKbIGQY4kTHBwyhZVd5BUgp aOkiOIvRk8SGw1N/5I4n6Kf+r60ANQcPI+j/BUvgtJQNPEpRUIt86ESCztTgB19843+Wz8nEURs sEZisCWk3F8+btKoaAP9KixOUCtxSBokOhsYvcWmVODSQ3zERSVXJ255i8KhIiThlw4v1zMedKu 5zrAGSPnao2oUVPX/lg== X-Authority-Analysis: v=2.4 cv=VMnQXtPX c=1 sm=1 tr=0 ts=6948df12 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=yIbM8MDk91bntAnC_RsA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: LaDkUWwT4tmJF9N81FQV6OJ5kcpJSLnm X-Proofpoint-GUID: LaDkUWwT4tmJF9N81FQV6OJ5kcpJSLnm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220052 From: Tao Zhang Introduce sysfs nodes to configure cross-trigger parameters for TPDA. These registers define the characteristics of cross-trigger packets, including generation frequency and flag values. Signed-off-by: Tao Zhang Reviewed-by: James Clark Co-developed-by: Jie Gan Signed-off-by: Jie Gan --- .../ABI/testing/sysfs-bus-coresight-devices-tpda | 35 +++++++ drivers/hwtracing/coresight/coresight-tpda.c | 109 +++++++++++++++++= +++- drivers/hwtracing/coresight/coresight-tpda.h | 63 +++++++++++- 3 files changed, 200 insertions(+), 7 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/D= ocumentation/ABI/testing/sysfs-bus-coresight-devices-tpda new file mode 100644 index 000000000000..735ce0e494da --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda @@ -0,0 +1,35 @@ +What: /sys/bus/coresight/devices//trig_async_enable +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Enable/disable cross trigger synchronization sequence interface. + +What: /sys/bus/coresight/devices//trig_flag_ts_enable +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Enable/disable cross trigger FLAG packet request interface. + +What: /sys/bus/coresight/devices//trig_freq_enable +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Enable/disable cross trigger FREQ packet request interface. + +What: /sys/bus/coresight/devices//freq_ts_enable +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Enable/disable the timestamp for all FREQ packets. + +What: /sys/bus/coresight/devices//cmbchan_mode +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Configure the CMB/MCMB channel mode for all enabled ports. + Value 0 means raw channel mapping mode. Value 1 means channel pair marki= ng mode. diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtraci= ng/coresight/coresight-tpda.c index 3a3825d27f86..2186223ad33e 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -137,12 +137,32 @@ static int tpda_get_element_size(struct tpda_drvdata = *drvdata, /* Settings pre enabling port control register */ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) { - u32 val; + u32 val =3D 0; =20 - val =3D readl_relaxed(drvdata->base + TPDA_CR); - val &=3D ~TPDA_CR_ATID; val |=3D FIELD_PREP(TPDA_CR_ATID, drvdata->atid); + if (drvdata->trig_async) + val |=3D TPDA_CR_SRIE; + + if (drvdata->trig_flag_ts) + val |=3D TPDA_CR_FLRIE; + + if (drvdata->trig_freq) + val |=3D TPDA_CR_FRIE; + + if (drvdata->freq_ts) + val |=3D TPDA_CR_FREQTS; + + if (drvdata->cmbchan_mode) + val |=3D TPDA_CR_CMBCHANMODE; + writel_relaxed(val, drvdata->base + TPDA_CR); + + /* + * If FLRIE bit is set, set the master and channel + * id as zero + */ + if (drvdata->trig_flag_ts) + writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); } =20 static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) @@ -258,6 +278,87 @@ static const struct coresight_ops tpda_cs_ops =3D { .link_ops =3D &tpda_link_ops, }; =20 +/* Read cross-trigger register member */ +static ssize_t tpda_trig_sysfs_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpda_trig_sysfs_attribute *tpda_attr =3D + container_of(attr, struct tpda_trig_sysfs_attribute, attr); + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + guard(spinlock)(&drvdata->spinlock); + switch (tpda_attr->mem) { + case FREQTS: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->freq_ts); + case FRIE: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_freq); + case FLRIE: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_flag_ts); + case SRIE: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_async); + case CMBCHANMODE: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->cmbchan_mode); + + } + return -EINVAL; +} + +static ssize_t tpda_trig_sysfs_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpda_trig_sysfs_attribute *tpda_attr =3D + container_of(attr, struct tpda_trig_sysfs_attribute, attr); + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + switch (tpda_attr->mem) { + case FREQTS: + drvdata->freq_ts =3D !!val; + break; + case FRIE: + drvdata->trig_freq =3D !!val; + break; + case FLRIE: + drvdata->trig_flag_ts =3D !!val; + break; + case SRIE: + drvdata->trig_async =3D !!val; + break; + case CMBCHANMODE: + drvdata->cmbchan_mode =3D !!val; + break; + default: + return -EINVAL; + } + + return size; +} + +static struct attribute *tpda_attrs[] =3D { + tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), + tpda_trig_sysfs_rw(trig_freq_enable, FRIE), + tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), + tpda_trig_sysfs_rw(trig_async_enable, SRIE), + tpda_trig_sysfs_rw(cmbchan_mode, CMBCHANMODE), + NULL, +}; + +static struct attribute_group tpda_attr_grp =3D { + .attrs =3D tpda_attrs, +}; + +static const struct attribute_group *tpda_attr_grps[] =3D { + &tpda_attr_grp, + NULL, +}; + static int tpda_init_default_data(struct tpda_drvdata *drvdata) { int atid; @@ -273,6 +374,7 @@ static int tpda_init_default_data(struct tpda_drvdata *= drvdata) return atid; =20 drvdata->atid =3D atid; + drvdata->freq_ts =3D true; return 0; } =20 @@ -316,6 +418,7 @@ static int tpda_probe(struct amba_device *adev, const s= truct amba_id *id) desc.ops =3D &tpda_cs_ops; desc.pdata =3D adev->dev.platform_data; desc.dev =3D &adev->dev; + desc.groups =3D tpda_attr_grps; desc.access =3D CSDEV_ACCESS_IOMEM(base); drvdata->csdev =3D coresight_register(&desc); if (IS_ERR(drvdata->csdev)) diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtraci= ng/coresight/coresight-tpda.h index c6af3d2da3ef..c93732e04af2 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023,2025 Qualcomm Innovation Center, Inc. All rights res= erved. */ =20 #ifndef _CORESIGHT_CORESIGHT_TPDA_H @@ -8,6 +8,25 @@ =20 #define TPDA_CR (0x000) #define TPDA_Pn_CR(n) (0x004 + (n * 4)) +#define TPDA_FPID_CR (0x084) + +/* Cross trigger FREQ packets timestamp bit */ +#define TPDA_CR_FREQTS BIT(2) +/* Cross trigger FREQ packet request bit */ +#define TPDA_CR_FRIE BIT(3) +/* Cross trigger FLAG packet request interface bit */ +#define TPDA_CR_FLRIE BIT(4) +/* Cross trigger synchronization bit */ +#define TPDA_CR_SRIE BIT(5) +/* Bits 6 ~ 12 is for atid value */ +#define TPDA_CR_ATID GENMASK(12, 6) +/* + * Channel mode bit of the packetization of CMB/MCB traffic + * 0 - raw channel mapping mode + * 1 - channel pair marking mode + */ +#define TPDA_CR_CMBCHANMODE BIT(20) + /* Aggregator port enable bit */ #define TPDA_Pn_CR_ENA BIT(0) /* Aggregator port CMB data set element size bit */ @@ -17,9 +36,6 @@ =20 #define TPDA_MAX_INPORTS 32 =20 -/* Bits 6 ~ 12 is for atid value */ -#define TPDA_CR_ATID GENMASK(12, 6) - /** * struct tpda_drvdata - specifics associated to an TPDA component * @base: memory mapped base address for this component. @@ -29,6 +45,11 @@ * @enable: enable status of the component. * @dsb_esize Record the DSB element size. * @cmb_esize Record the CMB element size. + * @trig_async: Enable/disable cross trigger synchronization sequence inte= rface. + * @trig_flag_ts: Enable/disable cross trigger FLAG packet request interfa= ce. + * @trig_freq: Enable/disable cross trigger FREQ packet request interface. + * @freq_ts: Enable/disable the timestamp for all FREQ packets. + * @cmbchan_mode: Configure the CMB/MCMB channel mode. */ struct tpda_drvdata { void __iomem *base; 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The register remains set until the flush operation is complete. Signed-off-by: Jie Gan --- .../ABI/testing/sysfs-bus-coresight-devices-tpda | 8 ++++ drivers/hwtracing/coresight/coresight-tpda.c | 45 ++++++++++++++++++= ++++ drivers/hwtracing/coresight/coresight-tpda.h | 2 + 3 files changed, 55 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/D= ocumentation/ABI/testing/sysfs-bus-coresight-devices-tpda index 735ce0e494da..c8bc7b19ab25 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda @@ -33,3 +33,11 @@ Contact: Jinlong Mao , Tao= Zhang /global_flush_req +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Set global (all ports) flush request bit. The bit remains set until= a + global flush request sequence completes. diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtraci= ng/coresight/coresight-tpda.c index 2186223ad33e..d24a9098f1b1 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -341,7 +341,52 @@ static ssize_t tpda_trig_sysfs_store(struct device *de= v, return size; } =20 +static ssize_t global_flush_req_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + unsigned long val; + + if (!drvdata->csdev->refcnt) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + val =3D readl_relaxed(drvdata->base + TPDA_CR); + /* read global_flush_req bit */ + val &=3D TPDA_CR_FLREQ; + + return sysfs_emit(buf, "%lu\n", val); +} + +static ssize_t global_flush_req_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + if (!drvdata->csdev->refcnt || !val) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + val =3D readl_relaxed(drvdata->base + TPDA_CR); + /* set global_flush_req bit */ + val |=3D TPDA_CR_FLREQ; + CS_UNLOCK(drvdata->base); + writel_relaxed(val, drvdata->base + TPDA_CR); + CS_LOCK(drvdata->base); + + return size; +} +static DEVICE_ATTR_RW(global_flush_req); + static struct attribute *tpda_attrs[] =3D { + &dev_attr_global_flush_req.attr, tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), tpda_trig_sysfs_rw(trig_freq_enable, FRIE), tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtraci= ng/coresight/coresight-tpda.h index c93732e04af2..1cc9253293ec 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -10,6 +10,8 @@ #define TPDA_Pn_CR(n) (0x004 + (n * 4)) #define TPDA_FPID_CR (0x084) =20 +/* Cross trigger global (all ports) flush request bit */ +#define TPDA_CR_FLREQ BIT(0) /* Cross trigger FREQ packets timestamp bit */ #define TPDA_CR_FREQTS BIT(2) /* Cross trigger FREQ packet request bit */ --=20 2.34.1 From nobody Mon Feb 9 20:42:01 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D68622156C for ; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7ff7e892926sm9070130b3a.66.2025.12.21.22.03.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Dec 2025 22:03:03 -0800 (PST) From: Jie Gan Date: Mon, 22 Dec 2025 14:02:23 +0800 Subject: [PATCH v6 3/4] coresight: tpda: add logic to configure TPDA_SYNCR register Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251222-add_sysfs_nodes_to_configure_tpda-v6-3-b27143d45c86@oss.qualcomm.com> References: <20251222-add_sysfs_nodes_to_configure_tpda-v6-0-b27143d45c86@oss.qualcomm.com> In-Reply-To: <20251222-add_sysfs_nodes_to_configure_tpda-v6-0-b27143d45c86@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Tingwei Zhang Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jie Gan , Tao Zhang X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766383369; l=5323; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=a3nnThULr7oV9TDmuW/OSuwqdlkJ14YmI+sHJq21AiY=; b=ndpVPu7Zd6YlW43+s07whWbRTEWZF+CoDPzG92PQb0mu7Inp2bmCKUlI33aURc/3CCiHJTUAX vpwUfCu7VTvD28boN1VUpV2kG8c/YM6QVBMm9nex1SCICZppYKuSzTQ X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Proofpoint-ORIG-GUID: nVdpODlwJKVJnf3O-xFnVPdV-DHGFFzd X-Authority-Analysis: v=2.4 cv=EvnfbCcA c=1 sm=1 tr=0 ts=6948df29 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=BPbcchGvNsiIBzbuidUA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: nVdpODlwJKVJnf3O-xFnVPdV-DHGFFzd X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA1MiBTYWx0ZWRfXxiHSCqBANAW1 FWqCjnNKZjzxqm5LIHmJphkc2A7zIbto8Nm1W4aFiaZYVC2ED36TyBPxH75ZmRbiD7s3JplxQzL uoiD2C6OopDk0SOVXTXP8sbbgI/y5tzQmcfl+Es6rVdrl3VcGf5ou6mdd04Edjvg2WbwchXX59N Z7lxW6Z2pke6wuuBbtLBvfeULUkWlAWaIiBQ/7Y7YLD3ppBKE3nVR2TtTj9/347cYb6lp7kl9Fm B3h9mZoIOczL1j2n2Ehf+DZIlKS9MZdW+jdCsc3peqLR9SJfikgxgOH7idlbGITAqUThSdDpU8r ZMY+iOhBtVXXD+vU3BQopf8ciI38DgqZkS5wWr9sRzgw+g1PxGwWCh4mw63EZ+aHBmB2+J6qOHl 5FrvSn+P+WOfxzVz1/ZT/Z5JxV0s2qAtAaoMNIxogMF213QE/XEYacWyWin/HJ/ySxSLdZ6k9Tu X7BcHhWbRU2f/r8mdZg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 phishscore=0 adultscore=0 clxscore=1015 priorityscore=1501 spamscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220052 From: Tao Zhang The TPDA_SYNC counter tracks the number of bytes transferred from the aggregator. When this count reaches the value programmed in the TPDA_SYNCR register, an ASYNC request is triggered, allowing userspace tools to accurately parse each valid packet. Signed-off-by: Tao Zhang Reviewed-by: James Clark Co-developed-by: Jie Gan Signed-off-by: Jie Gan --- .../ABI/testing/sysfs-bus-coresight-devices-tpda | 10 +++++ drivers/hwtracing/coresight/coresight-tpda.c | 46 ++++++++++++++++++= ++++ drivers/hwtracing/coresight/coresight-tpda.h | 8 ++++ 3 files changed, 64 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/D= ocumentation/ABI/testing/sysfs-bus-coresight-devices-tpda index c8bc7b19ab25..d359d90dca72 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda @@ -41,3 +41,13 @@ Contact: Jinlong Mao , Tao= Zhang /syncr_mode +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Set mode the of the syncr counter. + mode 0 - COUNT[11:0] value represents the approximate number of bytes mo= ved between two ASYNC packet requests + mode 1 - the bits COUNT[11:7] are used as a power of 2. for example, we = could insert an async packet every 8K + data by writing a value 13 to the COUNT[11:7] field. diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtraci= ng/coresight/coresight-tpda.c index d24a9098f1b1..7baa8a0965d3 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -163,6 +163,15 @@ static void tpda_enable_pre_port(struct tpda_drvdata *= drvdata) */ if (drvdata->trig_flag_ts) writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); + + /* Initialize with a value of 0 */ + val =3D 0; + if (drvdata->syncr_mode) + val |=3D TPDA_SYNCR_MODE_CTRL_MASK; + + /* Program the counter to its MAX value by default */ + val |=3D TPDA_SYNCR_COUNTER_MASK; + writel_relaxed(val, drvdata->base + TPDA_SYNCR); } =20 static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) @@ -385,8 +394,45 @@ static ssize_t global_flush_req_store(struct device *d= ev, } static DEVICE_ATTR_RW(global_flush_req); =20 +static ssize_t syncr_mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + unsigned long val, syncr_val; + + if (!drvdata->csdev->refcnt) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + syncr_val =3D readl_relaxed(drvdata->base + TPDA_SYNCR); + val =3D FIELD_GET(TPDA_SYNCR_MODE_CTRL_MASK, syncr_val); + + return sysfs_emit(buf, "%lu\n", val); +} + +static ssize_t syncr_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + /* set the mode when first enabling the device */ + drvdata->syncr_mode =3D !!val; + + return size; +} +static DEVICE_ATTR_RW(syncr_mode); + static struct attribute *tpda_attrs[] =3D { &dev_attr_global_flush_req.attr, + &dev_attr_syncr_mode.attr, tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), tpda_trig_sysfs_rw(trig_freq_enable, FRIE), tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtraci= ng/coresight/coresight-tpda.h index 1cc9253293ec..1d2de50bb9f9 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -9,6 +9,7 @@ #define TPDA_CR (0x000) #define TPDA_Pn_CR(n) (0x004 + (n * 4)) #define TPDA_FPID_CR (0x084) +#define TPDA_SYNCR (0x08C) =20 /* Cross trigger global (all ports) flush request bit */ #define TPDA_CR_FLREQ BIT(0) @@ -36,6 +37,11 @@ /* Aggregator port DSB data set element size bit */ #define TPDA_Pn_CR_DSBSIZE BIT(8) =20 +/* TPDA_SYNCR counter mask */ +#define TPDA_SYNCR_COUNTER_MASK GENMASK(11, 0) +/* TPDA_SYNCR mode control bit */ +#define TPDA_SYNCR_MODE_CTRL_MASK GENMASK(12, 12) + #define TPDA_MAX_INPORTS 32 =20 /** @@ -52,6 +58,7 @@ * @trig_freq: Enable/disable cross trigger FREQ packet request interface. * @freq_ts: Enable/disable the timestamp for all FREQ packets. * @cmbchan_mode: Configure the CMB/MCMB channel mode. + * @syncr_mode: Configure the mode for counting packets. */ struct tpda_drvdata { void __iomem *base; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7ff7e892926sm9070130b3a.66.2025.12.21.22.03.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Dec 2025 22:03:06 -0800 (PST) From: Jie Gan Date: Mon, 22 Dec 2025 14:02:24 +0800 Subject: [PATCH v6 4/4] coresight: tpda: add sysfs node to flush specific port Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251222-add_sysfs_nodes_to_configure_tpda-v6-4-b27143d45c86@oss.qualcomm.com> References: <20251222-add_sysfs_nodes_to_configure_tpda-v6-0-b27143d45c86@oss.qualcomm.com> In-Reply-To: <20251222-add_sysfs_nodes_to_configure_tpda-v6-0-b27143d45c86@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Tingwei Zhang Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jie Gan , Tao Zhang X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766383370; l=3743; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=YhrWWZcvphBxdWQngeTl1wZUK9CcQMLSULdlcXKLSig=; b=z+7ls+Ln1AZ8pgGq238ifoMXP/lvdihUzoNmklNPO93d8QMf67oRGQxs3bUS4uonJ/700+ula prTaWG3mgWLDGME3NlEWanU59KBrzbtPEWfhJW9ps3gMfEmJEVnSTZt X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Authority-Analysis: v=2.4 cv=cbbfb3DM c=1 sm=1 tr=0 ts=6948df1c cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=Uaz1Er67hVaxBR8z2rIA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA1MiBTYWx0ZWRfX5V72I3OxbnoR R8NJfVVIs22Ugk8AEO833HFx5txuQnzt46dfCtCW/8Hit4U3UJN8s39P2rWa+OF7npcJ/TY2bBW dB9HfVsNJLPKREE5MFyZ3K+Kv/mxlewca9+E1OzxiTAAn3MrY+EHvURMlLwxpV3gekB2C9O9t6g x3QBdK8XD7qGjvd5YP5JrSshm650js9Wp2DOZd8IJ0DqHvG0bGO8ZGHqSvgfIRjTF1/PsThIx5d YAuJ44YLxKt0qUwiX0/9OjXS4T26UREEBL8X5w9MosxW7SJoYu70MsY2r46rT2WctiPmCc7Jadz zgrLsa0xPPMgoC9XaqZgEtnzp/XDzEPto6nPzXOYXfy1POl1PCvvIN0k47ZJdNQbpQ5SHfwycIO EWC11vqXt5NKqQSo0okvVn08W3Hzt+TX16M6cyb1dBtLbAQXvSAVgI/T5sZNSf2FnB5rQf+6gFN IKifPc2JRzRI3xzsp0A== X-Proofpoint-GUID: 5xJhueOcDEY3w1Js6WLaftA1FeRPYGHx X-Proofpoint-ORIG-GUID: 5xJhueOcDEY3w1Js6WLaftA1FeRPYGHx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 phishscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 suspectscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220052 From: Tao Zhang Setting bit i in the TPDA_FLUSH_CR register initiates a flush request for port i, forcing the data to synchronize and be transmitted to the sink device. Signed-off-by: Tao Zhang Reviewed-by: James Clark Co-developed-by: Jie Gan Signed-off-by: Jie Gan --- .../ABI/testing/sysfs-bus-coresight-devices-tpda | 7 ++++ drivers/hwtracing/coresight/coresight-tpda.c | 40 ++++++++++++++++++= ++++ drivers/hwtracing/coresight/coresight-tpda.h | 1 + 3 files changed, 48 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/D= ocumentation/ABI/testing/sysfs-bus-coresight-devices-tpda index d359d90dca72..df8f03d4b573 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda @@ -51,3 +51,10 @@ Description: mode 0 - COUNT[11:0] value represents the approximate number of bytes mo= ved between two ASYNC packet requests mode 1 - the bits COUNT[11:7] are used as a power of 2. for example, we = could insert an async packet every 8K data by writing a value 13 to the COUNT[11:7] field. + +What: /sys/bus/coresight/devices//port_flush_req +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Configure the bit i to requests a flush operation of port i on the = TPDA. diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtraci= ng/coresight/coresight-tpda.c index 7baa8a0965d3..f79fea4fbb2c 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -430,9 +430,49 @@ static ssize_t syncr_mode_store(struct device *dev, } static DEVICE_ATTR_RW(syncr_mode); =20 +static ssize_t port_flush_req_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + unsigned long val; + + if (!drvdata->csdev->refcnt) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + val =3D readl_relaxed(drvdata->base + TPDA_FLUSH_CR); + + return sysfs_emit(buf, "0x%lx\n", val); +} + +static ssize_t port_flush_req_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + u32 val; + + if (kstrtou32(buf, 0, &val)) + return -EINVAL; + + if (!drvdata->csdev->refcnt || !val) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + CS_UNLOCK(drvdata->base); + writel_relaxed(val, drvdata->base + TPDA_FLUSH_CR); + CS_LOCK(drvdata->base); + + return size; +} +static DEVICE_ATTR_RW(port_flush_req); + static struct attribute *tpda_attrs[] =3D { &dev_attr_global_flush_req.attr, &dev_attr_syncr_mode.attr, + &dev_attr_port_flush_req.attr, tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), tpda_trig_sysfs_rw(trig_freq_enable, FRIE), tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtraci= ng/coresight/coresight-tpda.h index 1d2de50bb9f9..ef1ce2ce36a9 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -10,6 +10,7 @@ #define TPDA_Pn_CR(n) (0x004 + (n * 4)) #define TPDA_FPID_CR (0x084) #define TPDA_SYNCR (0x08C) +#define TPDA_FLUSH_CR (0x090) =20 /* Cross trigger global (all ports) flush request bit */ #define TPDA_CR_FLREQ BIT(0) --=20 2.34.1