From nobody Sat Feb 7 18:21:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D508817B43F; Sun, 21 Dec 2025 11:05:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766315120; cv=none; b=dY0lZTUxK5QPrTk6xQAzu89ZYqrLmWvYAc2aRuIH4cyt3QIi44gygWKrE3Kf9aKke1gq/QLIPhK8IhY6WrAYDc/o1G7usQ72gtLYrc7ekXcpx5RCflvLgO1G9NUHZgIzxcfYVM1X8GW5Boa8jpqXcbnyhM6/yUJe78APso5L41Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766315120; c=relaxed/simple; bh=SgM8LmbKsO/V0BAs72Ln5nuOFUP4AR1J+W8Vnt8HIOI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pciLR1jCY9JYcR6d7Ud3xz66Pq0rcoTo9v42sBF18Y/2vy9f6YSg6z29MaN22Y4rsetbV1DHY+cRsocbPVJQlbWb7Epd6wKMYDpWiTKBDmy92KPOrm8J4S9tIUcr0e0gnsDeYJh43fkrh0O+X3yq2Ph4O5MBB6KT1H8wDt8ofYc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ci0ELuQm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ci0ELuQm" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 53289C4CEFB; Sun, 21 Dec 2025 11:05:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1766315119; bh=SgM8LmbKsO/V0BAs72Ln5nuOFUP4AR1J+W8Vnt8HIOI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ci0ELuQmRBVBp53Sh75c5jhe1Fb1nawO/JXgGalOJqmBUS5EPw7EwpyP3oq868NqP 988tnyH0+H2KzxTr2l21ORdoWKhF2GoQkkaYeVR4RpYUmqqi0u1wrFmR4wJwdnGqVm QIhSbzw3osVPD5QM5DEWyxnKkFMxo7IDA9xP98TrNtS75S/FCkfBd1osamnkqsiJOc /DZAGf2Zr+cG+YxrkO0vsdHHK2x+l4boymMqetrdUyvuZXdmvDVIuQ5cXFM+BDAwzs r2TLvhO9a0FktHtqxlQeHaWXPFAxmfYdDbXncVpYJ0UIx8V6sSGZYqbqD1y0lkZC8O Hx2NDbuCg3Tvg== Received: by wens.tw (Postfix, from userid 1000) id 3ECE25FCB3; Sun, 21 Dec 2025 19:05:17 +0800 (CST) From: Chen-Yu Tsai To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mark Brown Cc: Andre Przywara , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] spi: dt-bindings: sun6i: Add compatibles for A523's SPI controllers Date: Sun, 21 Dec 2025 19:05:08 +0800 Message-ID: <20251221110513.1850535-2-wens@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251221110513.1850535-1-wens@kernel.org> References: <20251221110513.1850535-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The A523 has four SPI controllers. One of them supports MIPI DBI mode in addition to standard SPI. Compared to older generations, this newer controller now has a combined counter for the RX FIFO ad buffer levels. In older generations, the RX buffer level was a separate bitfield in the FIFO status register. In practice this difference is negligible. The buffer is mostly invisible to the implementation. If programmed I/O transfers are limited to the FIFO size, then the contents of the buffer seem to always be flushed over to the FIFO. For DMA, the DRQ trigger levels are only tied to the FIFO levels. In all other aspects, the controller is the same as the one in the R329. Add new compatible strings for the new controllers. Signed-off-by: Chen-Yu Tsai Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.= yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index 3b47b68b92cb..1b91d1566c95 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -17,6 +17,7 @@ properties: compatible: oneOf: - const: allwinner,sun50i-r329-spi + - const: allwinner,sun55i-a523-spi - const: allwinner,sun6i-a31-spi - const: allwinner,sun8i-h3-spi - items: @@ -35,6 +36,9 @@ properties: - const: allwinner,sun20i-d1-spi-dbi - const: allwinner,sun50i-r329-spi-dbi - const: allwinner,sun50i-r329-spi + - items: + - const: allwinner,sun55i-a523-spi-dbi + - const: allwinner,sun55i-a523-spi =20 reg: maxItems: 1 --=20 2.47.3 From nobody Sat Feb 7 18:21:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00F231AF4D5; Sun, 21 Dec 2025 11:05:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766315120; cv=none; b=icVMG1cBK8cl+oHAicZgLbQeiVV5cGfbzhgkxddZbOD1YL2mHbLmn5RvbPtf34YBucVsgJVvLJCUr0VHicoaL3TSKBIFsRaYVqX6hKRT9Ndvp50QMBTZ8FRUD7KY4DQ2gE9dbOZ2iMHDRj/oVneelYOAKRBmKKypG8yC7ar2DMc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766315120; c=relaxed/simple; bh=FqrfUyalVJxAzWiXrYozFMpf1r6H1cm5w3a0ofVlp2k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JmtJE4OhJR3CY8koUz89t8+SuduMeIQ9lEZus/OooxYR49KtRIDbQTMM+F+0ihAUsEbPXMQF0bQhhapgIZXEno2xcML94vNjWh6tFyIMpTZ0G0l9ad5/l2zI2iopPvH/Joi/JGV1cm1hvOsego/dYGD8+UnadGfEoxjLHd8Ig+U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jARikKwv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jARikKwv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 77246C19422; Sun, 21 Dec 2025 11:05:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1766315119; bh=FqrfUyalVJxAzWiXrYozFMpf1r6H1cm5w3a0ofVlp2k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jARikKwv1yStu2XbSDMg6WVzslk2JzGCGCiv6WE0C7SueaB5h/PAL8VrI1k6MF3rc fH8dI7Bnsv34RSdkC69NJH5Ys82ks+ADaUppeMTDaqH6ytFu/lP0/tJCwRInt4+KhE WYloa9zqCYr1RkYljUBVev2/d94MOBTKL96S8FDwEQIJbIgh+33iZuG0u2arNqcl8T 097fzZ4/p2gnmpLCB3ES7ZkE/iE0CVDYzqrTvKkfBbV0M9WtOqMl3C+SGNw3YnrTML roJ1L3ai+PTssG/ypDTFaw6TdvWFiNk0o0nBDvivfskmg/dvjgUB2U2iMkxkbI67J6 0lJFe9JMChwTQ== Received: by wens.tw (Postfix, from userid 1000) id 432215FE34; Sun, 21 Dec 2025 19:05:17 +0800 (CST) From: Chen-Yu Tsai To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mark Brown Cc: Andre Przywara , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] spi: sun6i: Support A523's SPI controllers Date: Sun, 21 Dec 2025 19:05:09 +0800 Message-ID: <20251221110513.1850535-3-wens@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251221110513.1850535-1-wens@kernel.org> References: <20251221110513.1850535-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The A523 has four SPI controllers. One of them supports MIPI DBI mode in addition to standard SPI. Compared to older generations, this newer controller now has a combined counter for the RX FIFO ad buffer levels. In older generations, the RX buffer level was a separate bitfield in the FIFO status register. In practice this difference is negligible. The buffer is mostly invisible to the implementation. If programmed I/O transfers are limited to the FIFO size, then the contents of the buffer seem to always be flushed over to the FIFO. For DMA, the DRQ trigger levels are only tied to the FIFO levels. In all other aspects, the controller is the same as the one in the R329. Support the standard SPI mode controllers using the settings for R329. DBI is left out as there currently is no infrastructure for enabling a DBI host controller, as was the case for the R329. Also fold the entry for the R329 to make the style consistent. Signed-off-by: Chen-Yu Tsai --- drivers/spi/spi-sun6i.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c index 871dfd3e77be..d1de6c99e762 100644 --- a/drivers/spi/spi-sun6i.c +++ b/drivers/spi/spi-sun6i.c @@ -795,10 +795,13 @@ static const struct sun6i_spi_cfg sun50i_r329_spi_cfg= =3D { static const struct of_device_id sun6i_spi_match[] =3D { { .compatible =3D "allwinner,sun6i-a31-spi", .data =3D &sun6i_a31_spi_cfg= }, { .compatible =3D "allwinner,sun8i-h3-spi", .data =3D &sun8i_h3_spi_cfg = }, - { - .compatible =3D "allwinner,sun50i-r329-spi", - .data =3D &sun50i_r329_spi_cfg - }, + { .compatible =3D "allwinner,sun50i-r329-spi", .data =3D &sun50i_r329_spi= _cfg }, + /* + * A523's SPI controller has a combined RX buffer + FIFO counter + * at offset 0x400, instead of split buffer count in FIFO status + * register. But in practice we only care about the FIFO level. + */ + { .compatible =3D "allwinner,sun55i-a523-spi", .data =3D &sun50i_r329_spi= _cfg }, {} }; MODULE_DEVICE_TABLE(of, sun6i_spi_match); --=20 2.47.3 From nobody Sat Feb 7 18:21:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 011AB1FECBA; Sun, 21 Dec 2025 11:05:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766315120; cv=none; b=YeD8TOebI/MPgnIwZTebYoTe4tZHJBQAYQr1iKuxCLm8wifi1FqA0ek2rRmTjmry6jbFnfdoEM8sl/HthfFvaKVs95iSDUk2i4kkwfPLZ+8rI1fe+IiDrfqgAzW5VmJzOpUkT173T+T0SJ+t26bzQiA/fK4O2X7DFk/4lWLH9vs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766315120; c=relaxed/simple; bh=joZzWHXLoIhSZSiC6PmIQjU/PLkF4PjJcggDkdZtN40=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=drAy+YwJeUTTMx4y5TMMoD2GX/A2+rjFIHIsJ7rfzrdS9wO0IlEpMnyERYODtQpSWSJlctUgle1BcqRzTstfL8hY13peINLyq+i4LT+UpfXiAqYhl+dOvcmkIC1yPq4a3pP2DvtKR3bKP4O3rqFBnJItambKjsH28HBToXrRHyc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bMDfzdUM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bMDfzdUM" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7923DC4AF09; Sun, 21 Dec 2025 11:05:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1766315119; bh=joZzWHXLoIhSZSiC6PmIQjU/PLkF4PjJcggDkdZtN40=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bMDfzdUMDd8YZFaRd6nmWU7dO9ubP94Fa17VDRxyQXqErYCpZ1Gg8tYHRsuW78KqP Zr7feOzSgZw55W++OE67S2M0W7sjy+GxWn7gthlSXGrTLQrRIfKPtOsu5ZFOLhvNz1 Pzgx07Mjf2Mcchs2iTg+8sQKGw/8AYC04XqyFu4iLdkKr9R19anbE9K6LLiJngO0YC T0pBTC80+OSO81tlvZeWCnChl9eO08P6W1WdPvHW333s8v7xrdM5cCsKlEPzYARb7v vJ+OD3OVJ5GBCqKxDo3Vr2/hl6+G39HtmkBzP3QLB9gNNURGnLJDm7erzfRb26PW9I ZE6aOVybSofVQ== Received: by wens.tw (Postfix, from userid 1000) id 5273E5FE35; Sun, 21 Dec 2025 19:05:17 +0800 (CST) From: Chen-Yu Tsai To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mark Brown Cc: Andre Przywara , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] arm64: dts: allwinner: sun55i: Add SPI controllers Date: Sun, 21 Dec 2025 19:05:10 +0800 Message-ID: <20251221110513.1850535-4-wens@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251221110513.1850535-1-wens@kernel.org> References: <20251221110513.1850535-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The A523 family SoCs have four SPI controllers. One of them also supports DBI mode. Add device nodes for all of them. Also add pinmux nodes for spi0 on the PC pins, which is commonly used for SPI-NOR boot flash. Signed-off-by: Chen-Yu Tsai --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 42dab01e3f56..9335977751e2 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -214,6 +214,43 @@ spdif_out_pi_pin: spdif-pi-pin { allwinner,pinmux =3D <2>; }; =20 + /omit-if-no-ref/ + spi0_pc_pins: spi0-pc-pins { + pins =3D "PC2", "PC4", "PC12"; + function =3D "spi0"; + allwinner,pinmux =3D <4>; + }; + + /omit-if-no-ref/ + spi0_cs0_pc_pin: spi0-cs0-pc-pin { + pins =3D "PC3"; + function =3D "spi0"; + allwinner,pinmux =3D <4>; + }; + + /omit-if-no-ref/ + spi0_cs1_pc_pin: spi0-cs1-pc-pin { + pins =3D "PC7"; + function =3D "spi0"; + allwinner,pinmux =3D <4>; + }; + + /omit-if-no-ref/ + spi0_hold_pc_pin: spi0-hold-pc-pin { + /* conflicts with eMMC D7 */ + pins =3D "PC16"; + function =3D "spi0"; + allwinner,pinmux =3D <4>; + }; + + /omit-if-no-ref/ + spi0_wp_pc_pin: spi0-wp-pc-pin { + /* conflicts with eMMC D2 */ + pins =3D "PC15"; + function =3D "spi0"; + allwinner,pinmux =3D <4>; + }; + uart0_pb_pins: uart0-pb-pins { pins =3D "PB9", "PB10"; allwinner,pinmux =3D <2>; @@ -563,6 +600,49 @@ mmc2: mmc@4022000 { #size-cells =3D <0>; }; =20 + spi0: spi@4025000 { + compatible =3D "allwinner,sun55i-a523-spi"; + reg =3D <0x04025000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names =3D "ahb", "mod"; + dmas =3D <&dma 22>, <&dma 22>; + dma-names =3D "rx", "tx"; + resets =3D <&ccu RST_BUS_SPI0>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + spi1: spi@4026000 { + compatible =3D "allwinner,sun55i-a523-spi-dbi", + "allwinner,sun55i-a523-spi"; + reg =3D <0x04026000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names =3D "ahb", "mod"; + dmas =3D <&dma 23>, <&dma 23>; + dma-names =3D "rx", "tx"; + resets =3D <&ccu RST_BUS_SPI1>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + spi2: spi@4027000 { + compatible =3D "allwinner,sun55i-a523-spi"; + reg =3D <0x04027000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; + clock-names =3D "ahb", "mod"; + dmas =3D <&dma 24>, <&dma 24>; + dma-names =3D "rx", "tx"; + resets =3D <&ccu RST_BUS_SPI2>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + usb_otg: usb@4100000 { compatible =3D "allwinner,sun55i-a523-musb", "allwinner,sun8i-a33-musb"; @@ -815,6 +895,20 @@ rtc: rtc@7090000 { #clock-cells =3D <1>; }; =20 + r_spi0: spi@7092000 { + compatible =3D "allwinner,sun55i-a523-spi"; + reg =3D <0x07092000 0x1000>; + interrupts =3D ; + clocks =3D <&r_ccu CLK_BUS_R_SPI>, <&r_ccu CLK_R_SPI>; + clock-names =3D "ahb", "mod"; + dmas =3D <&dma 53>, <&dma 53>; + dma-names =3D "rx", "tx"; + resets =3D <&r_ccu RST_BUS_R_SPI>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + mcu_ccu: clock-controller@7102000 { compatible =3D "allwinner,sun55i-a523-mcu-ccu"; reg =3D <0x7102000 0x200>; --=20 2.47.3 From nobody Sat Feb 7 18:21:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0120A207A32; Sun, 21 Dec 2025 11:05:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766315120; cv=none; b=U43utSpFTikoA6P8pgotXL/lvlGElBiCxtdovi8w5Db6dLl15op2I9+D+A/ncBv7iIISeB5IgjQcvzHKa6OLaxTp914vui3IHu9AXNiPnZca3swPR9LLkStHCoWYQcSHbdvM4S+n9tWP1IUwFIOwA1mklyzNtb52vWhCExDq1UE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766315120; c=relaxed/simple; bh=WIWtUvOCXqllobCBnum35H1c/nzaFuG9Bf2t7pmwke8=; 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Sun, 21 Dec 2025 19:05:17 +0800 (CST) From: Chen-Yu Tsai To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mark Brown Cc: Andre Przywara , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] arm64: dts: allwinner: t527: orangepi-4a: Enable SPI-NOR flash Date: Sun, 21 Dec 2025 19:05:11 +0800 Message-ID: <20251221110513.1850535-5-wens@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251221110513.1850535-1-wens@kernel.org> References: <20251221110513.1850535-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Orangepi 4A has a SPI-NOR flash connected to spi0 on the PC pins. The HOLD and WP pins are not connected, and are instead pulled up by the supply rail. Enable spi0 and add a device node for the SPI-NOR flash. Signed-off-by: Chen-Yu Tsai --- .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/ar= ch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index 9e6b21cf293e..055be86e5fae 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -400,6 +400,21 @@ &rtc { assigned-clock-rates =3D <32768>; }; =20 +&spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_pc_pins>, <&spi0_cs0_pc_pin>; + status =3D "okay"; + + flash@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <20000000>; + vcc-supply =3D <®_cldo1>; + }; +}; + &uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart0_pb_pins>; --=20 2.47.3