From nobody Sun Feb 8 17:55:14 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECFB122E3E7 for ; Sun, 21 Dec 2025 10:36:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766313415; cv=none; b=mhg239rrgSgXGFtPsY/ylmb7dYjYugAMr6NLeOKCGIhkO4Wx+du0QBQu9nAX2oC1LSHy0ic9svjmJ2Pw026ZDmUWWo4/QnL0+owmHD54fDAcP1I0gkGzl/lk15pbRc0BWDysAUu45GXP5eVX3mBoHQZt5H35T+r0AqjlKSZ4AgU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766313415; c=relaxed/simple; bh=q3Uj/NZVJjkzwSWbKVMfMAr3uA3LKimv6B/evUvOnrk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=W1Esf70s5nZidiuoxYlff0/fBvcTu7LWNsSyndnqD8U81Ih46G+4SCJ7dpP+49fdQtG9/pm0KPWT8dGsZ1C02u/fIRfo832UXWmf1VVEDChpRKvE8qZT0jdPIiJcOqpUu1Xas/lQKjDz3sqA+ZsMIAm7kO3Imx+1IjgfEz8vNN0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=GgJnqNoj; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="GgJnqNoj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1766313406; bh=q3Uj/NZVJjkzwSWbKVMfMAr3uA3LKimv6B/evUvOnrk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=GgJnqNojZ7n9yvTUF5pLxAJ8Dehkhvw22XpNW2TnnOkl5NL6k5FRsCcmIFzovLW2i O3m5MMtrr9crJ9w3keY7uZ8TaEMlo8HmT1teLOmOLheIJuK7ckfX/J4s+9a6QlXLOx /rUEO1NyzWfqMrgYLqYQtYZQJ8PbUTF6eW8X10wX65iHNuT7zYQcfeC7/FrYAuOmaL VhKnJhqdDeKXDtAJGFjhf6dzdu7lAGspVddC1aMW6ZHM5zd6Gt4QmJ5mzk9Sxc0v4I mGsdx7uCulIA5ZiFVStHZxF1lKObqLveVNxx2mk1SEwpYheyULwWIfnUo47H5EIhrh X5EZ6jUSRLOrw== Received: from localhost (unknown [82.79.138.145]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 38FBD17E12E8; Sun, 21 Dec 2025 11:36:46 +0100 (CET) From: Cristian Ciocaltea Date: Sun, 21 Dec 2025 12:36:23 +0200 Subject: [PATCH v2 1/2] phy: rockchip: samsung-hdptx: Pre-compute HDMI PLL config for 461.10125 MHz output Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251221-phy-hdptx-pll-fix-v2-1-ae4abf7f75a1@collabora.com> References: <20251221-phy-hdptx-pll-fix-v2-0-ae4abf7f75a1@collabora.com> In-Reply-To: <20251221-phy-hdptx-pll-fix-v2-0-ae4abf7f75a1@collabora.com> To: Vinod Koul , Neil Armstrong , Heiko Stuebner , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Derek Foreman X-Mailer: b4 0.14.3 Attempting to make use of a 1080p@120Hz display mode with 10 bpc RGB on my Acer XV275K P3 monitor results in a blank image. A similar behavior has been reported on Philips 279M1RV. The faulty modeline is created by drm_gtf_mode_complex() based on the following EDID entry from the Standard Timings block: GTF: 1920x1080 119.999987 Hz 16:9 138.840 kHz 368.759000 MHz It's worth noting the computed pixel clock ends up being slightly higher at 368.881000 MHz. Nevertheless, this seems to work consistently fine with 8 bpc RGB. After switching to 10 bpc, the TMDS character rate expected for the mode increases to 461.101250 MHz, as per drm_hdmi_compute_mode_clock(). Since there is no entry for this rate in the ropll_tmds_cfg table, the necessary HDMI PLL configuration parameters are calculated dynamically by rk_hdptx_phy_clk_pll_calc(). However, the resulting output rate is not quite a perfect match, i.e. 461.100000 MHz. That proved to be the actual root cause of the problem. Add a new entry to the TMDS configuration table and provide the necessary frequency division coefficients for the PHY PLL to generate the expected 461.101250 MHz output. Fixes: 9d0ec51d7c22 ("phy: rockchip: samsung-hdptx: Add high color depth ma= nagement") Tested-by: Derek Foreman Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 29de2f7bdae8..cafa618d70fd 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -414,6 +414,8 @@ struct rk_hdptx_phy { static const struct ropll_config ropll_tmds_cfg[] =3D { { 594000000ULL, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, + { 461101250ULL, 97, 97, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 71, 1, 53, 2, 6, + 35, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, { 371250000ULL, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, { 297000000ULL, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, --=20 2.51.2 From nobody Sun Feb 8 17:55:14 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F1AF244685 for ; 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Sun, 21 Dec 2025 11:36:46 +0100 (CET) From: Cristian Ciocaltea Date: Sun, 21 Dec 2025 12:36:24 +0200 Subject: [PATCH v2 2/2] phy: rockchip: samsung-hdptx: Cleanup TMDS PLL config table Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251221-phy-hdptx-pll-fix-v2-2-ae4abf7f75a1@collabora.com> References: <20251221-phy-hdptx-pll-fix-v2-0-ae4abf7f75a1@collabora.com> In-Reply-To: <20251221-phy-hdptx-pll-fix-v2-0-ae4abf7f75a1@collabora.com> To: Vinod Koul , Neil Armstrong , Heiko Stuebner , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 Drop a bunch of unused members from struct ropll_config and make the static ropll_tmds_cfg table more readable: * add a table header * sort rows by rate * convert hex values to decimal (for consistency) Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 82 +++++++------------= ---- 1 file changed, 24 insertions(+), 58 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index cafa618d70fd..e3d817e81d6d 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -336,27 +336,13 @@ struct ropll_config { u8 pms_pdiv; u8 pms_refdiv; u8 pms_sdiv; - u8 pms_iqdiv_rstn; - u8 ref_clk_sel; u8 sdm_en; - u8 sdm_rstn; - u8 sdc_frac_en; - u8 sdc_rstn; - u8 sdm_clk_div; u8 sdm_deno; u8 sdm_num_sign; u8 sdm_num; u8 sdc_n; u8 sdc_num; u8 sdc_deno; - u8 sdc_ndiv_rstn; - u8 ssc_en; - u8 ssc_fm_dev; - u8 ssc_fm_freq; - u8 ssc_clk_div_sel; - u8 ana_cpp_ctrl; - u8 ana_lpf_c_sel; - u8 cd_tx_ser_rate_sel; }; =20 struct tx_drv_ctrl { @@ -412,50 +398,30 @@ struct rk_hdptx_phy { }; =20 static const struct ropll_config ropll_tmds_cfg[] =3D { - { 594000000ULL, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, - 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 461101250ULL, 97, 97, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 71, 1, 53, 2, 6, - 35, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 371250000ULL, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, - 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 297000000ULL, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, - 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 162000000ULL, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x= 10, - 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 185625000ULL, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, - 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 154000000ULL, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1, - 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 148500000ULL, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5, - 0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 146250000ULL, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1,= 1, - 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 119000000ULL, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1,= 1, - 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 106500000ULL, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1, - 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 108000000ULL, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, - 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 85500000ULL, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1, - 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 83500000ULL, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0, - 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 92812500ULL, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, - 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 74250000ULL, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, - 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 65000000ULL, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1, - 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 50250000ULL, 84, 84, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 11, 1, 4, 5, - 4, 11, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 33750000ULL, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, = 5, - 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 40000000ULL, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, - 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 27000000ULL, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, = 0, - 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 25175000ULL, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, = 1, - 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, + /* | pms | sdm | = sdc | */ + /* rate, mdiv, mdafc, pdiv, rdiv, sdiv, en, deno, nsig, num, n, n= um, deno, */ + { 594000000ULL, 124, 124, 1, 1, 0, 1, 62, 1, 16, 5, = 0, 1, }, + { 461101250ULL, 97, 97, 1, 1, 0, 1, 71, 1, 53, 2, = 6, 35, }, + { 371250000ULL, 155, 155, 1, 1, 1, 1, 62, 1, 16, 5, = 0, 1, }, + { 297000000ULL, 124, 124, 1, 1, 1, 1, 62, 1, 16, 5, = 0, 1, }, + { 185625000ULL, 155, 155, 1, 1, 3, 1, 62, 1, 16, 5, = 0, 1, }, + { 162000000ULL, 135, 135, 1, 1, 3, 0, 4, 0, 3, 5, = 5, 16, }, + { 154000000ULL, 193, 193, 1, 1, 5, 1, 193, 1, 32, 2, = 1, 1, }, + { 148500000ULL, 123, 123, 1, 1, 3, 1, 4, 0, 3, 5, = 5, 16, }, + { 146250000ULL, 122, 122, 1, 1, 3, 1, 244, 1, 16, 2, = 1, 1, }, + { 119000000ULL, 149, 149, 1, 1, 5, 1, 149, 1, 16, 2, = 1, 1, }, + { 108000000ULL, 135, 135, 1, 1, 5, 0, 9, 0, 5, 0, = 20, 24, }, + { 106500000ULL, 89, 89, 1, 1, 3, 1, 89, 1, 16, 1, = 0, 1, }, + { 92812500ULL, 155, 155, 1, 1, 7, 1, 62, 1, 16, 5, = 0, 1, }, + { 85500000ULL, 214, 214, 1, 1, 11, 1, 214, 1, 16, 2, = 1, 1, }, + { 83500000ULL, 105, 105, 1, 1, 5, 1, 42, 1, 16, 1, = 0, 1, }, + { 74250000ULL, 124, 124, 1, 1, 7, 1, 62, 1, 16, 5, = 0, 1, }, + { 65000000ULL, 162, 162, 1, 1, 11, 1, 54, 0, 16, 4, = 1, 1, }, + { 50250000ULL, 84, 84, 1, 1, 7, 1, 11, 1, 4, 5, = 4, 11, }, + { 40000000ULL, 100, 100, 1, 1, 11, 0, 9, 0, 5, 0, = 20, 24, }, + { 33750000ULL, 112, 112, 1, 1, 15, 1, 2, 0, 1, 5, = 1, 1, }, + { 27000000ULL, 90, 90, 1, 1, 15, 0, 9, 0, 5, 0, = 20, 24, }, + { 25175000ULL, 84, 84, 1, 1, 15, 1, 168, 1, 16, 4, = 1, 1, }, }; =20 static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] =3D { --=20 2.51.2