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Sat, 20 Dec 2025 01:05:53 -0800 (PST) From: Peter Griffin Date: Sat, 20 Dec 2025 09:05:39 +0000 Subject: [PATCH v6 1/4] dt-bindings: clock: google,gs101-clock: add samsung,sysreg property as required Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251220-automatic-clocks-v6-1-36c2f276a135@linaro.org> References: <20251220-automatic-clocks-v6-0-36c2f276a135@linaro.org> In-Reply-To: <20251220-automatic-clocks-v6-0-36c2f276a135@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Sam Protsenko , Sylwester Nawrocki , Chanwoo Choi Cc: Will McVicker , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, kernel-team@android.com, Peter Griffin , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Each CMU (with the exception of cmu_top) has a corresponding sysreg bank that contains the BUSCOMPONENT_DRCG_EN and optional MEMCLK registers. The BUSCOMPONENT_DRCG_EN register enables dynamic root clock gating of bus components and MEMCLK gates the sram clock. Now the clock driver supports automatic clock mode, to fully enable dynamic root clock gating it is required to configure these registers. Update the bindings documentation so that all CMUs (with the exception of gs101-cmu-top) have samsung,sysreg as a required property. Note this is NOT an ABI break, as if the property isn't specified the clock driver will fallback to the current behaviour of not initializing the registers. The system still boots, but bus components won't benefit from dynamic root clock gating and dynamic power will be higher (which has been the case until now anyway). Additionally update the DT example to included the correct CMU size as registers in that region are used for automatic clock mode. Signed-off-by: Peter Griffin --- Changes in v5: - Invert the test for google,gs101-cmu-top (Andre) Changes in v4 - Update commit description with additional requested details (Krzysztof) Changes in v3: - Update commit description as to why the sysreg is required (Krzysztof) Changes in v2: - Update commit description regarding updated example (Andre) --- .../devicetree/bindings/clock/google,gs101-clock.yaml | 19 +++++++++++++++= +++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yam= l b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index 31e106ef913dead9a038b3b6d8b43b950587f6aa..09e679c1a9def03d53b8b493929= 911ea902a1763 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -52,6 +52,11 @@ properties: reg: maxItems: 1 =20 + samsung,sysreg: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to system registers interface. + required: - compatible - "#clock-cells" @@ -166,6 +171,18 @@ allOf: - const: bus - const: ip =20 + - if: + properties: + compatible: + contains: + const: google,gs101-cmu-top + then: + properties: + samsung,sysreg: false + else: + required: + - samsung,sysreg + additionalProperties: false =20 examples: @@ -175,7 +192,7 @@ examples: =20 cmu_top: clock-controller@1e080000 { compatible =3D "google,gs101-cmu-top"; - reg =3D <0x1e080000 0x8000>; + reg =3D <0x1e080000 0x10000>; #clock-cells =3D <1>; clocks =3D <&ext_24_5m>; clock-names =3D "oscclk"; --=20 2.52.0.351.gbe84eed79e-goog